remove clock skew introduced by BUFGs

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index 4cabd744bd9af09ff10b09f4be993047ba89da7c..0232f7698b1ec5f8ed1364b3b39f801d98200ca5 100644 (file)
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -152,14 +152,8 @@ mc_clock MC_CLK(
 \r
 );\r
 \r
-`ifdef DEVICE_CYCLONE\r
 assign W_CLK_12M = WB_CLK_12M;\r
 assign W_CLK_6M  = WB_CLK_6M;\r
-`endif\r
-`ifdef DEVICE_SPARTAN2E\r
-BUFG   BUFG_12MHz( .I(WB_CLK_12M),.O(W_CLK_12M) );\r
-BUFG   BUFG_6MHz ( .I(WB_CLK_6M ),.O(W_CLK_6M ) );\r
-`endif\r
 //---  DATA I/F -------------------------------------\r
 reg    [7:0]W_CPU_ROM_DO;\r
 wire   [7:0]W_CPU_ROM_DOB = W_CPU_ROM_CSn ? 8'h00: W_CPU_ROM_DO ;\r