From: Michael Gernoth Date: Mon, 19 May 2008 20:43:10 +0000 (+0200) Subject: fix clock for LRAM X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/commitdiff_plain/4b3ff7d86485dea579af0d8fd983a36a1e9295ea?hp=32e4dd19fc7a119e6d74fbfd246f7ab9bfd8e841 fix clock for LRAM --- diff --git a/galaxian/src/mc_bram_if.v b/galaxian/src/mc_bram_if.v index 1374c92..edbcdd0 100644 --- a/galaxian/src/mc_bram_if.v +++ b/galaxian/src/mc_bram_if.v @@ -282,7 +282,7 @@ RAMB4_S8 LRAM( .DI({3'b000,I_D}), .DO(W_D), .EN(1'b1), -.WE(~I_WE), +.WE(I_WE), .RST(1'b0) ); diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v index 5ccfbd6..36925f3 100644 --- a/galaxian/src/mc_clock.v +++ b/galaxian/src/mc_clock.v @@ -20,7 +20,8 @@ module mc_clock( I_CLK_36M, O_CLK_18M, O_CLK_12M, -O_CLK_06M +O_CLK_06M, +O_CLK_06Mn ); @@ -28,6 +29,7 @@ input I_CLK_36M; output O_CLK_18M; output O_CLK_12M; output O_CLK_06M; +output O_CLK_06Mn; // 2/3 clock divider(duty 33%) //I_CLK 1010101010101010101 @@ -68,10 +70,15 @@ assign O_CLK_18M = CLK_18M; // 1/3 clock divider (duty 50%) reg CLK_6M; +reg CLK_6Mn; + always @(posedge O_CLK_12M) begin CLK_6M <= ~CLK_6M; + CLK_6Mn <= CLK_6M; end + assign O_CLK_06M = CLK_6M; +assign O_CLK_06Mn = CLK_6Mn; endmodule diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v index 0232f76..99206f3 100644 --- a/galaxian/src/mc_top.v +++ b/galaxian/src/mc_top.v @@ -93,6 +93,7 @@ wire W_CLK_18M; wire W_CLK_36M; wire W_CLK_12M,WB_CLK_12M; wire W_CLK_6M,WB_CLK_6M; +wire W_CLK_6Mn; wire W_STARS_CLK; mc_dcm clockgen( @@ -148,7 +149,8 @@ mc_clock MC_CLK( .I_CLK_36M(W_CLK_36M), .O_CLK_18M(W_CLK_18M), .O_CLK_12M(WB_CLK_12M), -.O_CLK_06M(WB_CLK_6M) +.O_CLK_06M(WB_CLK_6M), +.O_CLK_06Mn(W_CLK_6Mn) ); @@ -443,6 +445,7 @@ mc_video MC_VID( .I_CLK_18M(W_CLK_18M), .I_CLK_12M(W_CLK_12M), .I_CLK_6M(W_CLK_6M), +.I_CLK_6Mn(W_CLK_6Mn), .I_H_CNT(W_H_CNT), .I_V_CNT(W_V_CNT), .I_H_FLIP(W_H_FLIP), diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v index a12155d..84f2397 100644 --- a/galaxian/src/mc_video.v +++ b/galaxian/src/mc_video.v @@ -29,6 +29,7 @@ module mc_video( I_CLK_18M, I_CLK_12M, I_CLK_6M, +I_CLK_6Mn, I_H_CNT, I_V_CNT, I_H_FLIP, @@ -60,6 +61,7 @@ O_COL input I_CLK_18M; input I_CLK_12M; input I_CLK_6M; +input I_CLK_6Mn; input [8:0]I_H_CNT; input [7:0]I_V_CNT; input I_H_FLIP; @@ -377,7 +379,7 @@ mc_lram LRAM( .I_CLK(I_CLK_18M), .I_ADDR(W_LRAM_A), -.I_WE(I_CLK_6M), +.I_WE(I_CLK_6Mn), .I_D(W_LRAM_DI), .O_Dn(W_LRAM_DO)