From: Michael Gernoth Date: Thu, 15 May 2008 20:29:51 +0000 (+0200) Subject: cleanup clocks X-Git-Url: https://git.zerfleddert.de/cgi-bin/gitweb.cgi/fpga-games/commitdiff_plain/c3bcc38aaf21ce2036ea66b9e5f764e6d3e7ac7f cleanup clocks --- diff --git a/galaxian/src/dcm.v b/galaxian/src/dcm.v index 64541bc..9f51aed 100644 --- a/galaxian/src/dcm.v +++ b/galaxian/src/dcm.v @@ -55,7 +55,7 @@ module mc_dcm(CLKIN_IN, .STATUS()); defparam DCM_SP_INST.CLK_FEEDBACK = "1X"; defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_SP_INST.CLKFX_DIVIDE = 27; + defparam DCM_SP_INST.CLKFX_DIVIDE = 13; defparam DCM_SP_INST.CLKFX_MULTIPLY = 4; defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM_SP_INST.CLKIN_PERIOD = 8.000; diff --git a/galaxian/src/mc_adec.v b/galaxian/src/mc_adec.v index 65525ba..2fa91fd 100644 --- a/galaxian/src/mc_adec.v +++ b/galaxian/src/mc_adec.v @@ -137,8 +137,8 @@ wire W_NMI_ONn = W_9N_Q[1]; // galaxian reg W_6S1_Q,W_6S1_Qn; reg W_6S2_Qn; -//assign O_WAITn = W_6S1_Qn; -assign O_WAITn = 1'b1 ; // No Wait +assign O_WAITn = W_6S1_Qn; +//assign O_WAITn = 1'b1 ; // No Wait always@(posedge I_CPU_CLK or negedge I_V_BLn) begin diff --git a/galaxian/src/mc_bram_if.v b/galaxian/src/mc_bram_if.v index 8476f25..1374c92 100644 --- a/galaxian/src/mc_bram_if.v +++ b/galaxian/src/mc_bram_if.v @@ -266,7 +266,7 @@ alt_ram_256_5 LRAM( .outclock(~I_CLK), .address(I_ADDR), .data(I_D), -.wren(I_WE), +.wren(~I_WE), .q(W_D) ); @@ -282,7 +282,7 @@ RAMB4_S8 LRAM( .DI({3'b000,I_D}), .DO(W_D), .EN(1'b1), -.WE(I_WE), +.WE(~I_WE), .RST(1'b0) ); diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v index 43cadb4..a88d95c 100644 --- a/galaxian/src/mc_clock.v +++ b/galaxian/src/mc_clock.v @@ -17,47 +17,61 @@ module mc_clock( -I_CLK_18M, +I_CLK_36M, +O_CLK_18M, O_CLK_12M, -O_CLK_06M, -O_CLK_06Mn +O_CLK_06M ); -input I_CLK_18M; +input I_CLK_36M; +output O_CLK_18M; output O_CLK_12M; output O_CLK_06M; -output O_CLK_06Mn; // 2/3 clock divider(duty 33%) -reg [1:0] clk_ff1,clk_ff2; //I_CLK 1010101010101010101 //c_ff10 0011110011110011110 //c_ff11 0011000011000011000 //c_ff20 0000110000110000110 //c_ff21 0110000110000110000 //O_12M 0000110110110110110 -always @(posedge I_CLK_18M) +reg [1:0] state; +reg clk_12m; +initial state = 0; +initial clk_12m = 0; + +// 2/3 clock (duty 66%) +always @(negedge I_CLK_36M) begin - clk_ff1[0] <= ~clk_ff1[0] | clk_ff1[1]; - clk_ff1[1] <= ~clk_ff1[0] & ~clk_ff1[1]; - clk_ff2[0] <= clk_ff1[0] & clk_ff1[1]; + case (state) + 2'd0: state <= 2'd1; + 2'd1: state <= 2'd2; + 2'd2: state <= 2'd0; + 2'd3: state <= 2'd0; + endcase + + if (state == 2'd2) + clk_12m = 1; + else + clk_12m = 0; end -always @(negedge I_CLK_18M) - clk_ff2[1] <= ~clk_ff1[0] & ~clk_ff1[1]; -// 2/3 clock (duty 66%) -assign O_CLK_12M = clk_ff2[0]| clk_ff2[1]; - +assign O_CLK_12M = clk_12m; + +reg CLK_18M; +always @(posedge I_CLK_36M) +begin + CLK_18M <= ~ CLK_18M; +end +assign O_CLK_18M = CLK_18M; + // 1/3 clock divider (duty 50%) -reg CLK_6M , CLK_6Mn; +reg CLK_6M; always @(posedge O_CLK_12M) begin - CLK_6Mn <= CLK_6M; CLK_6M <= ~CLK_6M; end assign O_CLK_06M = CLK_6M; -assign O_CLK_06Mn = CLK_6Mn; - -endmodule \ No newline at end of file +endmodule diff --git a/galaxian/src/mc_hv_count.v b/galaxian/src/mc_hv_count.v index aa34b40..06f3023 100644 --- a/galaxian/src/mc_hv_count.v +++ b/galaxian/src/mc_hv_count.v @@ -61,12 +61,11 @@ assign O_H_CNT = H_CNT[8:0]; //------- H_SYNC ---------------------------------------- -reg H_SYNCn; -wire H_SYNC = ~H_SYNCn; +reg H_SYNC; always@(posedge H_CNT[4] or negedge H_CNT[8]) begin - if(H_CNT[8]==1'b0) H_SYNCn <= 1'b1; - else H_SYNCn <= ~(~H_CNT[6]& H_CNT[5]); + if(H_CNT[8]==1'b0) H_SYNC <= 1'b0; + else H_SYNC <= (~H_CNT[6]& H_CNT[5]); end assign O_H_SYNC = H_SYNC; @@ -124,4 +123,4 @@ assign O_V_BL2n = V_BL2n; assign O_C_BLn = ~(~V_BLn | H_CNT[8]); -endmodule \ No newline at end of file +endmodule diff --git a/galaxian/src/mc_ld_pls.v b/galaxian/src/mc_ld_pls.v index 51a2934..01fc558 100644 --- a/galaxian/src/mc_ld_pls.v +++ b/galaxian/src/mc_ld_pls.v @@ -46,7 +46,7 @@ output O_MLDn; output O_SLDn; reg W_5C_Q; -always@(posedge I_CLK_6M) +always@(negedge I_CLK_6M) W_5C_Q <= I_H_CNT[0]; // Parts 4D @@ -83,7 +83,7 @@ logic_74xx139 U_4C1( ); reg W_4C1_Q3; -always@(negedge I_CLK_6M) // 2004-9-22 added +always@(posedge I_CLK_6M) // 2004-9-22 added W_4C1_Q3 <= W_4C1_Q[3]; reg W_4C2_B; diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v index 99a4a6a..4cabd74 100644 --- a/galaxian/src/mc_top.v +++ b/galaxian/src/mc_top.v @@ -89,7 +89,8 @@ output O_VGA_V_SYNCn; wire W_RESETn = |(~I_PSW[8:5]); //------ CLOCK GEN --------------------------- -wire I_CLK_18432M; +wire W_CLK_18M; +wire W_CLK_36M; wire W_CLK_12M,WB_CLK_12M; wire W_CLK_6M,WB_CLK_6M; wire W_STARS_CLK; @@ -97,7 +98,7 @@ wire W_STARS_CLK; mc_dcm clockgen( .CLKIN_IN(I_CLK_125M), .RST_IN(! W_RESETn), -.CLKFX_OUT(I_CLK_18432M) +.CLKFX_OUT(W_CLK_36M) ); //------ H&V COUNTER ------------------------- @@ -144,7 +145,8 @@ wire [7:0]W_VID_DO; mc_clock MC_CLK( -.I_CLK_18M(I_CLK_18432M), +.I_CLK_36M(W_CLK_36M), +.O_CLK_18M(W_CLK_18M), .O_CLK_12M(WB_CLK_12M), .O_CLK_06M(WB_CLK_6M) @@ -329,7 +331,7 @@ wire VIB_SW = died & (&on_game[1:0]); fpga_arcade_if pspad( -.CLK_18M432(I_CLK_18432M), +.CLK_18M432(W_CLK_18M), .I_RSTn(W_RESETn), .psCLK(psCLK), .psSEL(psSEL), @@ -444,7 +446,7 @@ wire [1:0]W_VID; wire [2:0]W_COL; mc_video MC_VID( -.I_CLK_18M(I_CLK_18432M), +.I_CLK_18M(W_CLK_18M), .I_CLK_12M(W_CLK_12M), .I_CLK_6M(W_CLK_6M), .I_H_CNT(W_H_CNT), @@ -503,7 +505,7 @@ wire [1:0]W_STARS_B; mc_stars MC_STARS( -.I_CLK_18M(I_CLK_18432M), +.I_CLK_18M(W_CLK_18M), `ifdef DEVICE_CYCLONE .I_CLK_6M(~WB_CLK_6M), `endif @@ -615,7 +617,7 @@ wire [7:0]W_SDAT_B; mc_sound_b MC_SOUND_B( -.I_CLK1(I_CLK_18432M), +.I_CLK1(W_CLK_18M), .I_CLK2(W_CLK_6M), .I_RSTn(rst_count[3]), .I_SW({&on_game[1:0],W_HIT,W_FIRE}), @@ -639,7 +641,7 @@ assign O_SOUND_OUT_R = W_DAC_B; dac wav_dac_a( -.Clk(I_CLK_18432M), +.Clk(W_CLK_18M), .Reset(~W_RESETn), .DACin(W_SDAT_A), .DACout(W_DAC_A) @@ -648,7 +650,7 @@ dac wav_dac_a( dac wav_dac_b( -.Clk(I_CLK_18432M), +.Clk(W_CLK_18M), .Reset(~W_RESETn), .DACin(W_SDAT_B), .DACout(W_DAC_B) diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v index c184923..a12155d 100644 --- a/galaxian/src/mc_video.v +++ b/galaxian/src/mc_video.v @@ -119,7 +119,7 @@ end mc_ld_pls LD_PLS( -.I_CLK_6M(~I_CLK_6M), +.I_CLK_6M(I_CLK_6M), .I_H_CNT(I_H_CNT), .I_3D_DI(W_3D), @@ -339,16 +339,14 @@ begin end wire [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}}; -wire W_LRAM_WE = ~I_CLK_6M; wire [4:0]W_LRAM_DI; wire [4:0]W_LRAM_DO; reg [1:0]W_RV; reg [2:0]W_RC; -wire W_1U_CLK = ~I_CLK_6M; -always@(posedge W_1U_CLK) +always@(negedge I_CLK_6M) begin W_RV <= W_LRAM_DO[1:0]; W_RC <= W_LRAM_DO[4:2]; @@ -379,7 +377,7 @@ mc_lram LRAM( .I_CLK(I_CLK_18M), .I_ADDR(W_LRAM_A), -.I_WE(W_LRAM_WE), +.I_WE(I_CLK_6M), .I_D(W_LRAM_DI), .O_Dn(W_LRAM_DO)