From fb335bc24ef27a3531085ad9a54aacd89882e41a Mon Sep 17 00:00:00 2001
From: Michael Gernoth <michael@gernoth.net>
Date: Thu, 22 May 2008 20:34:33 +0200
Subject: [PATCH] only start running, when the dcm is locked

---
 galaxian/src/mc_clock.v | 31 +++++++++++++++++++++----------
 galaxian/src/mc_top.v   |  5 ++++-
 2 files changed, 25 insertions(+), 11 deletions(-)

diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v
index 36925f3..b859754 100644
--- a/galaxian/src/mc_clock.v
+++ b/galaxian/src/mc_clock.v
@@ -18,6 +18,7 @@
 module mc_clock(
 
 I_CLK_36M,
+I_DCM_LOCKED,
 O_CLK_18M,
 O_CLK_12M,
 O_CLK_06M,
@@ -26,6 +27,7 @@ O_CLK_06Mn
 );
 
 input I_CLK_36M;
+input I_DCM_LOCKED;
 output O_CLK_18M;
 output O_CLK_12M;
 output O_CLK_06M;
@@ -46,17 +48,23 @@ initial clk_12m = 0;
 // 2/3 clock         (duty 66%)
 always @(posedge I_CLK_36M)
 begin
-   case (state)
-      2'd0: state <= 2'd1;
-      2'd1: state <= 2'd2;
-      2'd2: state <= 2'd0;
-      2'd3: state <= 2'd0;
-   endcase
+   if (I_DCM_LOCKED == 1) begin
+      case (state)
+         2'd0: state <= 2'd1;
+         2'd1: state <= 2'd2;
+         2'd2: state <= 2'd0;
+         2'd3: state <= 2'd0;
+      endcase
 
-   if (state == 2'd2)
+      if (state == 2'd2)
+         clk_12m = 0;
+      else
+         clk_12m = 1;
+   end
+   else begin
+      state <= 2'd0;
       clk_12m = 0;
-   else
-      clk_12m = 1;
+   end
 end
 
 assign O_CLK_12M = clk_12m;
@@ -64,7 +72,10 @@ assign O_CLK_12M = clk_12m;
 reg CLK_18M;
 always @(posedge I_CLK_36M)
 begin
-   CLK_18M <= ~ CLK_18M;
+   if (I_DCM_LOCKED == 1)
+      CLK_18M <= ~ CLK_18M;
+   else
+      CLK_18M <= 0;
 end
 assign O_CLK_18M = CLK_18M;
 
diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index 99206f3..c99fcd8 100644
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -95,11 +95,13 @@ wire   W_CLK_12M,WB_CLK_12M;
 wire   W_CLK_6M,WB_CLK_6M;
 wire   W_CLK_6Mn;
 wire   W_STARS_CLK;
+wire   W_DCM_LOCKED;
 
 mc_dcm clockgen(
 .CLKIN_IN(I_CLK_125M),
 .RST_IN(! W_RESETn),
-.CLKFX_OUT(W_CLK_36M)
+.CLKFX_OUT(W_CLK_36M),
+.LOCKED_OUT(W_DCM_LOCKED)
 );
 
 //------ H&V COUNTER -------------------------
@@ -147,6 +149,7 @@ wire   [7:0]W_VID_DO;
 mc_clock MC_CLK(
 
 .I_CLK_36M(W_CLK_36M),
+.I_DCM_LOCKED(W_DCM_LOCKED),
 .O_CLK_18M(W_CLK_18M),
 .O_CLK_12M(WB_CLK_12M),
 .O_CLK_06M(WB_CLK_6M),
-- 
2.39.5