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Merge branch 'master' of https://github.com/Proxmark/proxmark3
[proxmark3-svn] / armsrc / lfops.c
CommitLineData
15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
15c4dc5a 6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
15c4dc5a 12#include "apps.h"
f7e3ed82 13#include "util.h"
15c4dc5a 14#include "hitag2.h"
15#include "crc16.h"
9ab7a6c7 16#include "string.h"
7db5f1ca 17#include "lfdemod.h"
31abe49f 18#include "lfsampling.h"
f7048dc8 19#include "usb_cdc.h"
15c4dc5a 20
b2256785
MHS		 21
22/**
31abe49f
MHS		 23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
7c676e72 28 */
f7e3ed82 29void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
15c4dc5a 30{
15c4dc5a 31
ae8e8a43
MHS		 32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
b2256785 34
ae8e8a43
MHS		 35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
15c4dc5a 37
31abe49f
MHS		 38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
15c4dc5a 40
2b61c242 41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
b2256785 45
31abe49f 46 LFSetupFPGAForADC(sc.divisor, 1);
b2256785 47
ae8e8a43
MHS		 48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
15c4dc5a 50
ae8e8a43
MHS		 51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
31abe49f 56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
15c4dc5a 57
ae8e8a43
MHS		 58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
31abe49f 68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
15c4dc5a 69
ae8e8a43 70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
15c4dc5a 71
ae8e8a43 72 // now do the read
31abe49f 73 DoAcquisition_config(false);
15c4dc5a 74}
75
76/* blank r/w tag data stream
77...0000000000000000 01111111
781010101010101010101010101010101010101010101010101010101010101010
790011010010100001
8001111111
81101010101010101[0]000...
82
83[5555fe852c5555555555555555fe0000]
84*/
85void ReadTItag(void)
86{
ae8e8a43
MHS		 87 // some hardcoded initial params
88 // when we read a TI tag we sample the zerocross line at 2Mhz
89 // TI tags modulate a 1 as 16 cycles of 123.2Khz
90 // TI tags modulate a 0 as 16 cycles of 134.2Khz
ba1a299c 91 #define FSAMPLE 2000000
92 #define FREQLO 123200
93 #define FREQHI 134200
ae8e8a43 94
117d9ec2 95 signed char *dest = (signed char *)BigBuf_get_addr();
f71f4deb 96 uint16_t n = BigBuf_max_traceLen();
ae8e8a43
MHS		 97 // 128 bit shift register [shift3:shift2:shift1:shift0]
98 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
99
100 int i, cycles=0, samples=0;
101 // how many sample points fit in 16 cycles of each frequency
102 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
103 // when to tell if we're close enough to one freq or another
104 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
105
106 // TI tags charge at 134.2Khz
107 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
108 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
109
110 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
111 // connects to SSP_DIN and the SSP_DOUT logic level controls
112 // whether we're modulating the antenna (high)
113 // or listening to the antenna (low)
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
115
116 // get TI tag data into the buffer
117 AcquireTiType();
118
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120
121 for (i=0; i<n-1; i++) {
122 // count cycles by looking for lo to hi zero crossings
123 if ( (dest[i]<0) && (dest[i+1]>0) ) {
124 cycles++;
125 // after 16 cycles, measure the frequency
126 if (cycles>15) {
127 cycles=0;
128 samples=i-samples; // number of samples in these 16 cycles
129
130 // TI bits are coming to us lsb first so shift them
131 // right through our 128 bit right shift register
132 shift0 = (shift0>>1) | (shift1 << 31);
133 shift1 = (shift1>>1) | (shift2 << 31);
134 shift2 = (shift2>>1) | (shift3 << 31);
135 shift3 >>= 1;
136
137 // check if the cycles fall close to the number
138 // expected for either the low or high frequency
139 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
140 // low frequency represents a 1
141 shift3 |= (1<<31);
142 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
143 // high frequency represents a 0
144 } else {
145 // probably detected a gay waveform or noise
146 // use this as gaydar or discard shift register and start again
147 shift3 = shift2 = shift1 = shift0 = 0;
148 }
149 samples = i;
150
151 // for each bit we receive, test if we've detected a valid tag
152
153 // if we see 17 zeroes followed by 6 ones, we might have a tag
154 // remember the bits are backwards
155 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
156 // if start and end bytes match, we have a tag so break out of the loop
157 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
158 cycles = 0xF0B; //use this as a flag (ugly but whatever)
159 break;
160 }
161 }
162 }
163 }
164 }
165
166 // if flag is set we have a tag
167 if (cycles!=0xF0B) {
168 DbpString("Info: No valid tag detected.");
169 } else {
170 // put 64 bit data into shift1 and shift0
171 shift0 = (shift0>>24) | (shift1 << 8);
172 shift1 = (shift1>>24) | (shift2 << 8);
173
174 // align 16 bit crc into lower half of shift2
175 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
176
177 // if r/w tag, check ident match
ba1a299c 178 if (shift3 & (1<<15) ) {
ae8e8a43
MHS		 179 DbpString("Info: TI tag is rewriteable");
180 // only 15 bits compare, last bit of ident is not valid
ba1a299c 181 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
ae8e8a43
MHS		 182 DbpString("Error: Ident mismatch!");
183 } else {
184 DbpString("Info: TI tag ident is valid");
185 }
186 } else {
187 DbpString("Info: TI tag is readonly");
188 }
189
190 // WARNING the order of the bytes in which we calc crc below needs checking
191 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
192 // bytes in reverse or something
193 // calculate CRC
194 uint32_t crc=0;
195
196 crc = update_crc16(crc, (shift0)&0xff);
197 crc = update_crc16(crc, (shift0>>8)&0xff);
198 crc = update_crc16(crc, (shift0>>16)&0xff);
199 crc = update_crc16(crc, (shift0>>24)&0xff);
200 crc = update_crc16(crc, (shift1)&0xff);
201 crc = update_crc16(crc, (shift1>>8)&0xff);
202 crc = update_crc16(crc, (shift1>>16)&0xff);
203 crc = update_crc16(crc, (shift1>>24)&0xff);
204
205 Dbprintf("Info: Tag data: %x%08x, crc=%x",
206 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
207 if (crc != (shift2&0xffff)) {
208 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
209 } else {
210 DbpString("Info: CRC is good");
211 }
212 }
15c4dc5a 213}
214
f7e3ed82 215void WriteTIbyte(uint8_t b)
15c4dc5a 216{
ae8e8a43
MHS		 217 int i = 0;
218
219 // modulate 8 bits out to the antenna
220 for (i=0; i<8; i++)
221 {
222 if (b&(1<<i)) {
223 // stop modulating antenna
224 LOW(GPIO_SSC_DOUT);
225 SpinDelayUs(1000);
226 // modulate antenna
227 HIGH(GPIO_SSC_DOUT);
228 SpinDelayUs(1000);
229 } else {
230 // stop modulating antenna
231 LOW(GPIO_SSC_DOUT);
232 SpinDelayUs(300);
233 // modulate antenna
234 HIGH(GPIO_SSC_DOUT);
235 SpinDelayUs(1700);
236 }
237 }
15c4dc5a 238}
239
240void AcquireTiType(void)
241{
ae8e8a43
MHS		 242 int i, j, n;
243 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
244 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
ba1a299c 245 #define TIBUFLEN 1250
ae8e8a43
MHS		 246
247 // clear buffer
117d9ec2 248 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
f71f4deb 249 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
ae8e8a43
MHS		 250
251 // Set up the synchronous serial port
252 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
253 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
254
255 // steal this pin from the SSP and use it to control the modulation
256 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
257 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
258
259 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
261
262 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
263 // 48/2 = 24 MHz clock must be divided by 12
264 AT91C_BASE_SSC->SSC_CMR = 12;
265
266 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
267 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
268 AT91C_BASE_SSC->SSC_TCMR = 0;
269 AT91C_BASE_SSC->SSC_TFMR = 0;
270
271 LED_D_ON();
272
273 // modulate antenna
274 HIGH(GPIO_SSC_DOUT);
275
276 // Charge TI tag for 50ms.
277 SpinDelay(50);
278
279 // stop modulating antenna and listen
280 LOW(GPIO_SSC_DOUT);
281
282 LED_D_OFF();
283
284 i = 0;
285 for(;;) {
286 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
287 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
288 i++; if(i >= TIBUFLEN) break;
289 }
290 WDT_HIT();
291 }
292
293 // return stolen pin to SSP
294 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
295 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
296
117d9ec2 297 char *dest = (char *)BigBuf_get_addr();
ae8e8a43
MHS		 298 n = TIBUFLEN*32;
299 // unpack buffer
300 for (i=TIBUFLEN-1; i>=0; i--) {
301 for (j=0; j<32; j++) {
302 if(BigBuf[i] & (1 << j)) {
303 dest[--n] = 1;
304 } else {
305 dest[--n] = -1;
306 }
307 }
308 }
15c4dc5a 309}
310
311// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
312// if crc provided, it will be written with the data verbatim (even if bogus)
313// if not provided a valid crc will be computed from the data and written.
f7e3ed82 314void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
15c4dc5a 315{
ae8e8a43
MHS		 316 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
317 if(crc == 0) {
318 crc = update_crc16(crc, (idlo)&0xff);
319 crc = update_crc16(crc, (idlo>>8)&0xff);
320 crc = update_crc16(crc, (idlo>>16)&0xff);
321 crc = update_crc16(crc, (idlo>>24)&0xff);
322 crc = update_crc16(crc, (idhi)&0xff);
323 crc = update_crc16(crc, (idhi>>8)&0xff);
324 crc = update_crc16(crc, (idhi>>16)&0xff);
325 crc = update_crc16(crc, (idhi>>24)&0xff);
326 }
327 Dbprintf("Writing to tag: %x%08x, crc=%x",
328 (unsigned int) idhi, (unsigned int) idlo, crc);
329
330 // TI tags charge at 134.2Khz
331 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
332 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
333 // connects to SSP_DIN and the SSP_DOUT logic level controls
334 // whether we're modulating the antenna (high)
335 // or listening to the antenna (low)
336 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
337 LED_A_ON();
338
339 // steal this pin from the SSP and use it to control the modulation
340 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
341 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
342
343 // writing algorithm:
344 // a high bit consists of a field off for 1ms and field on for 1ms
345 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
346 // initiate a charge time of 50ms (field on) then immediately start writing bits
347 // start by writing 0xBB (keyword) and 0xEB (password)
348 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
349 // finally end with 0x0300 (write frame)
350 // all data is sent lsb firts
351 // finish with 15ms programming time
352
353 // modulate antenna
354 HIGH(GPIO_SSC_DOUT);
355 SpinDelay(50); // charge time
356
357 WriteTIbyte(0xbb); // keyword
358 WriteTIbyte(0xeb); // password
359 WriteTIbyte( (idlo )&0xff );
360 WriteTIbyte( (idlo>>8 )&0xff );
361 WriteTIbyte( (idlo>>16)&0xff );
362 WriteTIbyte( (idlo>>24)&0xff );
363 WriteTIbyte( (idhi )&0xff );
364 WriteTIbyte( (idhi>>8 )&0xff );
365 WriteTIbyte( (idhi>>16)&0xff );
366 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
367 WriteTIbyte( (crc )&0xff ); // crc lo
368 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
369 WriteTIbyte(0x00); // write frame lo
370 WriteTIbyte(0x03); // write frame hi
371 HIGH(GPIO_SSC_DOUT);
372 SpinDelay(50); // programming time
373
374 LED_A_OFF();
375
376 // get TI tag data into the buffer
377 AcquireTiType();
378
379 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
380 DbpString("Now use tiread to check");
15c4dc5a 381}
382
385f3987 383void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)
15c4dc5a 384{
ae8e8a43 385 int i;
117d9ec2 386 uint8_t *tab = BigBuf_get_addr();
ba1a299c 387
ae8e8a43
MHS		 388 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
389 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
ba1a299c 390
ae8e8a43 391 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
ba1a299c 392
ae8e8a43
MHS		 393 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
394 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
ba1a299c 395
e09f21fa 396 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
397 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
ba1a299c 398
ae8e8a43
MHS		 399 i = 0;
400 for(;;) {
e09f21fa 401 //wait until SSC_CLK goes HIGH
ae8e8a43 402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
f7048dc8 403 if(BUTTON_PRESS() || usb_poll()) {
ae8e8a43
MHS		 404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
ae8e8a43
MHS		 409 if (ledcontrol)
410 LED_D_ON();
952a8bb5 411
ae8e8a43
MHS		 412 if(tab[i])
413 OPEN_COIL();
414 else
415 SHORT_COIL();
952a8bb5 416
ae8e8a43
MHS		 417 if (ledcontrol)
418 LED_D_OFF();
e09f21fa 419 //wait until SSC_CLK goes LOW
ae8e8a43
MHS		 420 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
421 if(BUTTON_PRESS()) {
422 DbpString("Stopped");
423 return;
424 }
425 WDT_HIT();
e09f21fa 426 }
427
ae8e8a43
MHS		 428 i++;
429 if(i == period) {
e09f21fa 430
ae8e8a43
MHS		 431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
15c4dc5a 438}
439
15c4dc5a 440#define DEBUG_FRAME_CONTENTS 1
441void SimulateTagLowFrequencyBidir(int divisor, int t0)
442{
15c4dc5a 443}
444
e09f21fa 445// compose fc/8 fc/10 waveform (FSK2)
446static void fc(int c, int *n)
447{
117d9ec2 448 uint8_t *dest = BigBuf_get_addr();
ae8e8a43
MHS		 449 int idx;
450
451 // for when we want an fc8 pattern every 4 logical bits
452 if(c==0) {
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
e09f21fa 455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
ae8e8a43
MHS		 457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 }
e09f21fa 462
712ebfa6 463 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
ae8e8a43
MHS		 464 if(c==8) {
465 for (idx=0; idx<6; idx++) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
e09f21fa 468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
ae8e8a43
MHS		 470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475 }
476
712ebfa6 477 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
ae8e8a43
MHS		 478 if(c==10) {
479 for (idx=0; idx<5; idx++) {
e09f21fa 480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
ae8e8a43
MHS		 482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
ae8e8a43
MHS		 490 }
491 }
15c4dc5a 492}
e09f21fa 493// compose fc/X fc/Y waveform (FSKx)
712ebfa6 494static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 495{
496 uint8_t *dest = BigBuf_get_addr();
712ebfa6 497 uint8_t halfFC = fc/2;
498 uint8_t wavesPerClock = clock/fc;
499 uint8_t mod = clock % fc; //modifier
500 uint8_t modAdj = fc/mod; //how often to apply modifier
501 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
e09f21fa 502 // loop through clock - step field clock
712ebfa6 503 for (uint8_t idx=0; idx < wavesPerClock; idx++){
504 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
506 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
507 *n += fc;
e09f21fa 508 }
509 if (mod>0) (*modCnt)++;
510 if ((mod>0) && modAdjOk){ //fsk2
511 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
712ebfa6 512 memset(dest+(*n), 0, fc-halfFC);
513 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
514 *n += fc;
e09f21fa 515 }
516 }
e09f21fa 517 if (mod>0 && !modAdjOk){ //fsk1
712ebfa6 518 memset(dest+(*n), 0, mod-(mod/2));
519 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
520 *n += mod;
e09f21fa 521 }
522}
15c4dc5a 523
524// prepare a waveform pattern in the buffer based on the ID given then
525// simulate a HID tag until the button is pressed
526void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
527{
ae8e8a43
MHS		 528 int n=0, i=0;
529 /*
530 HID tag bitstream format
531 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
532 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
533 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
534 A fc8 is inserted before every 4 bits
535 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
536 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
537 */
538
539 if (hi>0xFFF) {
78f5b1a7 540 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
ae8e8a43
MHS		 541 return;
542 }
543 fc(0,&n);
544 // special start of frame marker containing invalid bit sequences
545 fc(8, &n); fc(8, &n); // invalid
546 fc(8, &n); fc(10, &n); // logical 0
547 fc(10, &n); fc(10, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549
550 WDT_HIT();
551 // manchester encode bits 43 to 32
552 for (i=11; i>=0; i--) {
553 if ((i%4)==3) fc(0,&n);
554 if ((hi>>i)&1) {
555 fc(10, &n); fc(8, &n); // low-high transition
556 } else {
557 fc(8, &n); fc(10, &n); // high-low transition
558 }
559 }
560
561 WDT_HIT();
562 // manchester encode bits 31 to 0
563 for (i=31; i>=0; i--) {
564 if ((i%4)==3) fc(0,&n);
565 if ((lo>>i)&1) {
566 fc(10, &n); fc(8, &n); // low-high transition
567 } else {
568 fc(8, &n); fc(10, &n); // high-low transition
569 }
570 }
571
572 if (ledcontrol)
573 LED_A_ON();
574 SimulateTagLowFrequency(n, 0, ledcontrol);
575
576 if (ledcontrol)
577 LED_A_OFF();
15c4dc5a 578}
eb191de6 579
e09f21fa 580// prepare a waveform pattern in the buffer based on the ID given then
581// simulate a FSK tag until the button is pressed
582// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
583void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
584{
585 int ledcontrol=1;
586 int n=0, i=0;
587 uint8_t fcHigh = arg1 >> 8;
588 uint8_t fcLow = arg1 & 0xFF;
589 uint16_t modCnt = 0;
e09f21fa 590 uint8_t clk = arg2 & 0xFF;
591 uint8_t invert = (arg2 >> 8) & 1;
712ebfa6 592
e09f21fa 593 for (i=0; i<size; i++){
594 if (BitStream[i] == invert){
595 fcAll(fcLow, &n, clk, &modCnt);
596 } else {
597 fcAll(fcHigh, &n, clk, &modCnt);
598 }
599 }
600 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
712ebfa6 601 /*Dbprintf("DEBUG: First 32:");
e09f21fa 602 uint8_t *dest = BigBuf_get_addr();
603 i=0;
604 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
605 i+=16;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
78f5b1a7 607 */
e09f21fa 608 if (ledcontrol)
609 LED_A_ON();
712ebfa6 610
78f5b1a7 611 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 612
613 if (ledcontrol)
614 LED_A_OFF();
615}
616
617// compose ask waveform for one bit(ASK)
618static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
619{
620 uint8_t *dest = BigBuf_get_addr();
712ebfa6 621 uint8_t halfClk = clock/2;
e09f21fa 622 // c = current bit 1 or 0
b41534d1 623 if (manchester==1){
712ebfa6 624 memset(dest+(*n), c, halfClk);
625 memset(dest+(*n) + halfClk, c^1, halfClk);
e09f21fa 626 } else {
712ebfa6 627 memset(dest+(*n), c, clock);
e09f21fa 628 }
712ebfa6 629 *n += clock;
e09f21fa 630}
631
b41534d1 632static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
633{
634 uint8_t *dest = BigBuf_get_addr();
635 uint8_t halfClk = clock/2;
636 if (c){
637 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
638 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
639 } else {
640 memset(dest+(*n), c ^ *phase, clock);
641 *phase ^= 1;
642 }
643
644}
645
e09f21fa 646// args clock, ask/man or askraw, invert, transmission separator
647void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
648{
649 int ledcontrol = 1;
650 int n=0, i=0;
651 uint8_t clk = (arg1 >> 8) & 0xFF;
b41534d1 652 uint8_t encoding = arg1 & 1;
e09f21fa 653 uint8_t separator = arg2 & 1;
654 uint8_t invert = (arg2 >> 8) & 1;
b41534d1 655
656 if (encoding==2){ //biphase
657 uint8_t phase=0;
e09f21fa 658 for (i=0; i<size; i++){
b41534d1 659 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
e09f21fa 660 }
b41534d1 661 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
ada339a1 662 for (i=0; i<size; i++){
b41534d1 663 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
664 }
665 }
666 } else { // ask/manchester || ask/raw
ada339a1 667 for (i=0; i<size; i++){
b41534d1 668 askSimBit(BitStream[i]^invert, &n, clk, encoding);
669 }
670 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
671 for (i=0; i<size; i++){
672 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
05446d5b 673 }
ada339a1 674 }
675 }
b41534d1 676
712ebfa6 677 if (separator==1) Dbprintf("sorry but separator option not yet available");
e09f21fa 678
b41534d1 679 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
e09f21fa 680 //DEBUG
712ebfa6 681 //Dbprintf("First 32:");
e09f21fa 682 //uint8_t *dest = BigBuf_get_addr();
683 //i=0;
684 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
685 //i+=16;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 687
688 if (ledcontrol)
689 LED_A_ON();
712ebfa6 690
78f5b1a7 691 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 692
693 if (ledcontrol)
694 LED_A_OFF();
695}
696
697//carrier can be 2,4 or 8
698static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
699{
700 uint8_t *dest = BigBuf_get_addr();
712ebfa6 701 uint8_t halfWave = waveLen/2;
702 //uint8_t idx;
e09f21fa 703 int i = 0;
704 if (phaseChg){
705 // write phase change
712ebfa6 706 memset(dest+(*n), *curPhase^1, halfWave);
707 memset(dest+(*n) + halfWave, *curPhase, halfWave);
708 *n += waveLen;
e09f21fa 709 *curPhase ^= 1;
712ebfa6 710 i += waveLen;
e09f21fa 711 }
712 //write each normal clock wave for the clock duration
713 for (; i < clk; i+=waveLen){
712ebfa6 714 memset(dest+(*n), *curPhase, halfWave);
715 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
716 *n += waveLen;
e09f21fa 717 }
718}
719
720// args clock, carrier, invert,
721void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
722{
723 int ledcontrol=1;
724 int n=0, i=0;
725 uint8_t clk = arg1 >> 8;
726 uint8_t carrier = arg1 & 0xFF;
727 uint8_t invert = arg2 & 0xFF;
78f5b1a7 728 uint8_t curPhase = 0;
e09f21fa 729 for (i=0; i<size; i++){
730 if (BitStream[i] == curPhase){
731 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
732 } else {
733 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
734 }
735 }
736 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
712ebfa6 737 //Dbprintf("DEBUG: First 32:");
738 //uint8_t *dest = BigBuf_get_addr();
739 //i=0;
740 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
741 //i+=16;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 743
744 if (ledcontrol)
745 LED_A_ON();
78f5b1a7 746 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 747
748 if (ledcontrol)
749 LED_A_OFF();
750}
751
b3b70669 752// loop to get raw HID waveform then FSK demodulate the TAG ID from it
69d88ec4
MHS		 753void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
754{
117d9ec2 755 uint8_t *dest = BigBuf_get_addr();
08ebca68 756 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
757 size_t size = 0;
ae8e8a43 758 uint32_t hi2=0, hi=0, lo=0;
a1d17964 759 int idx=0;
ae8e8a43
MHS		 760 // Configure to go in 125Khz listen mode
761 LFSetupFPGAForADC(95, true);
762
763 while(!BUTTON_PRESS()) {
764
765 WDT_HIT();
766 if (ledcontrol) LED_A_ON();
767
31abe49f 768 DoAcquisition_default(-1,true);
ae8e8a43 769 // FSK demodulator
08ebca68 770 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
a1d17964 771 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
772
ec75f5c1 773 if (idx>0 && lo>0){
ae8e8a43
MHS		 774 // final loop, go over previously decoded manchester data and decode into usable tag ID
775 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
776 if (hi2 != 0){ //extra large HID tags
777 Dbprintf("TAG ID: %x%08x%08x (%d)",
778 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
779 }else { //standard HID tags <38 bits
780 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
781 uint8_t bitlen = 0;
782 uint32_t fc = 0;
783 uint32_t cardnum = 0;
ba1a299c 784 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
ae8e8a43
MHS		 785 uint32_t lo2=0;
786 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
787 uint8_t idx3 = 1;
ba1a299c 788 while(lo2 > 1){ //find last bit set to 1 (format len bit)
789 lo2=lo2 >> 1;
ae8e8a43
MHS		 790 idx3++;
791 }
ba1a299c 792 bitlen = idx3+19;
ae8e8a43
MHS		 793 fc =0;
794 cardnum=0;
ba1a299c 795 if(bitlen == 26){
ae8e8a43
MHS		 796 cardnum = (lo>>1)&0xFFFF;
797 fc = (lo>>17)&0xFF;
798 }
ba1a299c 799 if(bitlen == 37){
ae8e8a43
MHS		 800 cardnum = (lo>>1)&0x7FFFF;
801 fc = ((hi&0xF)<<12)|(lo>>20);
802 }
ba1a299c 803 if(bitlen == 34){
ae8e8a43
MHS		 804 cardnum = (lo>>1)&0xFFFF;
805 fc= ((hi&1)<<15)|(lo>>17);
806 }
ba1a299c 807 if(bitlen == 35){
ae8e8a43
MHS		 808 cardnum = (lo>>1)&0xFFFFF;
809 fc = ((hi&1)<<11)|(lo>>21);
810 }
811 }
812 else { //if bit 38 is not set then 37 bit format is used
813 bitlen= 37;
814 fc =0;
815 cardnum=0;
816 if(bitlen==37){
817 cardnum = (lo>>1)&0x7FFFF;
818 fc = ((hi&0xF)<<12)|(lo>>20);
819 }
820 }
821 //Dbprintf("TAG ID: %x%08x (%d)",
822 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
823 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
824 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
825 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
826 }
827 if (findone){
828 if (ledcontrol) LED_A_OFF();
0892b968 829 *high = hi;
830 *low = lo;
ae8e8a43
MHS		 831 return;
832 }
833 // reset
834 hi2 = hi = lo = 0;
835 }
836 WDT_HIT();
ae8e8a43
MHS		 837 }
838 DbpString("Stopped");
839 if (ledcontrol) LED_A_OFF();
eb191de6 840}
841
66707a3b 842void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
eb191de6 843{
117d9ec2 844 uint8_t *dest = BigBuf_get_addr();
ae8e8a43 845
ec75f5c1 846 size_t size=0, idx=0;
e770c648 847 int clk=0, invert=0, errCnt=0, maxErr=20;
b41534d1 848 uint32_t hi=0;
ae8e8a43
MHS		 849 uint64_t lo=0;
850 // Configure to go in 125Khz listen mode
851 LFSetupFPGAForADC(95, true);
852
853 while(!BUTTON_PRESS()) {
854
855 WDT_HIT();
856 if (ledcontrol) LED_A_ON();
857
31abe49f 858 DoAcquisition_default(-1,true);
f71f4deb 859 size = BigBuf_max_traceLen();
ae8e8a43 860 //Dbprintf("DEBUG: Buffer got");
d91a31f9 861 //askdemod and manchester decode
e770c648 862 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
ae8e8a43
MHS		 863 //Dbprintf("DEBUG: ASK Got");
864 WDT_HIT();
865
866 if (errCnt>=0){
b41534d1 867 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
ae8e8a43 868 //Dbprintf("DEBUG: EM GOT");
b41534d1 869 if (errCnt){
870 if (size>64){
871 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
872 hi,
873 (uint32_t)(lo>>32),
874 (uint32_t)lo,
875 (uint32_t)(lo&0xFFFF),
876 (uint32_t)((lo>>16LL) & 0xFF),
877 (uint32_t)(lo & 0xFFFFFF));
878 } else {
d91a31f9 879 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
880 (uint32_t)(lo>>32),
881 (uint32_t)lo,
882 (uint32_t)(lo&0xFFFF),
883 (uint32_t)((lo>>16LL) & 0xFF),
884 (uint32_t)(lo & 0xFFFFFF));
ae8e8a43 885 }
e09f21fa 886 }
ae8e8a43
MHS		 887 if (findone){
888 if (ledcontrol) LED_A_OFF();
0892b968 889 *high=lo>>32;
890 *low=lo & 0xFFFFFFFF;
ae8e8a43
MHS		 891 return;
892 }
893 } else{
894 //Dbprintf("DEBUG: No Tag");
895 }
896 WDT_HIT();
897 lo = 0;
898 clk=0;
899 invert=0;
900 errCnt=0;
901 size=0;
ae8e8a43
MHS		 902 }
903 DbpString("Stopped");
904 if (ledcontrol) LED_A_OFF();
15c4dc5a 905}
69d88ec4 906
a1f3bb12 907void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
eb191de6 908{
117d9ec2 909 uint8_t *dest = BigBuf_get_addr();
ae8e8a43
MHS		 910 int idx=0;
911 uint32_t code=0, code2=0;
912 uint8_t version=0;
913 uint8_t facilitycode=0;
914 uint16_t number=0;
915 // Configure to go in 125Khz listen mode
916 LFSetupFPGAForADC(95, true);
917
918 while(!BUTTON_PRESS()) {
919 WDT_HIT();
920 if (ledcontrol) LED_A_ON();
31abe49f 921 DoAcquisition_default(-1,true);
ae8e8a43
MHS		 922 //fskdemod and get start index
923 WDT_HIT();
f71f4deb 924 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
ae8e8a43
MHS		 925 if (idx>0){
926 //valid tag found
927
928 //Index map
929 //0 10 20 30 40 50 60
930 //| | | | | | |
931 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
932 //-----------------------------------------------------------------------------
933 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
934 //
935 //XSF(version)facility:codeone+codetwo
936 //Handle the data
937 if(findone){ //only print binary if we are doing one
938 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
939 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
940 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
941 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
942 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
943 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
944 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
945 }
946 code = bytebits_to_byte(dest+idx,32);
947 code2 = bytebits_to_byte(dest+idx+32,32);
948 version = bytebits_to_byte(dest+idx+27,8); //14,4
949 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
950 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
951
952 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
953 // if we're only looking for one tag
954 if (findone){
955 if (ledcontrol) LED_A_OFF();
956 //LED_A_OFF();
0892b968 957 *high=code;
958 *low=code2;
ae8e8a43
MHS		 959 return;
960 }
961 code=code2=0;
962 version=facilitycode=0;
963 number=0;
964 idx=0;
965 }
966 WDT_HIT();
967 }
968 DbpString("Stopped");
969 if (ledcontrol) LED_A_OFF();
eb191de6 970}
a1f3bb12 971
2d4eae76 972/*------------------------------
973 * T5555/T5557/T5567 routines
974 *------------------------------
975 */
976
977/* T55x7 configuration register definitions */
978#define T55x7_POR_DELAY 0x00000001
979#define T55x7_ST_TERMINATOR 0x00000008
980#define T55x7_PWD 0x00000010
981#define T55x7_MAXBLOCK_SHIFT 5
982#define T55x7_AOR 0x00000200
983#define T55x7_PSKCF_RF_2 0
984#define T55x7_PSKCF_RF_4 0x00000400
985#define T55x7_PSKCF_RF_8 0x00000800
986#define T55x7_MODULATION_DIRECT 0
987#define T55x7_MODULATION_PSK1 0x00001000
988#define T55x7_MODULATION_PSK2 0x00002000
989#define T55x7_MODULATION_PSK3 0x00003000
990#define T55x7_MODULATION_FSK1 0x00004000
991#define T55x7_MODULATION_FSK2 0x00005000
992#define T55x7_MODULATION_FSK1a 0x00006000
993#define T55x7_MODULATION_FSK2a 0x00007000
994#define T55x7_MODULATION_MANCHESTER 0x00008000
995#define T55x7_MODULATION_BIPHASE 0x00010000
996#define T55x7_BITRATE_RF_8 0
997#define T55x7_BITRATE_RF_16 0x00040000
998#define T55x7_BITRATE_RF_32 0x00080000
999#define T55x7_BITRATE_RF_40 0x000C0000
1000#define T55x7_BITRATE_RF_50 0x00100000
1001#define T55x7_BITRATE_RF_64 0x00140000
1002#define T55x7_BITRATE_RF_100 0x00180000
1003#define T55x7_BITRATE_RF_128 0x001C0000
1004
1005/* T5555 (Q5) configuration register definitions */
1006#define T5555_ST_TERMINATOR 0x00000001
1007#define T5555_MAXBLOCK_SHIFT 0x00000001
1008#define T5555_MODULATION_MANCHESTER 0
1009#define T5555_MODULATION_PSK1 0x00000010
1010#define T5555_MODULATION_PSK2 0x00000020
1011#define T5555_MODULATION_PSK3 0x00000030
1012#define T5555_MODULATION_FSK1 0x00000040
1013#define T5555_MODULATION_FSK2 0x00000050
1014#define T5555_MODULATION_BIPHASE 0x00000060
1015#define T5555_MODULATION_DIRECT 0x00000070
1016#define T5555_INVERT_OUTPUT 0x00000080
1017#define T5555_PSK_RF_2 0
1018#define T5555_PSK_RF_4 0x00000100
1019#define T5555_PSK_RF_8 0x00000200
1020#define T5555_USE_PWD 0x00000400
1021#define T5555_USE_AOR 0x00000800
1022#define T5555_BITRATE_SHIFT 12
1023#define T5555_FAST_WRITE 0x00004000
1024#define T5555_PAGE_SELECT 0x00008000
1025
1026/*
1027 * Relevant times in microsecond
1028 * To compensate antenna falling times shorten the write times
1029 * and enlarge the gap ones.
1030 */
385f3987 1031#define START_GAP 30*8 // 10 - 50fc 250
1032#define WRITE_GAP 20*8 // 8 - 30fc
1033#define WRITE_0 24*8 // 16 - 31fc 24fc 192
1034#define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
1035
1036// VALUES TAKEN FROM EM4x function: SendForward
1037// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1038// WRITE_GAP = 128; (16*8)
1039// WRITE_1 = 256 32*8; (32*8)
1040
1041// These timings work for 4469/4269/4305 (with the 55*8 above)
1042// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1043
1044#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
2d4eae76 1045
1046// Write one bit to card
1047void T55xxWriteBit(int bit)
ec09b62d 1048{
ae8e8a43
MHS		 1049 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1050 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1051 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
385f3987 1052 if (!bit)
ae8e8a43
MHS		 1053 SpinDelayUs(WRITE_0);
1054 else
1055 SpinDelayUs(WRITE_1);
1056 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1057 SpinDelayUs(WRITE_GAP);
ec09b62d 1058}
1059
2d4eae76 1060// Write one card block in page 0, no lock
54a942b0 1061void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 1062{
385f3987 1063 uint32_t i = 0;
ae8e8a43 1064
385f3987 1065 // Set up FPGA, 125kHz
1066 // Wait for config.. (192+8190xPOW)x8 == 67ms
1067 LFSetupFPGAForADC(0, true);
ae8e8a43
MHS		 1068
1069 // Now start writting
1070 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1071 SpinDelayUs(START_GAP);
1072
1073 // Opcode
1074 T55xxWriteBit(1);
1075 T55xxWriteBit(0); //Page 0
1076 if (PwdMode == 1){
1077 // Pwd
1078 for (i = 0x80000000; i != 0; i >>= 1)
1079 T55xxWriteBit(Pwd & i);
1080 }
1081 // Lock bit
1082 T55xxWriteBit(0);
1083
1084 // Data
54a942b0 1085 for (i = 0x80000000; i != 0; i >>= 1)
ae8e8a43
MHS		 1086 T55xxWriteBit(Data & i);
1087
1088 // Block
1089 for (i = 0x04; i != 0; i >>= 1)
1090 T55xxWriteBit(Block & i);
1091
1092 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1093 // so wait a little more)
1094 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1095 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1096 SpinDelay(20);
1097 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
ec09b62d 1098}
1099
54a942b0 1100// Read one card block in page 0
1101void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 1102{
385f3987 1103 uint32_t i = 0;
68008fb5 1104 uint8_t *dest = BigBuf_get_addr();
1105 uint16_t bufferlength = BigBuf_max_traceLen();
1106 if ( bufferlength > T55xx_SAMPLES_SIZE )
1107 bufferlength = T55xx_SAMPLES_SIZE;
1108
1109 memset(dest, 0x80, bufferlength);
385f3987 1110
1111 // Set up FPGA, 125kHz
1112 // Wait for config.. (192+8190xPOW)x8 == 67ms
1113 LFSetupFPGAForADC(0, true);
ae8e8a43
MHS		 1114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1115 SpinDelayUs(START_GAP);
1116
1117 // Opcode
1118 T55xxWriteBit(1);
1119 T55xxWriteBit(0); //Page 0
1120 if (PwdMode == 1){
1121 // Pwd
1122 for (i = 0x80000000; i != 0; i >>= 1)
1123 T55xxWriteBit(Pwd & i);
1124 }
1125 // Lock bit
1126 T55xxWriteBit(0);
1127 // Block
1128 for (i = 0x04; i != 0; i >>= 1)
1129 T55xxWriteBit(Block & i);
1130
1131 // Turn field on to read the response
385f3987 1132 TurnReadLFOn();
ae8e8a43
MHS		 1133
1134 // Now do the acquisition
1135 i = 0;
1136 for(;;) {
1137 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1138 AT91C_BASE_SSC->SSC_THR = 0x43;
385f3987 1139 LED_D_ON();
ae8e8a43
MHS		 1140 }
1141 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1142 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
385f3987 1143 ++i;
1144 LED_D_OFF();
1145 if (i >= bufferlength) break;
ae8e8a43
MHS		 1146 }
1147 }
1148
385f3987 1149 cmd_send(CMD_ACK,0,0,0,0,0);
ae8e8a43
MHS		 1150 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1151 LED_D_OFF();
54a942b0 1152}
2d4eae76 1153
54a942b0 1154// Read card traceability data (page 1)
1155void T55xxReadTrace(void){
68008fb5 1156
385f3987 1157 uint32_t i = 0;
68008fb5 1158 uint8_t *dest = BigBuf_get_addr();
1159 uint16_t bufferlength = BigBuf_max_traceLen();
1160 if ( bufferlength > T55xx_SAMPLES_SIZE )
1161 bufferlength = T55xx_SAMPLES_SIZE;
385f3987 1162
385f3987 1163 memset(dest, 0x80, bufferlength);
1164
1165 LFSetupFPGAForADC(0, true);
ae8e8a43
MHS		 1166 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1167 SpinDelayUs(START_GAP);
1168
1169 // Opcode
1170 T55xxWriteBit(1);
1171 T55xxWriteBit(1); //Page 1
1172
1173 // Turn field on to read the response
385f3987 1174 TurnReadLFOn();
ae8e8a43
MHS		 1175
1176 // Now do the acquisition
ae8e8a43
MHS		 1177 for(;;) {
1178 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1179 AT91C_BASE_SSC->SSC_THR = 0x43;
385f3987 1180 LED_D_ON();
ae8e8a43
MHS		 1181 }
1182 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1183 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
385f3987 1184 ++i;
1185 LED_D_OFF();
1186
1187 if (i >= bufferlength) break;
1188 }
1189 }
1190
1191 cmd_send(CMD_ACK,0,0,0,0,0);
ae8e8a43
MHS		 1192 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1193 LED_D_OFF();
385f3987 1194}
1195
1196void TurnReadLFOn(){
68008fb5 1197 //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
385f3987 1198 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1199 // Give it a bit of time for the resonant antenna to settle.
1200 //SpinDelay(30);
0310364d 1201 SpinDelayUs(9*150);
54a942b0 1202}
ec09b62d 1203
54a942b0 1204/*-------------- Cloning routines -----------*/
1205// Copy HID id to card and setup block 0 config
1206void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1207{
ae8e8a43
MHS		 1208 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1209 int last_block = 0;
1210
1211 if (longFMT){
1212 // Ensure no more than 84 bits supplied
1213 if (hi2>0xFFFFF) {
1214 DbpString("Tags can only have 84 bits.");
1215 return;
1216 }
1217 // Build the 6 data blocks for supplied 84bit ID
1218 last_block = 6;
1219 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1220 for (int i=0;i<4;i++) {
1221 if (hi2 & (1<<(19-i)))
1222 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1223 else
1224 data1 |= (1<<((3-i)*2)); // 0 -> 01
1225 }
1226
1227 data2 = 0;
1228 for (int i=0;i<16;i++) {
1229 if (hi2 & (1<<(15-i)))
1230 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1231 else
1232 data2 |= (1<<((15-i)*2)); // 0 -> 01
1233 }
1234
1235 data3 = 0;
1236 for (int i=0;i<16;i++) {
1237 if (hi & (1<<(31-i)))
1238 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1239 else
1240 data3 |= (1<<((15-i)*2)); // 0 -> 01
1241 }
1242
1243 data4 = 0;
1244 for (int i=0;i<16;i++) {
1245 if (hi & (1<<(15-i)))
1246 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1247 else
1248 data4 |= (1<<((15-i)*2)); // 0 -> 01
1249 }
1250
1251 data5 = 0;
1252 for (int i=0;i<16;i++) {
1253 if (lo & (1<<(31-i)))
1254 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1255 else
1256 data5 |= (1<<((15-i)*2)); // 0 -> 01
1257 }
1258
1259 data6 = 0;
1260 for (int i=0;i<16;i++) {
1261 if (lo & (1<<(15-i)))
1262 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1263 else
1264 data6 |= (1<<((15-i)*2)); // 0 -> 01
1265 }
54a942b0 1266 }
ae8e8a43
MHS		 1267 else {
1268 // Ensure no more than 44 bits supplied
1269 if (hi>0xFFF) {
1270 DbpString("Tags can only have 44 bits.");
1271 return;
1272 }
1273
1274 // Build the 3 data blocks for supplied 44bit ID
1275 last_block = 3;
1276
1277 data1 = 0x1D000000; // load preamble
1278
1279 for (int i=0;i<12;i++) {
1280 if (hi & (1<<(11-i)))
1281 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1282 else
1283 data1 |= (1<<((11-i)*2)); // 0 -> 01
1284 }
1285
1286 data2 = 0;
1287 for (int i=0;i<16;i++) {
1288 if (lo & (1<<(31-i)))
1289 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1290 else
1291 data2 |= (1<<((15-i)*2)); // 0 -> 01
1292 }
1293
1294 data3 = 0;
1295 for (int i=0;i<16;i++) {
1296 if (lo & (1<<(15-i)))
1297 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1298 else
1299 data3 |= (1<<((15-i)*2)); // 0 -> 01
1300 }
54a942b0 1301 }
ae8e8a43
MHS		 1302
1303 LED_D_ON();
1304 // Program the data blocks for supplied ID
1305 // and the block 0 for HID format
1306 T55xxWriteBlock(data1,1,0,0);
1307 T55xxWriteBlock(data2,2,0,0);
1308 T55xxWriteBlock(data3,3,0,0);
1309
1310 if (longFMT) { // if long format there are 6 blocks
1311 T55xxWriteBlock(data4,4,0,0);
1312 T55xxWriteBlock(data5,5,0,0);
1313 T55xxWriteBlock(data6,6,0,0);
54a942b0 1314 }
ae8e8a43
MHS		 1315
1316 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1317 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1318 T55x7_MODULATION_FSK2a |
1319 last_block << T55x7_MAXBLOCK_SHIFT,
1320 0,0,0);
1321
1322 LED_D_OFF();
1323
1324 DbpString("DONE!");
2d4eae76 1325}
ec09b62d 1326
a1f3bb12 1327void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1328{
ae8e8a43
MHS		 1329 int data1=0, data2=0; //up to six blocks for long format
1330
a1f3bb12 1331 data1 = hi; // load preamble
1332 data2 = lo;
ba1a299c 1333
a1f3bb12 1334 LED_D_ON();
1335 // Program the data blocks for supplied ID
1336 // and the block 0 for HID format
1337 T55xxWriteBlock(data1,1,0,0);
1338 T55xxWriteBlock(data2,2,0,0);
ae8e8a43 1339
a1f3bb12 1340 //Config Block
1341 T55xxWriteBlock(0x00147040,0,0,0);
1342 LED_D_OFF();
ae8e8a43 1343
a1f3bb12 1344 DbpString("DONE!");
1345}
1346
2d4eae76 1347// Define 9bit header for EM410x tags
1348#define EM410X_HEADER 0x1FF
1349#define EM410X_ID_LENGTH 40
ec09b62d 1350
2d4eae76 1351void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1352{
ae8e8a43
MHS		 1353 int i, id_bit;
1354 uint64_t id = EM410X_HEADER;
1355 uint64_t rev_id = 0; // reversed ID
1356 int c_parity[4]; // column parity
1357 int r_parity = 0; // row parity
1358 uint32_t clock = 0;
1359
1360 // Reverse ID bits given as parameter (for simpler operations)
1361 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1362 if (i < 32) {
1363 rev_id = (rev_id << 1) | (id_lo & 1);
1364 id_lo >>= 1;
1365 } else {
1366 rev_id = (rev_id << 1) | (id_hi & 1);
1367 id_hi >>= 1;
1368 }
1369 }
1370
1371 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1372 id_bit = rev_id & 1;
1373
1374 if (i % 4 == 0) {
1375 // Don't write row parity bit at start of parsing
1376 if (i)
1377 id = (id << 1) | r_parity;
1378 // Start counting parity for new row
1379 r_parity = id_bit;
1380 } else {
1381 // Count row parity
1382 r_parity ^= id_bit;
1383 }
1384
1385 // First elements in column?
1386 if (i < 4)
1387 // Fill out first elements
1388 c_parity[i] = id_bit;
1389 else
1390 // Count column parity
1391 c_parity[i % 4] ^= id_bit;
1392
1393 // Insert ID bit
1394 id = (id << 1) | id_bit;
1395 rev_id >>= 1;
1396 }
1397
1398 // Insert parity bit of last row
1399 id = (id << 1) | r_parity;
1400
1401 // Fill out column parity at the end of tag
1402 for (i = 0; i < 4; ++i)
1403 id = (id << 1) | c_parity[i];
1404
1405 // Add stop bit
1406 id <<= 1;
1407
1408 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1409 LED_D_ON();
1410
1411 // Write EM410x ID
1412 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1413 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1414
1415 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1416 if (card) {
1417 // Clock rate is stored in bits 8-15 of the card value
1418 clock = (card & 0xFF00) >> 8;
1419 Dbprintf("Clock rate: %d", clock);
1420 switch (clock)
1421 {
1422 case 32:
1423 clock = T55x7_BITRATE_RF_32;
1424 break;
1425 case 16:
1426 clock = T55x7_BITRATE_RF_16;
1427 break;
1428 case 0:
1429 // A value of 0 is assumed to be 64 for backwards-compatibility
1430 // Fall through...
1431 case 64:
1432 clock = T55x7_BITRATE_RF_64;
1433 break;
1434 default:
1435 Dbprintf("Invalid clock rate: %d", clock);
1436 return;
1437 }
1438
1439 // Writing configuration for T55x7 tag
1440 T55xxWriteBlock(clock |
1441 T55x7_MODULATION_MANCHESTER |
1442 2 << T55x7_MAXBLOCK_SHIFT,
1443 0, 0, 0);
1444 }
1445 else
1446 // Writing configuration for T5555(Q5) tag
1447 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1448 T5555_MODULATION_MANCHESTER |
1449 2 << T5555_MAXBLOCK_SHIFT,
1450 0, 0, 0);
1451
1452 LED_D_OFF();
1453 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1454 (uint32_t)(id >> 32), (uint32_t)id);
2d4eae76 1455}
2414f978 1456
1457// Clone Indala 64-bit tag by UID to T55x7
1458void CopyIndala64toT55x7(int hi, int lo)
1459{
2414f978 1460
ae8e8a43
MHS		 1461 //Program the 2 data blocks for supplied 64bit UID
1462 // and the block 0 for Indala64 format
1463 T55xxWriteBlock(hi,1,0,0);
1464 T55xxWriteBlock(lo,2,0,0);
1465 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1466 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1467 T55x7_MODULATION_PSK1 |
1468 2 << T55x7_MAXBLOCK_SHIFT,
1469 0, 0, 0);
1470 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1471 // T5567WriteBlock(0x603E1042,0);
2414f978 1472
ae8e8a43 1473 DbpString("DONE!");
4118b74d 1474
ba1a299c 1475}
2414f978 1476
1477void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1478{
ae8e8a43 1479
ae8e8a43
MHS		 1480 //Program the 7 data blocks for supplied 224bit UID
1481 // and the block 0 for Indala224 format
1482 T55xxWriteBlock(uid1,1,0,0);
1483 T55xxWriteBlock(uid2,2,0,0);
1484 T55xxWriteBlock(uid3,3,0,0);
1485 T55xxWriteBlock(uid4,4,0,0);
1486 T55xxWriteBlock(uid5,5,0,0);
1487 T55xxWriteBlock(uid6,6,0,0);
1488 T55xxWriteBlock(uid7,7,0,0);
1489 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1490 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1491 T55x7_MODULATION_PSK1 |
1492 7 << T55x7_MAXBLOCK_SHIFT,
1493 0,0,0);
1494 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1495 // T5567WriteBlock(0x603E10E2,0);
1496
1497 DbpString("DONE!");
4118b74d 1498
2414f978 1499}
54a942b0 1500
1501
1502#define abs(x) ( ((x)<0) ? -(x) : (x) )
1503#define max(x,y) ( x<y ? y:x)
1504
1505int DemodPCF7931(uint8_t **outBlocks) {
d716ca2f 1506
1507 uint8_t BitStream[256] = {0x00};
5ff3c401 1508 uint8_t Blocks[8][16];
d716ca2f 1509 uint8_t *dest = BigBuf_get_addr();
f71f4deb 1510 int GraphTraceLen = BigBuf_max_traceLen();
ae8e8a43
MHS		 1511 int i, j, lastval, bitidx, half_switch;
1512 int clock = 64;
1513 int tolerance = clock / 8;
1514 int pmc, block_done;
1515 int lc, warnings = 0;
1516 int num_blocks = 0;
1517 int lmin=128, lmax=128;
1518 uint8_t dir;
1519
31abe49f 1520 LFSetupFPGAForADC(95, true);
d716ca2f 1521 DoAcquisition_default(0, true);
ae8e8a43
MHS		 1522
1523 lmin = 64;
1524 lmax = 192;
1525
1526 i = 2;
1527
1528 /* Find first local max/min */
d716ca2f 1529 if(dest[1] > dest[0]) {
ae8e8a43 1530 while(i < GraphTraceLen) {
d716ca2f 1531 if( !(dest[i] > dest[i-1]) && dest[i] > lmax)
ae8e8a43
MHS		 1532 break;
1533 i++;
1534 }
1535 dir = 0;
54a942b0 1536 }
ae8e8a43
MHS		 1537 else {
1538 while(i < GraphTraceLen) {
5ff3c401 1539 if( !(dest[i] < dest[i-1]) && dest[i] < lmin)
ae8e8a43
MHS		 1540 break;
1541 i++;
1542 }
1543 dir = 1;
54a942b0 1544 }
ae8e8a43
MHS		 1545
1546 lastval = i++;
1547 half_switch = 0;
1548 pmc = 0;
1549 block_done = 0;
1550
1551 for (bitidx = 0; i < GraphTraceLen; i++)
1552 {
d716ca2f 1553 if ( (dest[i-1] > dest[i] && dir == 1 && dest[i] > lmax) || (dest[i-1] < dest[i] && dir == 0 && dest[i] < lmin))
ae8e8a43
MHS		 1554 {
1555 lc = i - lastval;
1556 lastval = i;
1557
1558 // Switch depending on lc length:
1559 // Tolerance is 1/8 of clock rate (arbitrary)
1560 if (abs(lc-clock/4) < tolerance) {
1561 // 16T0
1562 if((i - pmc) == lc) { /* 16T0 was previous one */
1563 /* It's a PMC ! */
1564 i += (128+127+16+32+33+16)-1;
1565 lastval = i;
1566 pmc = 0;
1567 block_done = 1;
1568 }
1569 else {
1570 pmc = i;
1571 }
1572 } else if (abs(lc-clock/2) < tolerance) {
1573 // 32TO
1574 if((i - pmc) == lc) { /* 16T0 was previous one */
1575 /* It's a PMC ! */
1576 i += (128+127+16+32+33)-1;
1577 lastval = i;
1578 pmc = 0;
1579 block_done = 1;
1580 }
1581 else if(half_switch == 1) {
1582 BitStream[bitidx++] = 0;
1583 half_switch = 0;
1584 }
1585 else
1586 half_switch++;
1587 } else if (abs(lc-clock) < tolerance) {
1588 // 64TO
1589 BitStream[bitidx++] = 1;
1590 } else {
1591 // Error
1592 warnings++;
1593 if (warnings > 10)
1594 {
1595 Dbprintf("Error: too many detection errors, aborting.");
1596 return 0;
1597 }
1598 }
1599
1600 if(block_done == 1) {
1601 if(bitidx == 128) {
1602 for(j=0; j<16; j++) {
1603 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1604 64*BitStream[j*8+6]+
1605 32*BitStream[j*8+5]+
1606 16*BitStream[j*8+4]+
1607 8*BitStream[j*8+3]+
1608 4*BitStream[j*8+2]+
1609 2*BitStream[j*8+1]+
1610 BitStream[j*8];
1611 }
1612 num_blocks++;
1613 }
1614 bitidx = 0;
1615 block_done = 0;
1616 half_switch = 0;
1617 }
1618 if(i < GraphTraceLen)
1619 {
d716ca2f 1620 if (dest[i-1] > dest[i]) dir=0;
ae8e8a43
MHS		 1621 else dir = 1;
1622 }
1623 }
1624 if(bitidx==255)
1625 bitidx=0;
1626 warnings = 0;
1627 if(num_blocks == 4) break;
1628 }
1629 memcpy(outBlocks, Blocks, 16*num_blocks);
1630 return num_blocks;
54a942b0 1631}
1632
1633int IsBlock0PCF7931(uint8_t *Block) {
ae8e8a43
MHS		 1634 // Assume RFU means 0 :)
1635 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1636 return 1;
1637 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1638 return 1;
1639 return 0;
54a942b0 1640}
1641
1642int IsBlock1PCF7931(uint8_t *Block) {
ae8e8a43
MHS		 1643 // Assume RFU means 0 :)
1644 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1645 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1646 return 1;
1647
1648 return 0;
54a942b0 1649}
d91a31f9 1650
54a942b0 1651#define ALLOC 16
1652
1653void ReadPCF7931() {
ae8e8a43
MHS		 1654 uint8_t Blocks[8][17];
1655 uint8_t tmpBlocks[4][16];
1656 int i, j, ind, ind2, n;
1657 int num_blocks = 0;
1658 int max_blocks = 8;
1659 int ident = 0;
1660 int error = 0;
1661 int tries = 0;
1662
1663 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1664
1665 do {
1666 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1667 n = DemodPCF7931((uint8_t**)tmpBlocks);
1668 if(!n)
1669 error++;
1670 if(error==10 && num_blocks == 0) {
1671 Dbprintf("Error, no tag or bad tag");
1672 return;
54a942b0 1673 }
ae8e8a43
MHS		 1674 else if (tries==20 || error==10) {
1675 Dbprintf("Error reading the tag");
1676 Dbprintf("Here is the partial content");
1677 goto end;
1678 }
1679
1680 for(i=0; i<n; i++)
1681 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1682 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1683 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1684 if(!ident) {
1685 for(i=0; i<n; i++) {
1686 if(IsBlock0PCF7931(tmpBlocks[i])) {
1687 // Found block 0 ?
1688 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1689 // Found block 1!
1690 // \o/
1691 ident = 1;
1692 memcpy(Blocks[0], tmpBlocks[i], 16);
1693 Blocks[0][ALLOC] = 1;
1694 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1695 Blocks[1][ALLOC] = 1;
1696 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1697 // Debug print
1698 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1699 num_blocks = 2;
1700 // Handle following blocks
1701 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1702 if(j==n) j=0;
1703 if(j==i) break;
1704 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1705 Blocks[ind2][ALLOC] = 1;
1706 }
1707 break;
1708 }
54a942b0 1709 }
ae8e8a43
MHS		 1710 }
1711 }
1712 else {
1713 for(i=0; i<n; i++) { // Look for identical block in known blocks
1714 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1715 for(j=0; j<max_blocks; j++) {
1716 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1717 // Found an identical block
1718 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1719 if(ind2 < 0)
1720 ind2 = max_blocks;
1721 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1722 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1723 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1724 Blocks[ind2][ALLOC] = 1;
1725 num_blocks++;
1726 if(num_blocks == max_blocks) goto end;
1727 }
1728 }
1729 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1730 if(ind2 > max_blocks)
1731 ind2 = 0;
1732 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1733 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1734 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1735 Blocks[ind2][ALLOC] = 1;
1736 num_blocks++;
1737 if(num_blocks == max_blocks) goto end;
1738 }
1739 }
1740 }
1741 }
54a942b0 1742 }
54a942b0 1743 }
54a942b0 1744 }
ae8e8a43
MHS		 1745 tries++;
1746 if (BUTTON_PRESS()) return;
1747 } while (num_blocks != max_blocks);
e09f21fa 1748 end:
ae8e8a43
MHS		 1749 Dbprintf("-----------------------------------------");
1750 Dbprintf("Memory content:");
1751 Dbprintf("-----------------------------------------");
1752 for(i=0; i<max_blocks; i++) {
1753 if(Blocks[i][ALLOC]==1)
1754 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1755 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1756 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1757 else
1758 Dbprintf("<missing block %d>", i);
1759 }
1760 Dbprintf("-----------------------------------------");
1761
1762 return ;
54a942b0 1763}
1764
1765
1766//-----------------------------------
1767// EM4469 / EM4305 routines
1768//-----------------------------------
1769#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1770#define FWD_CMD_WRITE 0xA
1771#define FWD_CMD_READ 0x9
1772#define FWD_CMD_DISABLE 0x5
1773
1774
1775uint8_t forwardLink_data[64]; //array of forwarded bits
1776uint8_t * forward_ptr; //ptr for forward message preparation
1777uint8_t fwd_bit_sz; //forwardlink bit counter
1778uint8_t * fwd_write_ptr; //forwardlink bit pointer
1779
1780//====================================================================
1781// prepares command bits
1782// see EM4469 spec
1783//====================================================================
1784//--------------------------------------------------------------------
1785uint8_t Prepare_Cmd( uint8_t cmd ) {
ae8e8a43
MHS		 1786 //--------------------------------------------------------------------
1787
1788 *forward_ptr++ = 0; //start bit
1789 *forward_ptr++ = 0; //second pause for 4050 code
1790
1791 *forward_ptr++ = cmd;
1792 cmd >>= 1;
1793 *forward_ptr++ = cmd;
1794 cmd >>= 1;
1795 *forward_ptr++ = cmd;
1796 cmd >>= 1;
1797 *forward_ptr++ = cmd;
1798
1799 return 6; //return number of emited bits
54a942b0 1800}
1801
1802//====================================================================
1803// prepares address bits
1804// see EM4469 spec
1805//====================================================================
1806
1807//--------------------------------------------------------------------
1808uint8_t Prepare_Addr( uint8_t addr ) {
ae8e8a43
MHS		 1809 //--------------------------------------------------------------------
1810
1811 register uint8_t line_parity;
1812
1813 uint8_t i;
1814 line_parity = 0;
1815 for(i=0;i<6;i++) {
1816 *forward_ptr++ = addr;
1817 line_parity ^= addr;
1818 addr >>= 1;
1819 }
1820
1821 *forward_ptr++ = (line_parity & 1);
1822
1823 return 7; //return number of emited bits
54a942b0 1824}
1825
1826//====================================================================
1827// prepares data bits intreleaved with parity bits
1828// see EM4469 spec
1829//====================================================================
1830
1831//--------------------------------------------------------------------
1832uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
ae8e8a43
MHS		 1833 //--------------------------------------------------------------------
1834
1835 register uint8_t line_parity;
1836 register uint8_t column_parity;
1837 register uint8_t i, j;
1838 register uint16_t data;
1839
1840 data = data_low;
1841 column_parity = 0;
1842
1843 for(i=0; i<4; i++) {
1844 line_parity = 0;
1845 for(j=0; j<8; j++) {
1846 line_parity ^= data;
1847 column_parity ^= (data & 1) << j;
1848 *forward_ptr++ = data;
1849 data >>= 1;
1850 }
1851 *forward_ptr++ = line_parity;
1852 if(i == 1)
1853 data = data_hi;
1854 }
1855
54a942b0 1856 for(j=0; j<8; j++) {
ae8e8a43
MHS		 1857 *forward_ptr++ = column_parity;
1858 column_parity >>= 1;
54a942b0 1859 }
ae8e8a43
MHS		 1860 *forward_ptr = 0;
1861
1862 return 45; //return number of emited bits
54a942b0 1863}
1864
1865//====================================================================
1866// Forward Link send function
1867// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1868// fwd_bit_count set with number of bits to be sent
1869//====================================================================
1870void SendForward(uint8_t fwd_bit_count) {
ae8e8a43
MHS		 1871
1872 fwd_write_ptr = forwardLink_data;
1873 fwd_bit_sz = fwd_bit_count;
1874
1875 LED_D_ON();
1876
1877 //Field on
1878 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1879 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1880 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1881
1882 // Give it a bit of time for the resonant antenna to settle.
1883 // And for the tag to fully power up
1884 SpinDelay(150);
1885
1886 // force 1st mod pulse (start gap must be longer for 4305)
1887 fwd_bit_sz--; //prepare next bit modulation
1888 fwd_write_ptr++;
1889 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1890 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1891 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1892 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1893 SpinDelayUs(16*8); //16 cycles on (8us each)
1894
1895 // now start writting
1896 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1897 if(((*fwd_write_ptr++) & 1) == 1)
1898 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1899 else {
1900 //These timings work for 4469/4269/4305 (with the 55*8 above)
1901 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1902 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1903 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1904 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1905 SpinDelayUs(9*8); //16 cycles on (8us each)
1906 }
54a942b0 1907 }
54a942b0 1908}
1909
1910void EM4xLogin(uint32_t Password) {
ae8e8a43
MHS		 1911
1912 uint8_t fwd_bit_count;
1913
1914 forward_ptr = forwardLink_data;
1915 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1916 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1917
1918 SendForward(fwd_bit_count);
1919
1920 //Wait for command to complete
1921 SpinDelay(20);
1922
54a942b0 1923}
1924
1925void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
ae8e8a43 1926
385f3987 1927 uint8_t *dest = BigBuf_get_addr();
1928 uint16_t bufferlength = BigBuf_max_traceLen();
1929 uint32_t i = 0;
1930
1931 // Clear destination buffer before sending the command 0x80 = average.
1932 memset(dest, 0x80, bufferlength);
1933
ae8e8a43 1934 uint8_t fwd_bit_count;
ae8e8a43
MHS		 1935
1936 //If password mode do login
1937 if (PwdMode == 1) EM4xLogin(Pwd);
1938
1939 forward_ptr = forwardLink_data;
1940 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1941 fwd_bit_count += Prepare_Addr( Address );
1942
ae8e8a43
MHS		 1943 // Connect the A/D to the peak-detected low-frequency path.
1944 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1945 // Now set up the SSC to get the ADC samples that are now streaming at us.
1946 FpgaSetupSsc();
1947
1948 SendForward(fwd_bit_count);
1949
1950 // Now do the acquisition
1951 i = 0;
1952 for(;;) {
1953 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1954 AT91C_BASE_SSC->SSC_THR = 0x43;
1955 }
1956 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1957 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
385f3987 1958 ++i;
1959 if (i >= bufferlength) break;
1960 }
1961 }
1962
1963 cmd_send(CMD_ACK,0,0,0,0,0);
ae8e8a43
MHS		 1964 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1965 LED_D_OFF();
54a942b0 1966}
1967
1968void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
ae8e8a43
MHS		 1969
1970 uint8_t fwd_bit_count;
1971
1972 //If password mode do login
1973 if (PwdMode == 1) EM4xLogin(Pwd);
1974
1975 forward_ptr = forwardLink_data;
1976 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1977 fwd_bit_count += Prepare_Addr( Address );
1978 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1979
1980 SendForward(fwd_bit_count);
1981
1982 //Wait for write to complete
1983 SpinDelay(20);
1984 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1985 LED_D_OFF();
54a942b0 1986}
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