| 6658905f |
1 | //-----------------------------------------------------------------------------\r |
| 2 | // Incomplete register definitions for the AT91SAM7S128 chip.\r |
| 3 | // Jonathan Westhues, Jul 2005\r |
| 4 | //-----------------------------------------------------------------------------\r |
| 5 | \r |
| 6 | #ifndef __AT91SAM7S128_H\r |
| 7 | #define __AT91SAM7S128_H\r |
| 8 | \r |
| 9 | #define REG(x) (*(volatile unsigned long *)(x))\r |
| 10 | \r |
| 11 | //-------------\r |
| 12 | // Peripheral IDs\r |
| 13 | \r |
| 14 | #define PERIPH_AIC_FIQ 0\r |
| 15 | #define PERIPH_SYSIRQ 1\r |
| 16 | #define PERIPH_PIOA 2\r |
| 17 | #define PERIPH_ADC 4\r |
| 18 | #define PERIPH_SPI 5\r |
| 19 | #define PERIPH_US0 6\r |
| 20 | #define PERIPH_US1 7\r |
| 21 | #define PERIPH_SSC 8\r |
| 22 | #define PERIPH_TWI 9\r |
| 23 | #define PERIPH_PWMC 10\r |
| 24 | #define PERIPH_UDP 11\r |
| 25 | #define PERIPH_TC0 12\r |
| 26 | #define PERIPH_TC1 13\r |
| 27 | #define PERIPH_TC2 14\r |
| 28 | #define PERIPH_AIC_IRQ0 30\r |
| 29 | #define PERIPH_AIC_IRQ1 31\r |
| 30 | \r |
| 31 | //-------------\r |
| 32 | // Reset Controller\r |
| 33 | \r |
| 34 | #define RSTC_BASE (0xfffffd00)\r |
| 35 | \r |
| 36 | #define RSTC_CONTROL REG(RSTC_BASE+0x00)\r |
| 37 | \r |
| 38 | #define RST_CONTROL_KEY (0xa5<<24)\r |
| 39 | #define RST_CONTROL_PROCESSOR_RESET (1<<0)\r |
| 40 | \r |
| 41 | //-------------\r |
| 42 | // PWM Controller\r |
| 43 | \r |
| 44 | #define PWM_BASE (0xfffcc000)\r |
| 45 | \r |
| 46 | #define PWM_MODE REG(PWM_BASE+0x00)\r |
| 47 | #define PWM_ENABLE REG(PWM_BASE+0x04)\r |
| 48 | #define PWM_DISABLE REG(PWM_BASE+0x08)\r |
| 49 | #define PWM_STATUS REG(PWM_BASE+0x0c)\r |
| 50 | #define PWM_INTERRUPT_ENABLE REG(PWM_BASE+0x10)\r |
| 51 | #define PWM_INTERRUPT_DISABLE REG(PWM_BASE+0x14)\r |
| 52 | #define PWM_INTERRUPT_MASK REG(PWM_BASE+0x18)\r |
| 53 | #define PWM_INTERRUPT_STATUS REG(PWM_BASE+0x1c)\r |
| 54 | #define PWM_CH_MODE(x) REG(PWM_BASE+0x200+((x)*0x20))\r |
| 55 | #define PWM_CH_DUTY_CYCLE(x) REG(PWM_BASE+0x204+((x)*0x20))\r |
| 56 | #define PWM_CH_PERIOD(x) REG(PWM_BASE+0x208+((x)*0x20))\r |
| 57 | #define PWM_CH_COUNTER(x) REG(PWM_BASE+0x20c+((x)*0x20))\r |
| 58 | #define PWM_CH_UPDATE(x) REG(PWM_BASE+0x210+((x)*0x20))\r |
| 59 | \r |
| 60 | #define PWM_MODE_DIVA(x) ((x)<<0)\r |
| 61 | #define PWM_MODE_PREA(x) ((x)<<8)\r |
| 62 | #define PWM_MODE_DIVB(x) ((x)<<16)\r |
| 63 | #define PWM_MODE_PREB(x) ((x)<<24)\r |
| 64 | \r |
| 65 | #define PWM_CHANNEL(x) (1<<(x))\r |
| 66 | \r |
| 67 | #define PWM_CH_MODE_PRESCALER(x) ((x)<<0)\r |
| 68 | #define PWM_CH_MODE_PERIOD_CENTER_ALIGNED (1<<8)\r |
| 69 | #define PWM_CH_MODE_POLARITY_STARTS_HIGH (1<<9)\r |
| 70 | #define PWM_CH_MODE_UPDATE_UPDATES_PERIOD (1<<10)\r |
| 71 | \r |
| 72 | //-------------\r |
| 73 | // Debug Unit\r |
| 74 | \r |
| 75 | #define DBG_BASE (0xfffff200)\r |
| 76 | \r |
| 77 | #define DBGU_CR REG(DBG_BASE+0x0000)\r |
| 78 | #define DBGU_MR REG(DBG_BASE+0x0004)\r |
| 79 | #define DBGU_IER REG(DBG_BASE+0x0008)\r |
| 80 | #define DBGU_IDR REG(DBG_BASE+0x000C)\r |
| 81 | #define DBGU_IMR REG(DBG_BASE+0x0010)\r |
| 82 | #define DBGU_SR REG(DBG_BASE+0x0014)\r |
| 83 | #define DBGU_RHR REG(DBG_BASE+0x0018)\r |
| 84 | #define DBGU_THR REG(DBG_BASE+0x001C)\r |
| 85 | #define DBGU_BRGR REG(DBG_BASE+0x0020)\r |
| 86 | #define DBGU_CIDR REG(DBG_BASE+0x0040)\r |
| 87 | #define DBGU_EXID REG(DBG_BASE+0x0044)\r |
| 88 | #define DBGU_FNR REG(DBG_BASE+0x0048)\r |
| 89 | \r |
| 90 | //-------------\r |
| 91 | // Embedded Flash Controller\r |
| 92 | \r |
| 93 | #define MC_BASE (0xffffff00)\r |
| 94 | \r |
| 95 | #define MC_FLASH_MODE0 REG(MC_BASE+0x60)\r |
| 96 | #define MC_FLASH_COMMAND REG(MC_BASE+0x64)\r |
| 97 | #define MC_FLASH_STATUS REG(MC_BASE+0x68)\r |
| 98 | #define MC_FLASH_MODE1 REG(MC_BASE+0x70)\r |
| 99 | \r |
| 100 | #define MC_FLASH_MODE_READY_INTERRUPT_ENABLE (1<<0)\r |
| 101 | #define MC_FLASH_MODE_LOCK_INTERRUPT_ENABLE (1<<2)\r |
| 102 | #define MC_FLASH_MODE_PROG_ERROR_INTERRUPT_ENABLE (1<<3)\r |
| 103 | #define MC_FLASH_MODE_NO_ERASE_BEFORE_PROGRAMMING (1<<7)\r |
| 104 | #define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)\r |
| 105 | #define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)\r |
| 106 | \r |
| 107 | #define MC_FLASH_COMMAND_FCMD(x) ((x)<<0)\r |
| 108 | #define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)\r |
| 109 | #define MC_FLASH_COMMAND_KEY ((0x5a)<<24)\r |
| 110 | \r |
| 111 | #define FCMD_NOP 0x0\r |
| 112 | #define FCMD_WRITE_PAGE 0x1\r |
| 113 | #define FCMD_SET_LOCK_BIT 0x2\r |
| 114 | #define FCMD_WRITE_PAGE_LOCK 0x3\r |
| 115 | #define FCMD_CLEAR_LOCK_BIT 0x4\r |
| 116 | #define FCMD_ERASE_ALL 0x8\r |
| 117 | #define FCMD_SET_GP_NVM_BIT 0xb\r |
| 118 | #define FCMD_SET_SECURITY_BIT 0xf\r |
| 119 | \r |
| 120 | #define MC_FLASH_STATUS_READY (1<<0)\r |
| 121 | #define MC_FLASH_STATUS_LOCK_ERROR (1<<2)\r |
| 122 | #define MC_FLASH_STATUS_PROGRAMMING_ERROR (1<<3)\r |
| 123 | #define MC_FLASH_STATUS_SECURITY_BIT_ACTIVE (1<<4)\r |
| 124 | #define MC_FLASH_STATUS_GP_NVM_ACTIVE_0 (1<<8)\r |
| 125 | #define MC_FLASH_STATUS_GP_NVM_ACTIVE_1 (1<<9)\r |
| 126 | #define MC_FLASH_STATUS_LOCK_ACTIVE(x) (1<<((x)+16))\r |
| 127 | \r |
| 128 | #define FLASH_PAGE_SIZE_BYTES 256\r |
| 129 | #define FLASH_PAGE_COUNT 512\r |
| 130 | \r |
| 131 | //-------------\r |
| 132 | // Watchdog Timer - 12 bit down counter, uses slow clock divided by 128 as source\r |
| 133 | \r |
| 134 | #define WDT_BASE (0xfffffd40)\r |
| 135 | \r |
| 136 | #define WDT_CONTROL REG(WDT_BASE+0x00)\r |
| 137 | #define WDT_MODE REG(WDT_BASE+0x04)\r |
| 138 | #define WDT_STATUS REG(WDT_BASE+0x08)\r |
| 139 | \r |
| 140 | #define WDT_HIT() WDT_CONTROL = 0xa5000001\r |
| 141 | \r |
| 142 | #define WDT_MODE_COUNT(x) ((x)<<0)\r |
| 143 | #define WDT_MODE_INTERRUPT_ON_EVENT (1<<12)\r |
| 144 | #define WDT_MODE_RESET_ON_EVENT_ENABLE (1<<13)\r |
| 145 | #define WDT_MODE_RESET_ON_EVENT (1<<14)\r |
| 146 | #define WDT_MODE_WATCHDOG_DELTA(x) ((x)<<16)\r |
| 147 | #define WDT_MODE_HALT_IN_DEBUG_MODE (1<<28)\r |
| 148 | #define WDT_MODE_HALT_IN_IDLE_MODE (1<<29)\r |
| 149 | #define WDT_MODE_DISABLE (1<<15)\r |
| 150 | \r |
| 151 | //-------------\r |
| 152 | // Parallel Input/Output Controller\r |
| 153 | \r |
| 154 | #define PIO_BASE (0xfffff400)\r |
| 155 | \r |
| 156 | #define PIO_ENABLE REG(PIO_BASE+0x000)\r |
| 157 | #define PIO_DISABLE REG(PIO_BASE+0x004)\r |
| 158 | #define PIO_STATUS REG(PIO_BASE+0x008)\r |
| 159 | #define PIO_OUTPUT_ENABLE REG(PIO_BASE+0x010)\r |
| 160 | #define PIO_OUTPUT_DISABLE REG(PIO_BASE+0x014)\r |
| 161 | #define PIO_OUTPUT_STATUS REG(PIO_BASE+0x018)\r |
| 162 | #define PIO_GLITCH_ENABLE REG(PIO_BASE+0x020)\r |
| 163 | #define PIO_GLITCH_DISABLE REG(PIO_BASE+0x024)\r |
| 164 | #define PIO_GLITCH_STATUS REG(PIO_BASE+0x028)\r |
| 165 | #define PIO_OUTPUT_DATA_SET REG(PIO_BASE+0x030)\r |
| 166 | #define PIO_OUTPUT_DATA_CLEAR REG(PIO_BASE+0x034)\r |
| 167 | #define PIO_OUTPUT_DATA_STATUS REG(PIO_BASE+0x038)\r |
| 168 | #define PIO_PIN_DATA_STATUS REG(PIO_BASE+0x03c)\r |
| 169 | #define PIO_OPEN_DRAIN_ENABLE REG(PIO_BASE+0x050)\r |
| 170 | #define PIO_OPEN_DRAIN_DISABLE REG(PIO_BASE+0x054)\r |
| 171 | #define PIO_OPEN_DRAIN_STATUS REG(PIO_BASE+0x058)\r |
| 172 | #define PIO_NO_PULL_UP_ENABLE REG(PIO_BASE+0x060)\r |
| 173 | #define PIO_NO_PULL_UP_DISABLE REG(PIO_BASE+0x064)\r |
| 174 | #define PIO_NO_PULL_UP_STATUS REG(PIO_BASE+0x068)\r |
| 175 | #define PIO_PERIPHERAL_A_SEL REG(PIO_BASE+0x070)\r |
| 176 | #define PIO_PERIPHERAL_B_SEL REG(PIO_BASE+0x074)\r |
| 177 | #define PIO_PERIPHERAL_WHICH REG(PIO_BASE+0x078)\r |
| 178 | #define PIO_OUT_WRITE_ENABLE REG(PIO_BASE+0x0a0)\r |
| 179 | #define PIO_OUT_WRITE_DISABLE REG(PIO_BASE+0x0a4)\r |
| 180 | #define PIO_OUT_WRITE_STATUS REG(PIO_BASE+0x0a8)\r |
| 181 | \r |
| 182 | //-------------\r |
| 183 | // USB Device Port\r |
| 184 | \r |
| 185 | #define UDP_BASE (0xfffb0000)\r |
| 186 | \r |
| 187 | #define UDP_FRAME_NUMBER REG(UDP_BASE+0x0000)\r |
| 188 | #define UDP_GLOBAL_STATE REG(UDP_BASE+0x0004)\r |
| 189 | #define UDP_FUNCTION_ADDR REG(UDP_BASE+0x0008)\r |
| 190 | #define UDP_INTERRUPT_ENABLE REG(UDP_BASE+0x0010)\r |
| 191 | #define UDP_INTERRUPT_DISABLE REG(UDP_BASE+0x0014)\r |
| 192 | #define UDP_INTERRUPT_MASK REG(UDP_BASE+0x0018)\r |
| 193 | #define UDP_INTERRUPT_STATUS REG(UDP_BASE+0x001c)\r |
| 194 | #define UDP_INTERRUPT_CLEAR REG(UDP_BASE+0x0020)\r |
| 195 | #define UDP_RESET_ENDPOINT REG(UDP_BASE+0x0028)\r |
| 196 | #define UDP_ENDPOINT_CSR(x) REG(UDP_BASE+0x0030+((x)*4))\r |
| 197 | #define UDP_ENDPOINT_FIFO(x) REG(UDP_BASE+0x0050+((x)*4))\r |
| 198 | #define UDP_TRANSCEIVER_CTRL REG(UDP_BASE+0x0074)\r |
| 199 | \r |
| 200 | #define UDP_GLOBAL_STATE_ADDRESSED (1<<0)\r |
| 201 | #define UDP_GLOBAL_STATE_CONFIGURED (1<<1)\r |
| 202 | #define UDP_GLOBAL_STATE_SEND_RESUME_ENABLED (1<<2)\r |
| 203 | #define UDP_GLOBAL_STATE_RESUME_RECEIVED (1<<3)\r |
| 204 | #define UDP_GLOBAL_STATE_REMOTE_WAKE_UP_ENABLED (1<<4)\r |
| 205 | \r |
| 206 | #define UDP_FUNCTION_ADDR_ENABLED (1<<8)\r |
| 207 | \r |
| 208 | #define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))\r |
| 209 | #define UDP_INTERRUPT_SUSPEND (1<<8)\r |
| 210 | #define UDP_INTERRUPT_RESUME (1<<9)\r |
| 211 | #define UDP_INTERRUPT_EXTERNAL_RESUME (1<<10)\r |
| 212 | #define UDP_INTERRUPT_SOF (1<<11)\r |
| 213 | #define UDP_INTERRUPT_END_OF_BUS_RESET (1<<12)\r |
| 214 | #define UDP_INTERRUPT_WAKEUP (1<<13)\r |
| 215 | \r |
| 216 | #define UDP_RESET_ENDPOINT_NUMBER(x) (1<<(x))\r |
| 217 | \r |
| 218 | #define UDP_CSR_TX_PACKET_ACKED (1<<0)\r |
| 219 | #define UDP_CSR_RX_PACKET_RECEIVED_BANK_0 (1<<1)\r |
| 220 | #define UDP_CSR_RX_HAVE_READ_SETUP_DATA (1<<2)\r |
| 221 | #define UDP_CSR_STALL_SENT (1<<3)\r |
| 222 | #define UDP_CSR_TX_PACKET (1<<4)\r |
| 223 | #define UDP_CSR_FORCE_STALL (1<<5)\r |
| 224 | #define UDP_CSR_RX_PACKET_RECEIVED_BANK_1 (1<<6)\r |
| 225 | #define UDP_CSR_CONTROL_DATA_DIR (1<<7)\r |
| 226 | #define UDP_CSR_EPTYPE_CONTROL (0<<8)\r |
| 227 | #define UDP_CSR_EPTYPE_ISOCHRON_OUT (1<<8)\r |
| 228 | #define UDP_CSR_EPTYPE_ISOCHRON_IN (5<<8)\r |
| 229 | #define UDP_CSR_EPTYPE_BULK_OUT (2<<8)\r |
| 230 | #define UDP_CSR_EPTYPE_BULK_IN (6<<8)\r |
| 231 | #define UDP_CSR_EPTYPE_INTERRUPT_OUT (3<<8)\r |
| 232 | #define UDP_CSR_EPTYPE_INTERRUPT_IN (7<<8)\r |
| 233 | #define UDP_CSR_IS_DATA1 (1<<11)\r |
| 234 | #define UDP_CSR_ENABLE_EP (1<<15)\r |
| 235 | #define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)\r |
| 236 | \r |
| 237 | #define UDP_TRANSCEIVER_CTRL_DISABLE (1<<8)\r |
| 238 | \r |
| 239 | //-------------\r |
| 240 | // Power Management Controller\r |
| 241 | \r |
| 242 | #define PMC_BASE (0xfffffc00)\r |
| 243 | \r |
| 244 | #define PMC_SYS_CLK_ENABLE REG(PMC_BASE+0x0000)\r |
| 245 | #define PMC_SYS_CLK_DISABLE REG(PMC_BASE+0x0004)\r |
| 246 | #define PMC_SYS_CLK_STATUS REG(PMC_BASE+0x0008)\r |
| 247 | #define PMC_PERIPHERAL_CLK_ENABLE REG(PMC_BASE+0x0010)\r |
| 248 | #define PMC_PERIPHERAL_CLK_DISABLE REG(PMC_BASE+0x0014)\r |
| 249 | #define PMC_PERIPHERAL_CLK_STATUS REG(PMC_BASE+0x0018)\r |
| 250 | #define PMC_MAIN_OSCILLATOR REG(PMC_BASE+0x0020)\r |
| 251 | #define PMC_MAIN_CLK_FREQUENCY REG(PMC_BASE+0x0024)\r |
| 252 | #define PMC_PLL REG(PMC_BASE+0x002c)\r |
| 253 | #define PMC_MASTER_CLK REG(PMC_BASE+0x0030)\r |
| 254 | #define PMC_PROGRAMMABLE_CLK_0 REG(PMC_BASE+0x0040)\r |
| 255 | #define PMC_PROGRAMMABLE_CLK_1 REG(PMC_BASE+0x0044)\r |
| 256 | #define PMC_INTERRUPT_ENABLE REG(PMC_BASE+0x0060)\r |
| 257 | #define PMC_INTERRUPT_DISABLE REG(PMC_BASE+0x0064)\r |
| 258 | #define PMC_INTERRUPT_STATUS REG(PMC_BASE+0x0068)\r |
| 259 | #define PMC_INTERRUPT_MASK REG(PMC_BASE+0x006c)\r |
| 260 | \r |
| 261 | #define PMC_SYS_CLK_PROCESSOR_CLK (1<<0)\r |
| 262 | #define PMC_SYS_CLK_UDP_CLK (1<<7)\r |
| 263 | #define PMC_SYS_CLK_PROGRAMMABLE_CLK_0 (1<<8)\r |
| 264 | #define PMC_SYS_CLK_PROGRAMMABLE_CLK_1 (1<<9)\r |
| 265 | #define PMC_SYS_CLK_PROGRAMMABLE_CLK_2 (1<<10)\r |
| 266 | \r |
| 267 | #define PMC_MAIN_OSCILLATOR_STABILIZED (1<<0)\r |
| 268 | #define PMC_MAIN_OSCILLATOR_PLL_LOCK (1<<2)\r |
| 269 | #define PMC_MAIN_OSCILLATOR_MCK_READY (1<<3)\r |
| 270 | #define PMC_MAIN_OSCILLATOR_ENABLE (1<<0)\r |
| 271 | #define PMC_MAIN_OSCILLATOR_BYPASS (1<<1)\r |
| 272 | #define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x) ((x)<<8)\r |
| 273 | \r |
| 274 | #define PMC_PLL_DIVISOR(x) (x)\r |
| 275 | #define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)\r |
| 276 | #define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)\r |
| 277 | #define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)\r |
| 278 | #define PMC_PLL_USB_DIVISOR(x) ((x)<<28)\r |
| 279 | \r |
| 280 | #define PMC_CLK_SELECTION_PLL_CLOCK (3<<0)\r |
| 281 | #define PMC_CLK_SELECTION_MAIN_CLOCK (1<<0)\r |
| 282 | #define PMC_CLK_SELECTION_SLOW_CLOCK (0<<0)\r |
| 283 | #define PMC_CLK_PRESCALE_DIV_1 (0<<2)\r |
| 284 | #define PMC_CLK_PRESCALE_DIV_2 (1<<2)\r |
| 285 | #define PMC_CLK_PRESCALE_DIV_4 (2<<2)\r |
| 286 | #define PMC_CLK_PRESCALE_DIV_8 (3<<2)\r |
| 287 | #define PMC_CLK_PRESCALE_DIV_16 (4<<2)\r |
| 288 | #define PMC_CLK_PRESCALE_DIV_32 (5<<2)\r |
| 289 | #define PMC_CLK_PRESCALE_DIV_64 (6<<2)\r |
| 290 | \r |
| 291 | //-------------\r |
| 292 | // Serial Peripheral Interface (SPI)\r |
| 293 | \r |
| 294 | #define SPI_BASE (0xfffe0000)\r |
| 295 | \r |
| 296 | #define SPI_CONTROL REG(SPI_BASE+0x00)\r |
| 297 | #define SPI_MODE REG(SPI_BASE+0x04)\r |
| 298 | #define SPI_RX_DATA REG(SPI_BASE+0x08)\r |
| 299 | #define SPI_TX_DATA REG(SPI_BASE+0x0c)\r |
| 300 | #define SPI_STATUS REG(SPI_BASE+0x10)\r |
| 301 | #define SPI_INTERRUPT_ENABLE REG(SPI_BASE+0x14)\r |
| 302 | #define SPI_INTERRUPT_DISABLE REG(SPI_BASE+0x18)\r |
| 303 | #define SPI_INTERRUPT_MASK REG(SPI_BASE+0x1c)\r |
| 304 | #define SPI_FOR_CHIPSEL_0 REG(SPI_BASE+0x30)\r |
| 305 | #define SPI_FOR_CHIPSEL_1 REG(SPI_BASE+0x34)\r |
| 306 | #define SPI_FOR_CHIPSEL_2 REG(SPI_BASE+0x38)\r |
| 307 | #define SPI_FOR_CHIPSEL_3 REG(SPI_BASE+0x3c)\r |
| 308 | \r |
| 309 | #define SPI_CONTROL_ENABLE (1<<0)\r |
| 310 | #define SPI_CONTROL_DISABLE (1<<1)\r |
| 311 | #define SPI_CONTROL_RESET (1<<7)\r |
| 312 | #define SPI_CONTROL_LAST_TRANSFER (1<<24)\r |
| 313 | \r |
| 314 | #define SPI_MODE_MASTER (1<<0)\r |
| 315 | #define SPI_MODE_VARIABLE_CHIPSEL (1<<1)\r |
| 316 | #define SPI_MODE_CHIPSELS_DECODED (1<<2)\r |
| 317 | #define SPI_MODE_USE_DIVIDED_CLOCK (1<<3)\r |
| 318 | #define SPI_MODE_MODE_FAULT_DETECTION_OFF (1<<4)\r |
| 319 | #define SPI_MODE_LOOPBACK (1<<7)\r |
| 320 | #define SPI_MODE_CHIPSEL(x) ((x)<<16)\r |
| 321 | #define SPI_MODE_DELAY_BETWEEN_CHIPSELS(x) ((x)<<24)\r |
| 322 | \r |
| 323 | #define SPI_RX_DATA_CHIPSEL(x) (((x)>>16)&0xf)\r |
| 324 | \r |
| 325 | #define SPI_TX_DATA_CHIPSEL(x) ((x)<<16)\r |
| 326 | #define SPI_TX_DATA_LAST_TRANSFER (1<<24)\r |
| 327 | \r |
| 328 | #define SPI_STATUS_RECEIVE_FULL (1<<0)\r |
| 329 | #define SPI_STATUS_TRANSMIT_EMPTY (1<<1)\r |
| 330 | #define SPI_STATUS_MODE_FAULT (1<<2)\r |
| 331 | #define SPI_STATUS_OVERRUN (1<<3)\r |
| 332 | #define SPI_STATUS_END_OF_RX_BUFFER (1<<4)\r |
| 333 | #define SPI_STATUS_END_OF_TX_BUFFER (1<<5)\r |
| 334 | #define SPI_STATUS_RX_BUFFER_FULL (1<<6)\r |
| 335 | #define SPI_STATUS_TX_BUFFER_EMPTY (1<<7)\r |
| 336 | #define SPI_STATUS_NSS_RISING_DETECTED (1<<8)\r |
| 337 | #define SPI_STATUS_TX_EMPTY (1<<9)\r |
| 338 | #define SPI_STATUS_SPI_ENABLED (1<<16)\r |
| 339 | \r |
| 340 | #define SPI_FOR_CHIPSEL_INACTIVE_CLK_1 (1<<0)\r |
| 341 | #define SPI_FOR_CHIPSEL_PHASE (1<<1)\r |
| 342 | #define SPI_FOR_CHIPSEL_LEAVE_CHIPSEL_LOW (1<<3)\r |
| 343 | #define SPI_FOR_CHIPSEL_BITS_IN_WORD(x) ((x)<<4)\r |
| 344 | #define SPI_FOR_CHIPSEL_DIVISOR(x) ((x)<<8)\r |
| 345 | #define SPI_FOR_CHIPSEL_DELAY_BEFORE_CLK(x) ((x)<<16)\r |
| 346 | #define SPI_FOR_CHIPSEL_INTERWORD_DELAY(x) ((x)<<24)\r |
| 347 | \r |
| 348 | //-------------\r |
| 349 | // Analog to Digital Converter\r |
| 350 | \r |
| 351 | #define ADC_BASE (0xfffd8000)\r |
| 352 | \r |
| 353 | #define ADC_CONTROL REG(ADC_BASE+0x00)\r |
| 354 | #define ADC_MODE REG(ADC_BASE+0x04)\r |
| 355 | #define ADC_CHANNEL_ENABLE REG(ADC_BASE+0x10)\r |
| 356 | #define ADC_CHANNEL_DISABLE REG(ADC_BASE+0x14)\r |
| 357 | #define ADC_CHANNEL_STATUS REG(ADC_BASE+0x18)\r |
| 358 | #define ADC_STATUS REG(ADC_BASE+0x1c)\r |
| 359 | #define ADC_LAST_CONVERTED_DATA REG(ADC_BASE+0x20)\r |
| 360 | #define ADC_INTERRUPT_ENABLE REG(ADC_BASE+0x24)\r |
| 361 | #define ADC_INTERRUPT_DISABLE REG(ADC_BASE+0x28)\r |
| 362 | #define ADC_INTERRUPT_MASK REG(ADC_BASE+0x2c)\r |
| 363 | #define ADC_CHANNEL_DATA(x) REG(ADC_BASE+0x30+(4*(x)))\r |
| 364 | \r |
| 365 | #define ADC_CONTROL_RESET (1<<0)\r |
| 366 | #define ADC_CONTROL_START (1<<1)\r |
| 367 | \r |
| 368 | #define ADC_MODE_HW_TRIGGERS_ENABLED (1<<0)\r |
| 369 | #define ADC_MODE_8_BIT_RESOLUTION (1<<4)\r |
| 370 | #define ADC_MODE_SLEEP (1<<5)\r |
| 371 | #define ADC_MODE_PRESCALE(x) ((x)<<8)\r |
| 372 | #define ADC_MODE_STARTUP_TIME(x) ((x)<<16)\r |
| 373 | #define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)\r |
| 374 | \r |
| 375 | #define ADC_CHANNEL(x) (1<<(x))\r |
| 376 | \r |
| 377 | #define ADC_END_OF_CONVERSION(x) (1<<(x))\r |
| 378 | #define ADC_OVERRUN_ERROR(x) (1<<(8+(x)))\r |
| 379 | #define ADC_DATA_READY (1<<16)\r |
| 380 | #define ADC_GENERAL_OVERRUN (1<<17)\r |
| 381 | #define ADC_END_OF_RX_BUFFER (1<<18)\r |
| 382 | #define ADC_RX_BUFFER_FULL (1<<19)\r |
| 383 | \r |
| 846225d5 |
384 | #define ADC_CHAN_LF 4\r |
| 385 | #define ADC_CHAN_HF 5\r |
| 6658905f |
386 | //-------------\r |
| 387 | // Synchronous Serial Controller\r |
| 388 | \r |
| 389 | #define SSC_BASE (0xfffd4000)\r |
| 390 | \r |
| 391 | #define SSC_CONTROL REG(SSC_BASE+0x00)\r |
| 392 | #define SSC_CLOCK_DIVISOR REG(SSC_BASE+0x04)\r |
| 393 | #define SSC_RECEIVE_CLOCK_MODE REG(SSC_BASE+0x10)\r |
| 394 | #define SSC_RECEIVE_FRAME_MODE REG(SSC_BASE+0x14)\r |
| 395 | #define SSC_TRANSMIT_CLOCK_MODE REG(SSC_BASE+0x18)\r |
| 396 | #define SSC_TRANSMIT_FRAME_MODE REG(SSC_BASE+0x1c)\r |
| 397 | #define SSC_RECEIVE_HOLDING REG(SSC_BASE+0x20)\r |
| 398 | #define SSC_TRANSMIT_HOLDING REG(SSC_BASE+0x24)\r |
| 399 | #define SSC_RECEIVE_SYNC_HOLDING REG(SSC_BASE+0x30)\r |
| 400 | #define SSC_TRANSMIT_SYNC_HOLDING REG(SSC_BASE+0x34)\r |
| 401 | #define SSC_STATUS REG(SSC_BASE+0x40)\r |
| 402 | #define SSC_INTERRUPT_ENABLE REG(SSC_BASE+0x44)\r |
| 403 | #define SSC_INTERRUPT_DISABLE REG(SSC_BASE+0x48)\r |
| 404 | #define SSC_INTERRUPT_MASK REG(SSC_BASE+0x4c)\r |
| 405 | \r |
| 406 | #define SSC_CONTROL_RX_ENABLE (1<<0)\r |
| 407 | #define SSC_CONTROL_RX_DISABLE (1<<1)\r |
| 408 | #define SSC_CONTROL_TX_ENABLE (1<<8)\r |
| 409 | #define SSC_CONTROL_TX_DISABLE (1<<9)\r |
| 410 | #define SSC_CONTROL_RESET (1<<15)\r |
| 411 | \r |
| 412 | #define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)\r |
| 413 | #define SSC_CLOCK_MODE_OUTPUT(x) ((x)<<2)\r |
| 414 | #define SSC_CLOCK_MODE_INVERT (1<<5)\r |
| 415 | #define SSC_CLOCK_MODE_START(x) ((x)<<8)\r |
| 416 | #define SSC_CLOCK_MODE_START_DELAY(x) ((x)<<16)\r |
| 417 | #define SSC_CLOCK_MODE_FRAME_PERIOD(x) ((x)<<24)\r |
| 418 | \r |
| 419 | #define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)\r |
| 420 | #define SSC_FRAME_MODE_LOOPBACK (1<<5) // for RX\r |
| 421 | #define SSC_FRAME_MODE_DEFAULT_IS_1 (1<<5) // for TX\r |
| 422 | #define SSC_FRAME_MODE_MSB_FIRST (1<<7)\r |
| 423 | #define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)\r |
| 424 | #define SSC_FRAME_MODE_FRAME_SYNC_LEN(x) ((x)<<16)\r |
| 425 | #define SSC_FRAME_MODE_FRAME_SYNC_TYPE(x) ((x)<<20)\r |
| 426 | #define SSC_FRAME_MODE_SYNC_DATA_ENABLE (1<<23) // for TX only\r |
| 427 | #define SSC_FRAME_MODE_NEGATIVE_EDGE (1<<24)\r |
| 428 | \r |
| 429 | #define SSC_STATUS_TX_READY (1<<0)\r |
| 430 | #define SSC_STATUS_TX_EMPTY (1<<1)\r |
| 431 | #define SSC_STATUS_TX_ENDED (1<<2)\r |
| 432 | #define SSC_STATUS_TX_BUF_EMPTY (1<<3)\r |
| 433 | #define SSC_STATUS_RX_READY (1<<4)\r |
| 434 | #define SSC_STATUS_RX_OVERRUN (1<<5)\r |
| 435 | #define SSC_STATUS_RX_ENDED (1<<6)\r |
| 436 | #define SSC_STATUS_RX_BUF_FULL (1<<7)\r |
| 437 | #define SSC_STATUS_TX_SYNC_OCCURRED (1<<10)\r |
| 438 | #define SSC_STATUS_RX_SYNC_OCCURRED (1<<11)\r |
| 439 | #define SSC_STATUS_TX_ENABLED (1<<16)\r |
| 440 | #define SSC_STATUS_RX_ENABLED (1<<17)\r |
| 441 | \r |
| 442 | //-------------\r |
| 443 | // Peripheral DMA Controller\r |
| 444 | //\r |
| 445 | // There is one set of registers for every peripheral that supports DMA.\r |
| 446 | \r |
| 447 | #define PDC_RX_POINTER(x) REG((x)+0x100)\r |
| 448 | #define PDC_RX_COUNTER(x) REG((x)+0x104)\r |
| 449 | #define PDC_TX_POINTER(x) REG((x)+0x108)\r |
| 450 | #define PDC_TX_COUNTER(x) REG((x)+0x10c)\r |
| 451 | #define PDC_RX_NEXT_POINTER(x) REG((x)+0x110)\r |
| 452 | #define PDC_RX_NEXT_COUNTER(x) REG((x)+0x114)\r |
| 453 | #define PDC_TX_NEXT_POINTER(x) REG((x)+0x118)\r |
| 454 | #define PDC_TX_NEXT_COUNTER(x) REG((x)+0x11c)\r |
| 455 | #define PDC_CONTROL(x) REG((x)+0x120)\r |
| 456 | #define PDC_STATUS(x) REG((x)+0x124)\r |
| 457 | \r |
| 458 | #define PDC_RX_ENABLE (1<<0)\r |
| 459 | #define PDC_RX_DISABLE (1<<1)\r |
| 460 | #define PDC_TX_ENABLE (1<<8)\r |
| 461 | #define PDC_TX_DISABLE (1<<9)\r |
| 462 | \r |
| aae8787c |
463 | //-------------\r |
| 464 | // Timer/Counter base\r |
| 465 | \r |
| 466 | #define TC_BASE (0xfffa0000)\r |
| 467 | \r |
| 468 | #define TC_BCR REG(TC_BASE+0xC0)\r |
| 469 | #define TC_BMR REG(TC_BASE+0xC4)\r |
| 470 | \r |
| 471 | #define TC_BCR_SYNC (1<<0)\r |
| 472 | \r |
| 473 | #define TC_CCR_CLKEN (1<<0)\r |
| 474 | #define TC_CCR_CLKDIS (1<<1)\r |
| 475 | #define TC_CCR_SWTRG (1<<2)\r |
| 476 | \r |
| 477 | #define TC_CMR_TCCLKS (7<<0)\r |
| 478 | #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)\r |
| 479 | #define TC_CMR_TCCLKS_TIMER_CLOCK2 (1<<0)\r |
| 480 | #define TC_CMR_TCCLKS_TIMER_CLOCK3 (2<<0)\r |
| 481 | #define TC_CMR_TCCLKS_TIMER_CLOCK4 (3<<0)\r |
| 482 | #define TC_CMR_TCCLKS_TIMER_CLOCK5 (4<<0)\r |
| 483 | #define TC_CMR_TCCLKS_XC0 (5<<0)\r |
| 484 | #define TC_CMR_TCCLKS_XC1 (6<<0)\r |
| 485 | #define TC_CMR_TCCLKS_XC2 (7<<0)\r |
| 486 | #define TC_CMR_CLKI (1<<3)\r |
| 487 | #define TC_CMR_BURST (3<<4)\r |
| 488 | #define TC_CMR_BURST_XC0 (1<<4)\r |
| 489 | #define TC_CMR_BURST_XC1 (2<<4)\r |
| 490 | #define TC_CMR_BURST_XC2 (3<<4)\r |
| 491 | #define TC_CMR_LDBSTOP (1<<6)\r |
| 492 | #define TC_CMR_CPCSTOP (1<<6)\r |
| 493 | #define TC_CMR_LDBDIS (1<<7)\r |
| 494 | #define TC_CMR_CPCDIS (1<<7)\r |
| 495 | #define TC_CMR_ETRGEDG (3<<8)\r |
| 496 | #define TC_CMR_ETRGEDG_NONE (0<<8)\r |
| 497 | #define TC_CMR_ETRGEDG_RISING (1<<8)\r |
| 498 | #define TC_CMR_ETRGEDG_FALLING (2<<8)\r |
| 499 | #define TC_CMR_ETRGEDG_EACH (3<<8)\r |
| 500 | #define TC_CMR_EEVTEDG (3<<8)\r |
| 501 | #define TC_CMR_EEVTEDG_NONE (0<<8)\r |
| 502 | #define TC_CMR_EEVTEDG_RISING (1<<8)\r |
| 503 | #define TC_CMR_EEVTEDG_FALLING (2<<8)\r |
| 504 | #define TC_CMR_EEVTEDG_EACH (3<<8)\r |
| 505 | #define TC_CMR_ABETRG (1<<10)\r |
| 506 | #define TC_CMR_EEVT (3<<10)\r |
| 507 | #define TC_CMR_EEVT_TIOB (0<<10)\r |
| 508 | #define TC_CMR_EEVT_XC0 (1<<10)\r |
| 509 | #define TC_CMR_EEVT_XC1 (2<<10)\r |
| 510 | #define TC_CMR_EEVT_XC2 (3<<10)\r |
| 511 | #define TC_CMR_ENETRG (1<<12)\r |
| 512 | #define TC_CMR_WAVSEL (3<<13)\r |
| 513 | #define TC_CMR_WAVSEL_UP (0<<13)\r |
| 514 | #define TC_CMR_WAVSEL_UP_AUTO (2<<13)\r |
| 515 | #define TC_CMR_WAVSEL_UPDOWN (1<<13)\r |
| 516 | #define TC_CMR_WAVSEL_UPDOWN_AUTO (3<<13)\r |
| 517 | #define TC_CMR_CPCTRG (1<<14)\r |
| 518 | #define TC_CMR_WAVE (1<<15)\r |
| 519 | #define TC_CMR_LDRA (3<<16)\r |
| 520 | #define TC_CMR_LDRA_NONE (0<<16)\r |
| 521 | #define TC_CMR_LDRA_RISING (1<<16)\r |
| 522 | #define TC_CMR_LDRA_FALLING (2<<16)\r |
| 523 | #define TC_CMR_LDRA_EACH (3<<16)\r |
| 524 | #define TC_CMR_ACPA (3<<16)\r |
| 525 | #define TC_CMR_ACPA_NONE (0<<16)\r |
| 526 | #define TC_CMR_ACPA_SET (1<<16)\r |
| 527 | #define TC_CMR_ACPA_CLEAR (2<<16)\r |
| 528 | #define TC_CMR_ACPA_TOGGLE (3<<16)\r |
| 529 | #define TC_CMR_LDRB (3<<18)\r |
| 530 | #define TC_CMR_LDRB_NONE (0<<18)\r |
| 531 | #define TC_CMR_LDRB_RISING (1<<18)\r |
| 532 | #define TC_CMR_LDRB_FALLING (2<<18)\r |
| 533 | #define TC_CMR_LDRB_EACH (3<<18)\r |
| 534 | #define TC_CMR_ACPC (3<<18)\r |
| 535 | #define TC_CMR_ACPC_NONE (0<<18)\r |
| 536 | #define TC_CMR_ACPC_SET (1<<18)\r |
| 537 | #define TC_CMR_ACPC_CLEAR (2<<18)\r |
| 538 | #define TC_CMR_ACPC_TOGGLE (3<<18)\r |
| 539 | #define TC_CMR_AEEVT (3<<20)\r |
| 540 | #define TC_CMR_AEEVT_NONE (0<<20)\r |
| 541 | #define TC_CMR_AEEVT_SET (1<<20)\r |
| 542 | #define TC_CMR_AEEVT_CLEAR (2<<20)\r |
| 543 | #define TC_CMR_AEEVT_TOGGLE (3<<20)\r |
| 544 | #define TC_CMR_ASWTRG (3<<22)\r |
| 545 | #define TC_CMR_ASWTRG_NONE (0<<22)\r |
| 546 | #define TC_CMR_ASWTRG_SET (1<<22)\r |
| 547 | #define TC_CMR_ASWTRG_CLEAR (2<<22)\r |
| 548 | #define TC_CMR_ASWTRG_TOGGLE (3<<22)\r |
| 549 | #define TC_CMR_BCPB (3<<24)\r |
| 550 | #define TC_CMR_BCPB_NONE (0<<24)\r |
| 551 | #define TC_CMR_BCPB_SET (1<<24)\r |
| 552 | #define TC_CMR_BCPB_CLEAR (2<<24)\r |
| 553 | #define TC_CMR_BCPB_TOGGLE (3<<24)\r |
| 554 | #define TC_CMR_BCPC (3<<26)\r |
| 555 | #define TC_CMR_BCPC_NONE (0<<26)\r |
| 556 | #define TC_CMR_BCPC_SET (1<<26)\r |
| 557 | #define TC_CMR_BCPC_CLEAR (2<<26)\r |
| 558 | #define TC_CMR_BCPC_TOGGLE (3<<26)\r |
| 559 | #define TC_CMR_BEEVT (3<<28)\r |
| 560 | #define TC_CMR_BEEVT_NONE (0<<28)\r |
| 561 | #define TC_CMR_BEEVT_SET (1<<28)\r |
| 562 | #define TC_CMR_BEEVT_CLEAR (2<<28)\r |
| 563 | #define TC_CMR_BEEVT_TOGGLE (3<<28)\r |
| 564 | #define TC_CMR_BSWTRG (3<<30)\r |
| 565 | #define TC_CMR_BSWTRG_NONE (0<<30)\r |
| 566 | #define TC_CMR_BSWTRG_SET (1<<30)\r |
| 567 | #define TC_CMR_BSWTRG_CLEAR (2<<30)\r |
| 568 | #define TC_CMR_BSWTRG_TOGGLE (3<<30)\r |
| 569 | \r |
| 570 | #define TC_SR_COVFS (1<<0)\r |
| 571 | #define TC_SR_LOVFS (1<<1)\r |
| 572 | #define TC_SR_CPAS (1<<2)\r |
| 573 | #define TC_SR_CPBS (1<<3)\r |
| 574 | #define TC_SR_CPCS (1<<4)\r |
| 575 | #define TC_SR_LDRAS (1<<5)\r |
| 576 | #define TC_SR_LDRBS (1<<6)\r |
| 577 | #define TC_SR_ETRGS (1<<7)\r |
| 578 | #define TC_SR_CLKSTA (1<<16)\r |
| 579 | #define TC_SR_MTIOA (1<<17)\r |
| 580 | #define TC_SR_MTIOB (1<<18)\r |
| 581 | \r |
| 582 | //-------------\r |
| 583 | // Timer/Counter 0\r |
| 584 | \r |
| 585 | #define TC0_BASE (TC_BASE+0x40*0)\r |
| 586 | \r |
| 587 | #define TC0_CCR REG(TC0_BASE+0x00)\r |
| 588 | #define TC0_CMR REG(TC0_BASE+0x04)\r |
| 589 | #define TC0_CV REG(TC0_BASE+0x10)\r |
| 590 | #define TC0_RA REG(TC0_BASE+0x14)\r |
| 591 | #define TC0_RB REG(TC0_BASE+0x18)\r |
| 592 | #define TC0_RC REG(TC0_BASE+0x1C)\r |
| 593 | #define TC0_SR REG(TC0_BASE+0x20)\r |
| 594 | #define TC0_IER REG(TC0_BASE+0x24)\r |
| 595 | #define TC0_IDR REG(TC0_BASE+0x28)\r |
| 596 | #define TC0_IMR REG(TC0_BASE+0x2C)\r |
| 597 | \r |
| 598 | //-------------\r |
| 599 | // Timer/Counter 1\r |
| 600 | \r |
| 601 | #define TC1_BASE (TC_BASE+0x40*1)\r |
| 602 | \r |
| 603 | #define TC1_CCR REG(TC1_BASE+0x00)\r |
| 604 | #define TC1_CMR REG(TC1_BASE+0x04)\r |
| 605 | #define TC1_CV REG(TC1_BASE+0x10)\r |
| 606 | #define TC1_RA REG(TC1_BASE+0x14)\r |
| 607 | #define TC1_RB REG(TC1_BASE+0x18)\r |
| 608 | #define TC1_RC REG(TC1_BASE+0x1C)\r |
| 609 | #define TC1_SR REG(TC1_BASE+0x20)\r |
| 610 | #define TC1_IER REG(TC1_BASE+0x24)\r |
| 611 | #define TC1_IDR REG(TC1_BASE+0x28)\r |
| 612 | #define TC1_IMR REG(TC1_BASE+0x2C)\r |
| 613 | \r |
| 614 | //-------------\r |
| 615 | // Timer/Counter 2\r |
| 616 | \r |
| 617 | #define TC2_BASE (TC_BASE+0x40*2)\r |
| 618 | \r |
| 619 | #define TC2_CCR REG(TC2_BASE+0x00)\r |
| 620 | #define TC2_CMR REG(TC2_BASE+0x04)\r |
| 621 | #define TC2_CV REG(TC2_BASE+0x10)\r |
| 622 | #define TC2_RA REG(TC2_BASE+0x14)\r |
| 623 | #define TC2_RB REG(TC2_BASE+0x18)\r |
| 624 | #define TC2_RC REG(TC2_BASE+0x1C)\r |
| 625 | #define TC2_SR REG(TC2_BASE+0x20)\r |
| 626 | #define TC2_IER REG(TC2_BASE+0x24)\r |
| 627 | #define TC2_IDR REG(TC2_BASE+0x28)\r |
| 628 | #define TC2_IMR REG(TC2_BASE+0x2C)\r |
| 629 | \r |
| 630 | \r |
| 6658905f |
631 | #endif\r |
projects / proxmark3-svn / blame