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e30c654b 1//-----------------------------------------------------------------------------
e30c654b 2// Jonathan Westhues, Sept 2005
bd20f8f4 3//
4// This code is licensed to you under the terms of the GNU GPL, version 2 or,
5// at your option, any later version. See the LICENSE.txt file for the text of
6// the license.
7//-----------------------------------------------------------------------------
8// Utility functions used in many places, not specific to any piece of code.
e30c654b 9//-----------------------------------------------------------------------------
bd20f8f4 10
c3c241f3 11#include "proxmark3.h"
f7e3ed82 12#include "util.h"
9ab7a6c7 13#include "string.h"
9492e0b0 14#include "apps.h"
7d5ebac9 15#include "BigBuf.h"
e30c654b 16
f38a1528 17void print_result(char *name, uint8_t *buf, size_t len) {
41863885 18 uint8_t *p = buf;
f38a1528 19
41863885 20 if ( len % 16 == 0 ) {
21 for(; p-buf < len; p += 16)
22 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
f38a1528 23 name,
24 p-buf,
25 len,
26 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
41863885 27 );
28 }
29 else {
30 for(; p-buf < len; p += 8)
31 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x",
32 name,
33 p-buf,
34 len,
35 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
36 }
f38a1528 37}
38
195af472 39size_t nbytes(size_t nbits) {
665775c8 40 return (nbits >> 3)+((nbits % 8) > 0);
195af472 41}
42
81cd0474 43uint32_t SwapBits(uint32_t value, int nrbits) {
81cd0474 44 uint32_t newvalue = 0;
5192a0a6 45 for(int i = 0; i < nrbits; i++) {
81cd0474 46 newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
47 }
48 return newvalue;
49}
50
41863885 51void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) {
e30c654b 52 while (len--) {
f7e3ed82 53 dest[len] = (uint8_t) n;
e30c654b 54 n >>= 8;
55 }
56}
57
41863885 58uint64_t bytes_to_num(uint8_t* src, size_t len) {
e30c654b 59 uint64_t num = 0;
2abdfa49 60 while (len--) {
e30c654b 61 num = (num << 8) | (*src);
62 src++;
63 }
64 return num;
65}
66
f38a1528 67// RotateLeft - Ultralight, Desfire
41863885 68void rol(uint8_t *data, const size_t len) {
f38a1528 69 uint8_t first = data[0];
70 for (size_t i = 0; i < len-1; i++) {
71 data[i] = data[i+1];
72 }
73 data[len-1] = first;
74}
dd79e03a 75
f38a1528 76void lsl (uint8_t *data, size_t len) {
77 for (size_t n = 0; n < len - 1; n++) {
78 data[n] = (data[n] << 1) | (data[n+1] >> 7);
79 }
80 data[len - 1] <<= 1;
81}
82
83int32_t le24toh (uint8_t data[3])
84{
85 return (data[2] << 16) | (data[1] << 8) | data[0];
86}
87
e30c654b 88void LEDsoff()
89{
90 LED_A_OFF();
91 LED_B_OFF();
92 LED_C_OFF();
93 LED_D_OFF();
94}
95
96// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
97void LED(int led, int ms)
98{
99 if (led & LED_RED)
100 LED_C_ON();
101 if (led & LED_ORANGE)
102 LED_A_ON();
103 if (led & LED_GREEN)
104 LED_B_ON();
105 if (led & LED_RED2)
106 LED_D_ON();
107
108 if (!ms)
109 return;
110
111 SpinDelay(ms);
112
113 if (led & LED_RED)
114 LED_C_OFF();
115 if (led & LED_ORANGE)
116 LED_A_OFF();
117 if (led & LED_GREEN)
118 LED_B_OFF();
119 if (led & LED_RED2)
120 LED_D_OFF();
121}
122
123
124// Determine if a button is double clicked, single clicked,
125// not clicked, or held down (for ms || 1sec)
126// In general, don't use this function unless you expect a
127// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
128int BUTTON_CLICKED(int ms)
129{
130 // Up to 500ms in between clicks to mean a double click
131 int ticks = (48000 * (ms ? ms : 1000)) >> 10;
132
133 // If we're not even pressed, forget about it!
134 if (!BUTTON_PRESS())
135 return BUTTON_NO_CLICK;
136
137 // Borrow a PWM unit for my real-time clock
138 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
139 // 48 MHz / 1024 gives 46.875 kHz
140 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
141 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
142 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
143
f7e3ed82 144 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 145
146 int letoff = 0;
147 for(;;)
148 {
f7e3ed82 149 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 150
151 // We haven't let off the button yet
152 if (!letoff)
153 {
154 // We just let it off!
155 if (!BUTTON_PRESS())
156 {
157 letoff = 1;
158
159 // reset our timer for 500ms
160 start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
161 ticks = (48000 * (500)) >> 10;
162 }
163
164 // Still haven't let it off
165 else
166 // Have we held down a full second?
f7e3ed82 167 if (now == (uint16_t)(start + ticks))
e30c654b 168 return BUTTON_HOLD;
169 }
170
171 // We already let off, did we click again?
172 else
173 // Sweet, double click!
174 if (BUTTON_PRESS())
175 return BUTTON_DOUBLE_CLICK;
176
177 // Have we ran out of time to double click?
178 else
f7e3ed82 179 if (now == (uint16_t)(start + ticks))
e30c654b 180 // At least we did a single click
181 return BUTTON_SINGLE_CLICK;
182
183 WDT_HIT();
184 }
185
186 // We should never get here
187 return BUTTON_ERROR;
188}
189
190// Determine if a button is held down
191int BUTTON_HELD(int ms)
192{
193 // If button is held for one second
194 int ticks = (48000 * (ms ? ms : 1000)) >> 10;
195
196 // If we're not even pressed, forget about it!
197 if (!BUTTON_PRESS())
198 return BUTTON_NO_CLICK;
199
200 // Borrow a PWM unit for my real-time clock
201 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
202 // 48 MHz / 1024 gives 46.875 kHz
203 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
204 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
205 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
206
f7e3ed82 207 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 208
209 for(;;)
210 {
f7e3ed82 211 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 212
213 // As soon as our button let go, we didn't hold long enough
214 if (!BUTTON_PRESS())
215 return BUTTON_SINGLE_CLICK;
216
217 // Have we waited the full second?
218 else
f7e3ed82 219 if (now == (uint16_t)(start + ticks))
e30c654b 220 return BUTTON_HOLD;
221
222 WDT_HIT();
223 }
224
225 // We should never get here
226 return BUTTON_ERROR;
227}
228
229// attempt at high resolution microsecond timer
230// beware: timer counts in 21.3uS increments (1024/48Mhz)
231void SpinDelayUs(int us)
232{
233 int ticks = (48*us) >> 10;
234
235 // Borrow a PWM unit for my real-time clock
236 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
237 // 48 MHz / 1024 gives 46.875 kHz
238 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
239 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
240 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
241
f7e3ed82 242 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 243
244 for(;;) {
f7e3ed82 245 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
246 if (now == (uint16_t)(start + ticks))
e30c654b 247 return;
248
249 WDT_HIT();
250 }
251}
252
253void SpinDelay(int ms)
254{
255 // convert to uS and call microsecond delay function
256 SpinDelayUs(ms*1000);
257}
258
259/* Similar to FpgaGatherVersion this formats stored version information
260 * into a string representation. It takes a pointer to the struct version_information,
261 * verifies the magic properties, then stores a formatted string, prefixed by
262 * prefix in dst.
263 */
264void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
265{
266 struct version_information *v = (struct version_information*)version_information;
267 dst[0] = 0;
a61b4976 268 strncat(dst, prefix, len-1);
e30c654b 269 if(v->magic != VERSION_INFORMATION_MAGIC) {
9783989b 270 strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);
e30c654b 271 return;
272 }
273 if(v->versionversion != 1) {
9783989b 274 strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);
e30c654b 275 return;
276 }
277 if(!v->present) {
9783989b 278 strncat(dst, "Version information not available\n", len - strlen(dst) - 1);
e30c654b 279 return;
280 }
281
cba867f2 282 strncat(dst, v->gitversion, len - strlen(dst) - 1);
e30c654b 283 if(v->clean == 0) {
cba867f2 284 strncat(dst, "-unclean", len - strlen(dst) - 1);
e30c654b 285 } else if(v->clean == 2) {
cba867f2 286 strncat(dst, "-suspect", len - strlen(dst) - 1);
e30c654b 287 }
288
cba867f2
MHS
289 strncat(dst, " ", len - strlen(dst) - 1);
290 strncat(dst, v->buildtime, len - strlen(dst) - 1);
9783989b 291 strncat(dst, "\n", len - strlen(dst) - 1);
e30c654b 292}
9ca155ba
M
293
294// -------------------------------------------------------------------------
295// timer lib
296// -------------------------------------------------------------------------
297// test procedure:
298//
299// ti = GetTickCount();
300// SpinDelay(1000);
301// ti = GetTickCount() - ti;
302// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
303
304void StartTickCount()
305{
f62b5e12 306 // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
307 // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
308 uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
309 // set RealTimeCounter divider to count at 1kHz:
310 AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
311 // note: worst case precision is approx 2.5%
9ca155ba
M
312}
313
314/*
315* Get the current count.
316*/
317uint32_t RAMFUNC GetTickCount(){
8f51ddb0 318 return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
9ca155ba
M
319}
320
8f51ddb0
M
321// -------------------------------------------------------------------------
322// microseconds timer
323// -------------------------------------------------------------------------
324void StartCountUS()
325{
326 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
327// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
328 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
329
330 // fast clock
331 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
332 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
aaa1a9a2 333 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
334 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
8f51ddb0
M
335 AT91C_BASE_TC0->TC_RA = 1;
336 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
337
338 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
339 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
1c611bbd 340
8f51ddb0
M
341 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
342 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
343 AT91C_BASE_TCB->TCB_BCR = 1;
1c611bbd 344 }
8f51ddb0
M
345
346uint32_t RAMFUNC GetCountUS(){
0de8e387 347 //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
348 // By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
41863885 349 //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3);
350 return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3);
8f51ddb0
M
351}
352
41863885 353// static uint32_t GlobalUsCounter = 0;
8f51ddb0 354
41863885 355// uint32_t RAMFUNC GetDeltaCountUS(){
356 // uint32_t g_cnt = GetCountUS();
357 // uint32_t g_res = g_cnt - GlobalUsCounter;
358 // GlobalUsCounter = g_cnt;
359 // return g_res;
360// }
8f51ddb0
M
361
362
1c611bbd 363// -------------------------------------------------------------------------
7bc95e2e 364// Timer for iso14443 commands. Uses ssp_clk from FPGA
1c611bbd 365// -------------------------------------------------------------------------
7bc95e2e 366void StartCountSspClk()
1c611bbd 367{
368 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers
369 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
370 | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
371 | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
372
373 // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
374 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
375 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
376 | AT91C_TC_CPCSTOP // Stop clock on RC compare
377 | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
7bc95e2e 378 | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
1c611bbd 379 | AT91C_TC_ENETRG // Enable external trigger event
380 | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
381 | AT91C_TC_WAVE // Waveform Mode
382 | AT91C_TC_AEEVT_SET // Set TIOA1 on external event
383 | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
384 AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
385
386 // use TC0 to count TIOA1 pulses
7bc95e2e 387 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
1c611bbd 388 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
389 | AT91C_TC_WAVE // Waveform Mode
390 | AT91C_TC_WAVESEL_UP // just count
391 | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
392 | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
393 AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
394 AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
395
396 // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
397 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
398 AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
399 | AT91C_TC_WAVE // Waveform Mode
400 | AT91C_TC_WAVESEL_UP; // just count
88e20c9f 401
1c611bbd 402 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
403 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
404 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
9492e0b0 405
88e20c9f 406 // synchronize the counter with the ssp_frame signal.
407 // Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present
7bc95e2e 408 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
9492e0b0 409 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
7bc95e2e 410 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
88e20c9f 411
7bc95e2e 412 // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
413 // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
1c611bbd 414 AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
7bc95e2e 415 // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
416 // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
417 // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
418 // (just started with the transfer of the 4th Bit).
88e20c9f 419
420 // The high word of the counter (TC2) will not reset until the low word (TC0) overflows.
421 // Therefore need to wait quite some time before we can use the counter.
7bc95e2e 422 while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
1c611bbd 423}
424
7bc95e2e 425uint32_t RAMFUNC GetCountSspClk(){
5192a0a6 426 uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
427 if ((tmp_count & 0x0000ffff) == 0) //small chance that we may have missed an increment in TC2
1c611bbd 428 return (AT91C_BASE_TC2->TC_CV << 16);
5192a0a6 429 return tmp_count;
1c611bbd 430}
7bc95e2e 431
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