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bd20f8f4 | 1 | //----------------------------------------------------------------------------- |
2 | // (c) 2009 Henryk Plötz <henryk@ploetzli.ch> | |
3 | // | |
4 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, | |
5 | // at your option, any later version. See the LICENSE.txt file for the text of | |
6 | // the license. | |
7 | //----------------------------------------------------------------------------- | |
8 | // LEGIC RF simulation code | |
9 | //----------------------------------------------------------------------------- | |
a7247d85 | 10 | |
f7e3ed82 | 11 | #include "legicrf.h" |
8e220a91 | 12 | |
a7247d85 | 13 | static struct legic_frame { |
ccedd6ae | 14 | int bits; |
a2b1414f | 15 | uint32_t data; |
a7247d85 | 16 | } current_frame; |
8e220a91 | 17 | |
3612a8a8 | 18 | static enum { |
19 | STATE_DISCON, | |
20 | STATE_IV, | |
21 | STATE_CON, | |
22 | } legic_state; | |
23 | ||
24 | static crc_t legic_crc; | |
25 | static int legic_read_count; | |
26 | static uint32_t legic_prng_bc; | |
27 | static uint32_t legic_prng_iv; | |
28 | ||
29 | static int legic_phase_drift; | |
30 | static int legic_frame_drift; | |
31 | static int legic_reqresp_drift; | |
8e220a91 | 32 | |
c71c5ee1 | 33 | int timestamp; |
34 | ||
add16a62 | 35 | AT91PS_TC timer; |
3612a8a8 | 36 | AT91PS_TC prng_timer; |
add16a62 | 37 | |
c71c5ee1 | 38 | static void setup_timer(void) { |
add16a62 | 39 | /* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging |
40 | * this it won't be terribly accurate but should be good enough. | |
41 | */ | |
42 | AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); | |
43 | timer = AT91C_BASE_TC1; | |
44 | timer->TC_CCR = AT91C_TC_CLKDIS; | |
0aa4cfc2 | 45 | timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK; |
add16a62 | 46 | timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; |
47 | ||
3612a8a8 | 48 | /* |
49 | * Set up Timer 2 to use for measuring time between frames in | |
50 | * tag simulation mode. Runs 4x faster as Timer 1 | |
51 | */ | |
52 | AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2); | |
53 | prng_timer = AT91C_BASE_TC2; | |
54 | prng_timer->TC_CCR = AT91C_TC_CLKDIS; | |
55 | prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK; | |
56 | prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
57 | } | |
58 | ||
add16a62 | 59 | /* At TIMER_CLOCK3 (MCK/32) */ |
60 | #define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */ | |
61 | #define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */ | |
62 | #define RWD_TIME_PAUSE 30 /* 20us */ | |
63 | #define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */ | |
64 | #define TAG_TIME_BIT 150 /* 100us for every bit */ | |
f7b42573 | 65 | #define TAG_TIME_WAIT 490 /* 490 time from RWD frame end to tag frame start, experimentally determined */ |
add16a62 | 66 | |
3612a8a8 | 67 | #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */ |
68 | #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */ | |
69 | ||
70 | #define SESSION_IV 0x55 | |
71 | #define OFFSET_LOG 1024 | |
add16a62 | 72 | |
73 | #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz))) | |
aac23b24 | 74 | |
c71c5ee1 | 75 | // ~ 258us + 100us*delay |
76 | #define WAIT_387 WAIT(387) | |
77 | #define WAIT(delay) while(timer->TC_CV < (delay) ); | |
78 | ||
79 | ||
80 | // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces. | |
81 | // Historically it used to be FREE_BUFFER_SIZE, which was 2744. | |
82 | #define LEGIC_CARD_MEMSIZE 1024 | |
83 | static uint8_t* cardmem; | |
84 | ||
85 | /* | |
86 | The new tracelog.. | |
87 | // Traceformat: | |
88 | // 32 bits timestamp (little endian) | |
89 | // 16 bits duration (little endian) | |
90 | // 16 bits data length (little endian, Highest Bit used as readerToTag flag) | |
91 | // y Bytes data | |
92 | // x Bytes parity (one byte per 8 bytes data) | |
93 | */ | |
94 | ||
3612a8a8 | 95 | /* Generate Keystream */ |
96 | static uint32_t get_key_stream(int skip, int count) | |
97 | { | |
c71c5ee1 | 98 | uint32_t key = 0; |
99 | int i; | |
edaf10af | 100 | |
c71c5ee1 | 101 | // Use int to enlarge timer tc to 32bit |
edaf10af | 102 | legic_prng_bc += prng_timer->TC_CV; |
c71c5ee1 | 103 | |
104 | // reset the prng timer. | |
edaf10af | 105 | prng_timer->TC_CCR = AT91C_TC_SWTRG; |
c71c5ee1 | 106 | while(prng_timer->TC_CV > 1) ; |
edaf10af | 107 | |
108 | /* If skip == -1, forward prng time based */ | |
109 | if(skip == -1) { | |
c71c5ee1 | 110 | i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */ |
edaf10af | 111 | i -= legic_prng_count(); /* substract cycles of finished frames */ |
c71c5ee1 | 112 | i -= count; /* substract current frame length, rewind to beginning */ |
edaf10af | 113 | legic_prng_forward(i); |
114 | } else { | |
115 | legic_prng_forward(skip); | |
116 | } | |
117 | ||
edaf10af | 118 | i = (count == 6) ? -1 : legic_read_count; |
119 | ||
c71c5ee1 | 120 | /* Write Time Data into LOG */ |
121 | // uint8_t *BigBuf = BigBuf_get_addr(); | |
122 | // BigBuf[OFFSET_LOG+128+i] = legic_prng_count(); | |
123 | // BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff; | |
124 | // BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff; | |
125 | // BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff; | |
126 | // BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff; | |
127 | // BigBuf[OFFSET_LOG+384+i] = count; | |
edaf10af | 128 | |
129 | /* Generate KeyStream */ | |
130 | for(i=0; i<count; i++) { | |
131 | key |= legic_prng_get_bit() << i; | |
132 | legic_prng_forward(1); | |
133 | } | |
134 | return key; | |
3612a8a8 | 135 | } |
136 | ||
137 | /* Send a frame in tag mode, the FPGA must have been set up by | |
138 | * LegicRfSimulate | |
139 | */ | |
140 | static void frame_send_tag(uint16_t response, int bits, int crypt) | |
141 | { | |
142 | /* Bitbang the response */ | |
143 | AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; | |
144 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
145 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
146 | ||
147 | /* Use time to crypt frame */ | |
148 | if(crypt) { | |
149 | legic_prng_forward(2); /* TAG_TIME_WAIT -> shift by 2 */ | |
c71c5ee1 | 150 | int key = 0; |
151 | for(int i = 0; i < bits; i++) { | |
3612a8a8 | 152 | key |= legic_prng_get_bit() << i; |
153 | legic_prng_forward(1); | |
154 | } | |
3612a8a8 | 155 | response = response ^ key; |
156 | } | |
157 | ||
158 | /* Wait for the frame start */ | |
c71c5ee1 | 159 | //while(timer->TC_CV < (TAG_TIME_WAIT - 30)) ; |
160 | WAIT( TAG_TIME_WAIT - 30) | |
161 | ||
162 | uint8_t bit = 0; | |
163 | for(int i = 0; i < bits; i++) { | |
3612a8a8 | 164 | int nextbit = timer->TC_CV + TAG_TIME_BIT; |
c71c5ee1 | 165 | bit = response & 1; |
166 | response >>= 1; | |
167 | ||
168 | if (bit) | |
3612a8a8 | 169 | AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; |
edaf10af | 170 | else |
3612a8a8 | 171 | AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; |
edaf10af | 172 | |
c71c5ee1 | 173 | //while(timer->TC_CV < nextbit) ; |
174 | WAIT(nextbit) | |
3612a8a8 | 175 | } |
176 | AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; | |
177 | } | |
178 | ||
c71c5ee1 | 179 | // Starts Clock and waits until its reset |
180 | static void ResetClock(void){ | |
181 | timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
182 | while(timer->TC_CV > 1) ; | |
183 | } | |
184 | ||
dcc10e5e | 185 | /* Send a frame in reader mode, the FPGA must have been set up by |
186 | * LegicRfReader | |
187 | */ | |
f7b42573 | 188 | static void frame_send_rwd(uint32_t data, uint8_t bits){ |
e30c654b | 189 | |
f7b42573 | 190 | uint8_t bit = 0; |
191 | uint32_t starttime = 0, pause_end = 0, bit_end = 0, temp = data; | |
c71c5ee1 | 192 | ResetClock(); |
c71c5ee1 | 193 | |
f7b42573 | 194 | for(int i = 0; i < bits; i++) { |
c71c5ee1 | 195 | |
196 | starttime = timer->TC_CV; | |
197 | pause_end = starttime + RWD_TIME_PAUSE; | |
f7b42573 | 198 | bit = temp & 1; |
199 | temp >>= 1; | |
8e220a91 | 200 | |
edaf10af | 201 | if(bit ^ legic_prng_get_bit()) |
dcc10e5e | 202 | bit_end = starttime + RWD_TIME_1; |
edaf10af | 203 | else |
dcc10e5e | 204 | bit_end = starttime + RWD_TIME_0; |
edaf10af | 205 | |
dcc10e5e | 206 | /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is |
207 | * RWD_TIME_x, where x is the bit to be transmitted */ | |
208 | AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; | |
c71c5ee1 | 209 | |
210 | WAIT( pause_end ) | |
211 | ||
dcc10e5e | 212 | AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; |
c71c5ee1 | 213 | |
f7b42573 | 214 | // bit duration is longest. use this time to forward the lfsr |
215 | legic_prng_forward(1); | |
e30c654b | 216 | |
c71c5ee1 | 217 | WAIT( bit_end ) |
dcc10e5e | 218 | } |
e30c654b | 219 | |
f7b42573 | 220 | // One final pause to mark the end of the frame |
c71c5ee1 | 221 | pause_end = timer->TC_CV + RWD_TIME_PAUSE; |
222 | ||
edaf10af | 223 | AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; |
c71c5ee1 | 224 | |
225 | WAIT(pause_end) | |
226 | ||
edaf10af | 227 | AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; |
228 | ||
f7b42573 | 229 | // log |
230 | uint8_t cmdbytes[2] = { (data & 0xFF), 0 }; | |
231 | if ( bits > 8 ) { | |
232 | cmdbytes[1] = (data >> 8 ) & 0xFF; | |
233 | LogTrace(cmdbytes, 2, 0, timer->TC_CV, NULL, TRUE); | |
234 | } else { | |
235 | LogTrace(cmdbytes, 1, 0, timer->TC_CV, NULL, TRUE); | |
236 | } | |
dcc10e5e | 237 | /* Reset the timer, to measure time until the start of the tag frame */ |
c71c5ee1 | 238 | ResetClock(); |
dcc10e5e | 239 | } |
240 | ||
241 | /* Receive a frame from the card in reader emulation mode, the FPGA and | |
242 | * timer must have been set up by LegicRfReader and frame_send_rwd. | |
e30c654b | 243 | * |
dcc10e5e | 244 | * The LEGIC RF protocol from card to reader does not include explicit |
245 | * frame start/stop information or length information. The reader must | |
246 | * know beforehand how many bits it wants to receive. (Notably: a card | |
247 | * sending a stream of 0-bits is indistinguishable from no card present.) | |
e30c654b | 248 | * |
dcc10e5e | 249 | * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but |
250 | * I'm not smart enough to use it. Instead I have patched hi_read_tx to output | |
251 | * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look | |
252 | * for edges. Count the edges in each bit interval. If they are approximately | |
253 | * 0 this was a 0-bit, if they are approximately equal to the number of edges | |
254 | * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the | |
255 | * timer that's still running from frame_send_rwd in order to get a synchronization | |
256 | * with the frame that we just sent. | |
e30c654b | 257 | * |
258 | * FIXME: Because we're relying on the hysteresis to just do the right thing | |
dcc10e5e | 259 | * the range is severely reduced (and you'll probably also need a good antenna). |
e30c654b | 260 | * So this should be fixed some time in the future for a proper receiver. |
dcc10e5e | 261 | */ |
8e220a91 | 262 | static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt) |
dcc10e5e | 263 | { |
f7b42573 | 264 | uint32_t starttime = timer->TC_CV; |
265 | ||
266 | uint32_t the_bit = 1; | |
267 | uint32_t data = 0;/* Use a bitmask to save on shifts */ | |
c71c5ee1 | 268 | int i, old_level = 0, edges = 0; |
dcc10e5e | 269 | int next_bit_at = TAG_TIME_WAIT; |
f7b42573 | 270 | int level = 0; |
3612a8a8 | 271 | |
c71c5ee1 | 272 | if(bits > 32) bits = 32; |
dcc10e5e | 273 | |
274 | AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; | |
275 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; | |
276 | ||
8e220a91 | 277 | /* we have some time now, precompute the cipher |
3612a8a8 | 278 | * since we cannot compute it on the fly while reading */ |
8e220a91 | 279 | legic_prng_forward(2); |
280 | ||
edaf10af | 281 | if(crypt) { |
8e220a91 | 282 | for(i=0; i<bits; i++) { |
283 | data |= legic_prng_get_bit() << i; | |
284 | legic_prng_forward(1); | |
285 | } | |
286 | } | |
287 | ||
f7b42573 | 288 | // QUESTION: how long did those extra calls to logtrace take? |
c71c5ee1 | 289 | WAIT(next_bit_at) |
8e220a91 | 290 | |
dcc10e5e | 291 | next_bit_at += TAG_TIME_BIT; |
e30c654b | 292 | |
dcc10e5e | 293 | for(i=0; i<bits; i++) { |
294 | edges = 0; | |
295 | while(timer->TC_CV < next_bit_at) { | |
f7b42573 | 296 | level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); |
dcc10e5e | 297 | if(level != old_level) |
298 | edges++; | |
299 | old_level = level; | |
300 | } | |
301 | next_bit_at += TAG_TIME_BIT; | |
3612a8a8 | 302 | |
c71c5ee1 | 303 | // We expect 42 edges |
304 | if(edges > 20 && edges < 60) { | |
8e220a91 | 305 | data ^= the_bit; |
dcc10e5e | 306 | } |
dcc10e5e | 307 | the_bit <<= 1; |
308 | } | |
e30c654b | 309 | |
dcc10e5e | 310 | f->data = data; |
311 | f->bits = bits; | |
f7b42573 | 312 | |
313 | // log | |
314 | uint8_t cmdbytes[] = { (data & 0xFF), (data >> 8) & 0xFF }; | |
315 | LogTrace(cmdbytes, 2, starttime, timer->TC_CV, NULL, FALSE); | |
316 | ||
c71c5ee1 | 317 | // Reset the timer, to synchronize the next frame |
318 | ResetClock(); | |
dcc10e5e | 319 | } |
320 | ||
c71c5ee1 | 321 | static void frame_append_bit(struct legic_frame * const f, int bit) { |
322 | // Overflow, won't happen | |
323 | if (f->bits >= 31) return; | |
edaf10af | 324 | |
65c2d21d | 325 | f->data |= (bit << f->bits); |
3612a8a8 | 326 | f->bits++; |
327 | } | |
328 | ||
c71c5ee1 | 329 | static void frame_clean(struct legic_frame * const f) { |
ccedd6ae | 330 | f->data = 0; |
331 | f->bits = 0; | |
a7247d85 | 332 | } |
333 | ||
c71c5ee1 | 334 | // Setup pm3 as a Legic Reader |
f7b42573 | 335 | static uint32_t perform_setup_phase_rwd(uint8_t iv) { |
336 | ||
337 | // Switch on carrier and let the tag charge for 1ms | |
2561caa2 | 338 | AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT; |
c71c5ee1 | 339 | SpinDelay(20); // was 1ms before. |
340 | ||
f7b42573 | 341 | // no keystream yet |
c71c5ee1 | 342 | legic_prng_init(0); |
e30c654b | 343 | |
8e220a91 | 344 | frame_send_rwd(iv, 7); |
f7b42573 | 345 | |
3612a8a8 | 346 | legic_prng_init(iv); |
e30c654b | 347 | |
2561caa2 | 348 | frame_clean(¤t_frame); |
f7b42573 | 349 | |
8e220a91 | 350 | frame_receive_rwd(¤t_frame, 6, 1); |
c71c5ee1 | 351 | |
352 | // we wait anyways | |
353 | legic_prng_forward(3); | |
354 | ||
f7b42573 | 355 | WAIT(387) |
356 | ||
357 | // Send obsfuscated acknowledgment frame. | |
358 | // 0x19 = MIM22 | |
359 | // 0x39 = MIM256, MIM1024 | |
360 | if ( current_frame.data == 0x0D ){ | |
361 | frame_send_rwd(0x19, 6); | |
362 | }else{ | |
363 | frame_send_rwd(0x39, 6); | |
364 | } | |
2561caa2 | 365 | |
8e220a91 | 366 | return current_frame.data; |
2561caa2 | 367 | } |
368 | ||
8e220a91 | 369 | static void LegicCommonInit(void) { |
c71c5ee1 | 370 | |
7cc204bf | 371 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); |
dcc10e5e | 372 | SetAdcMuxFor(GPIO_MUXSEL_HIPKD); |
373 | FpgaSetupSsc(); | |
374 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); | |
e30c654b | 375 | |
dcc10e5e | 376 | /* Bitbang the transmitter */ |
377 | AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; | |
378 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
379 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
e30c654b | 380 | |
c71c5ee1 | 381 | // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier. |
382 | cardmem = BigBuf_malloc(LEGIC_CARD_MEMSIZE); | |
383 | memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE); | |
384 | ||
385 | clear_trace(); | |
386 | set_tracing(TRUE); | |
387 | ||
dcc10e5e | 388 | setup_timer(); |
e30c654b | 389 | |
8e220a91 | 390 | crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); |
391 | } | |
392 | ||
3e134b4c | 393 | /* Switch off carrier, make sure tag is reset */ |
c71c5ee1 | 394 | static void switch_off_tag_rwd(void) { |
8e220a91 | 395 | AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT; |
396 | SpinDelay(10); | |
8e220a91 | 397 | WDT_HIT(); |
398 | } | |
c71c5ee1 | 399 | |
f7b42573 | 400 | // calculate crc4 for a legic READ command |
401 | // 5,8,10 address size. | |
402 | static int LegicCRC(uint16_t byte_index, uint8_t value, uint8_t cmd_sz) { | |
8e220a91 | 403 | crc_clear(&legic_crc); |
f7b42573 | 404 | crc_update(&legic_crc, LEGIC_READ, 1); |
a2b1414f | 405 | crc_update(&legic_crc, byte_index, cmd_sz-1); |
8e220a91 | 406 | crc_update(&legic_crc, value, 8); |
407 | return crc_finish(&legic_crc); | |
408 | } | |
409 | ||
f7b42573 | 410 | #define LEGIC_READ 0x01 |
411 | #define LEGIC_WRITE 0x00 | |
8e220a91 | 412 | |
f7b42573 | 413 | int legic_read_byte(int byte_index, int cmd_sz) { |
8e220a91 | 414 | |
f7b42573 | 415 | int calcCrc = 0, crc = 0; |
416 | uint8_t byte = 0; | |
417 | uint32_t cmd = (byte_index << 1) | LEGIC_READ; | |
c71c5ee1 | 418 | |
419 | WAIT_387 | |
8e220a91 | 420 | |
f7b42573 | 421 | // send read command |
c71c5ee1 | 422 | frame_send_rwd(cmd, cmd_sz); |
423 | ||
c71c5ee1 | 424 | frame_clean(¤t_frame); |
f7b42573 | 425 | |
426 | // receive | |
8e220a91 | 427 | frame_receive_rwd(¤t_frame, 12, 1); |
428 | ||
429 | byte = current_frame.data & 0xff; | |
c71c5ee1 | 430 | calcCrc = LegicCRC(byte_index, byte, cmd_sz); |
431 | crc = (current_frame.data >> 8); | |
65c2d21d | 432 | |
c71c5ee1 | 433 | if( calcCrc != crc ) { |
434 | Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc); | |
a2b1414f | 435 | return -1; |
436 | } | |
8e220a91 | 437 | |
c71c5ee1 | 438 | // we wait anyways |
439 | legic_prng_forward(4); | |
8e220a91 | 440 | return byte; |
441 | } | |
442 | ||
c71c5ee1 | 443 | /* |
444 | * - assemble a write_cmd_frame with crc and send it | |
445 | * - wait until the tag sends back an ACK ('1' bit unencrypted) | |
446 | * - forward the prng based on the timing | |
8e220a91 | 447 | */ |
3e134b4c | 448 | //int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) { |
3612a8a8 | 449 | int legic_write_byte(int byte, int addr, int addr_sz) { |
c71c5ee1 | 450 | |
451 | //do not write UID, CRC at offset 0-4. | |
452 | if(addr <= 0x04) return 0; | |
453 | ||
454 | // crc | |
3612a8a8 | 455 | crc_clear(&legic_crc); |
456 | crc_update(&legic_crc, 0, 1); /* CMD_WRITE */ | |
457 | crc_update(&legic_crc, addr, addr_sz); | |
458 | crc_update(&legic_crc, byte, 8); | |
3612a8a8 | 459 | uint32_t crc = crc_finish(&legic_crc); |
c71c5ee1 | 460 | |
461 | // send write command | |
3612a8a8 | 462 | uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC |
463 | |(byte <<(addr_sz+1)) //Data | |
464 | |(addr <<1) //Address | |
465 | |(0x00 <<0)); //CMD = W | |
466 | uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd | |
467 | ||
cc708897 | 468 | legic_prng_forward(2); /* we wait anyways */ |
c71c5ee1 | 469 | |
3612a8a8 | 470 | while(timer->TC_CV < 387) ; /* ~ 258us */ |
c71c5ee1 | 471 | |
3612a8a8 | 472 | frame_send_rwd(cmd, cmd_sz); |
c71c5ee1 | 473 | |
474 | // wllm-rbnt doesnt have these | |
475 | // AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; | |
476 | // AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; | |
3612a8a8 | 477 | |
c71c5ee1 | 478 | // wait for ack |
479 | int t, old_level = 0, edges = 0; | |
480 | int next_bit_at = 0; | |
3e134b4c | 481 | |
3612a8a8 | 482 | while(timer->TC_CV < 387) ; /* ~ 258us */ |
c71c5ee1 | 483 | |
484 | for( t = 0; t < 80; t++) { | |
3612a8a8 | 485 | edges = 0; |
486 | next_bit_at += TAG_TIME_BIT; | |
487 | while(timer->TC_CV < next_bit_at) { | |
488 | int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); | |
489 | if(level != old_level) { | |
490 | edges++; | |
491 | } | |
492 | old_level = level; | |
493 | } | |
494 | if(edges > 20 && edges < 60) { /* expected are 42 edges */ | |
495 | int t = timer->TC_CV; | |
c71c5ee1 | 496 | int c = t / TAG_TIME_BIT; |
497 | ||
498 | ResetClock(); | |
cc708897 | 499 | legic_prng_forward(c); |
3612a8a8 | 500 | return 0; |
501 | } | |
502 | } | |
c71c5ee1 | 503 | |
504 | ResetClock(); | |
3612a8a8 | 505 | return -1; |
506 | } | |
8e220a91 | 507 | |
cc708897 | 508 | int LegicRfReader(int offset, int bytes, int iv) { |
3e134b4c | 509 | |
510 | // ice_legic_setup(); | |
511 | // ice_legic_select_card(); | |
512 | // return 0; | |
f7b42573 | 513 | int byte_index = 0, cmd_sz = 0, card_sz = 0; |
cc708897 | 514 | |
8e220a91 | 515 | LegicCommonInit(); |
516 | ||
c71c5ee1 | 517 | if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card"); |
e30c654b | 518 | |
cc708897 | 519 | uint32_t tag_type = perform_setup_phase_rwd(iv); |
c71c5ee1 | 520 | |
521 | //we lose to mutch time with dprintf | |
522 | switch_off_tag_rwd(); | |
523 | ||
a2b1414f | 524 | switch(tag_type) { |
3e134b4c | 525 | case 0x0d: |
c71c5ee1 | 526 | if ( MF_DBGLEVEL >= 2) DbpString("MIM22 card found, reading card ..."); |
3e134b4c | 527 | cmd_sz = 6; |
528 | card_sz = 22; | |
529 | break; | |
a2b1414f | 530 | case 0x1d: |
c71c5ee1 | 531 | if ( MF_DBGLEVEL >= 2) DbpString("MIM256 card found, reading card ..."); |
3612a8a8 | 532 | cmd_sz = 9; |
a2b1414f | 533 | card_sz = 256; |
534 | break; | |
535 | case 0x3d: | |
c71c5ee1 | 536 | if ( MF_DBGLEVEL >= 2) DbpString("MIM1024 card found, reading card ..."); |
3612a8a8 | 537 | cmd_sz = 11; |
a2b1414f | 538 | card_sz = 1024; |
539 | break; | |
540 | default: | |
c71c5ee1 | 541 | if ( MF_DBGLEVEL >= 1) Dbprintf("Unknown card format: %x",tag_type); |
3612a8a8 | 542 | return -1; |
a2b1414f | 543 | } |
edaf10af | 544 | if(bytes == -1) |
a2b1414f | 545 | bytes = card_sz; |
edaf10af | 546 | |
547 | if(bytes+offset >= card_sz) | |
c71c5ee1 | 548 | bytes = card_sz - offset; |
a2b1414f | 549 | |
cc708897 | 550 | perform_setup_phase_rwd(iv); |
551 | ||
552 | legic_prng_forward(2); | |
8e220a91 | 553 | |
3612a8a8 | 554 | LED_B_ON(); |
8e220a91 | 555 | while(byte_index < bytes) { |
3612a8a8 | 556 | int r = legic_read_byte(byte_index+offset, cmd_sz); |
c71c5ee1 | 557 | if(r == -1 || BUTTON_PRESS()) { |
558 | switch_off_tag_rwd(); | |
559 | LEDsoff(); | |
560 | if ( MF_DBGLEVEL >= 2) DbpString("operation aborted"); | |
561 | return -1; | |
a2b1414f | 562 | } |
c71c5ee1 | 563 | cardmem[byte_index] = r; |
3612a8a8 | 564 | WDT_HIT(); |
c71c5ee1 | 565 | byte_index++; |
2561caa2 | 566 | } |
c71c5ee1 | 567 | |
3612a8a8 | 568 | switch_off_tag_rwd(); |
c71c5ee1 | 569 | LEDsoff(); |
570 | ||
571 | if ( MF_DBGLEVEL >= 1) Dbprintf("Card read, use 'hf legic decode' or"); | |
572 | if ( MF_DBGLEVEL >= 1) Dbprintf("'data hexsamples %d' to view results", (bytes+7) & ~7); | |
3612a8a8 | 573 | return 0; |
574 | } | |
575 | ||
cc708897 | 576 | /*int _LegicRfWriter(int offset, int bytes, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) { |
3e134b4c | 577 | int byte_index=0; |
578 | ||
579 | LED_B_ON(); | |
580 | perform_setup_phase_rwd(SESSION_IV); | |
581 | //legic_prng_forward(2); | |
582 | while(byte_index < bytes) { | |
583 | int r; | |
584 | ||
585 | //check if the DCF should be changed | |
586 | if ( (offset == 0x05) && (bytes == 0x02) ) { | |
587 | //write DCF in reverse order (addr 0x06 before 0x05) | |
588 | r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue); | |
589 | //legic_prng_forward(1); | |
590 | if(r == 0) { | |
591 | byte_index++; | |
592 | r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue); | |
593 | } | |
594 | //legic_prng_forward(1); | |
595 | } | |
596 | else { | |
597 | r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue); | |
598 | } | |
599 | if((r != 0) || BUTTON_PRESS()) { | |
600 | Dbprintf("operation aborted @ 0x%03.3x", byte_index); | |
601 | switch_off_tag_rwd(); | |
602 | LED_B_OFF(); | |
603 | LED_C_OFF(); | |
604 | return -1; | |
605 | } | |
606 | ||
607 | WDT_HIT(); | |
608 | byte_index++; | |
609 | if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF(); | |
610 | } | |
611 | LED_B_OFF(); | |
612 | LED_C_OFF(); | |
613 | DbpString("write successful"); | |
614 | return 0; | |
615 | }*/ | |
616 | ||
cc708897 | 617 | void LegicRfWriter(int offset, int bytes, int iv) { |
618 | ||
c71c5ee1 | 619 | int byte_index = 0, addr_sz = 0; |
620 | ||
cc708897 | 621 | iv = (iv <=0 ) ? SESSION_IV : iv; |
117d9ec2 | 622 | |
3612a8a8 | 623 | LegicCommonInit(); |
624 | ||
c71c5ee1 | 625 | if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card"); |
626 | ||
cc708897 | 627 | uint32_t tag_type = perform_setup_phase_rwd(iv); |
c71c5ee1 | 628 | |
8e220a91 | 629 | switch_off_tag_rwd(); |
c71c5ee1 | 630 | |
3612a8a8 | 631 | switch(tag_type) { |
3e134b4c | 632 | case 0x0d: |
633 | if(offset+bytes > 22) { | |
634 | Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset+bytes); | |
635 | return; | |
636 | } | |
637 | addr_sz = 5; | |
c71c5ee1 | 638 | if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset+bytes); |
3e134b4c | 639 | break; |
3612a8a8 | 640 | case 0x1d: |
641 | if(offset+bytes > 0x100) { | |
3e134b4c | 642 | Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset+bytes); |
3612a8a8 | 643 | return; |
644 | } | |
645 | addr_sz = 8; | |
c71c5ee1 | 646 | if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset+bytes); |
3612a8a8 | 647 | break; |
648 | case 0x3d: | |
649 | if(offset+bytes > 0x400) { | |
3e134b4c | 650 | Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset+bytes); |
3612a8a8 | 651 | return; |
652 | } | |
653 | addr_sz = 10; | |
c71c5ee1 | 654 | if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset+bytes); |
3612a8a8 | 655 | break; |
656 | default: | |
657 | Dbprintf("No or unknown card found, aborting"); | |
658 | return; | |
659 | } | |
660 | ||
661 | LED_B_ON(); | |
cc708897 | 662 | perform_setup_phase_rwd(iv); |
3612a8a8 | 663 | while(byte_index < bytes) { |
3e134b4c | 664 | int r; |
665 | ||
666 | //check if the DCF should be changed | |
667 | if ( ((byte_index+offset) == 0x05) && (bytes >= 0x02) ) { | |
668 | //write DCF in reverse order (addr 0x06 before 0x05) | |
c71c5ee1 | 669 | r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), addr_sz); |
3e134b4c | 670 | |
671 | // write second byte on success... | |
672 | if(r == 0) { | |
673 | byte_index++; | |
c71c5ee1 | 674 | r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), addr_sz); |
3e134b4c | 675 | } |
676 | } | |
677 | else { | |
c71c5ee1 | 678 | r = legic_write_byte(cardmem[byte_index+offset], byte_index+offset, addr_sz); |
3e134b4c | 679 | } |
c71c5ee1 | 680 | |
3612a8a8 | 681 | if((r != 0) || BUTTON_PRESS()) { |
682 | Dbprintf("operation aborted @ 0x%03.3x", byte_index); | |
683 | switch_off_tag_rwd(); | |
c71c5ee1 | 684 | LEDsoff(); |
3612a8a8 | 685 | return; |
686 | } | |
3e134b4c | 687 | |
688 | WDT_HIT(); | |
689 | byte_index++; | |
3e134b4c | 690 | } |
c71c5ee1 | 691 | LEDsoff(); |
692 | if ( MF_DBGLEVEL >= 1) DbpString("write successful"); | |
3e134b4c | 693 | } |
694 | ||
cc708897 | 695 | void LegicRfRawWriter(int address, int byte, int iv) { |
c71c5ee1 | 696 | |
697 | int byte_index = 0, addr_sz = 0; | |
cc708897 | 698 | |
699 | iv = (iv <= 0) ? SESSION_IV : iv; | |
3e134b4c | 700 | |
701 | LegicCommonInit(); | |
702 | ||
c71c5ee1 | 703 | if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card"); |
704 | ||
cc708897 | 705 | uint32_t tag_type = perform_setup_phase_rwd(iv); |
c71c5ee1 | 706 | |
3e134b4c | 707 | switch_off_tag_rwd(); |
c71c5ee1 | 708 | |
3e134b4c | 709 | switch(tag_type) { |
710 | case 0x0d: | |
cc708897 | 711 | if(address > 22) { |
712 | Dbprintf("Error: can not write to 0x%03.3x on MIM22", address); | |
3e134b4c | 713 | return; |
714 | } | |
715 | addr_sz = 5; | |
c71c5ee1 | 716 | if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte); |
3e134b4c | 717 | break; |
718 | case 0x1d: | |
cc708897 | 719 | if(address > 0x100) { |
720 | Dbprintf("Error: can not write to 0x%03.3x on MIM256", address); | |
3e134b4c | 721 | return; |
722 | } | |
723 | addr_sz = 8; | |
c71c5ee1 | 724 | if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte); |
3e134b4c | 725 | break; |
726 | case 0x3d: | |
cc708897 | 727 | if(address > 0x400) { |
728 | Dbprintf("Error: can not write to 0x%03.3x on MIM1024", address); | |
3e134b4c | 729 | return; |
730 | } | |
731 | addr_sz = 10; | |
c71c5ee1 | 732 | if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", address, byte); |
3e134b4c | 733 | break; |
734 | default: | |
735 | Dbprintf("No or unknown card found, aborting"); | |
736 | return; | |
737 | } | |
c71c5ee1 | 738 | |
cc708897 | 739 | Dbprintf("integer value: %d address: %d addr_sz: %d", byte, address, addr_sz); |
3e134b4c | 740 | LED_B_ON(); |
c71c5ee1 | 741 | |
cc708897 | 742 | perform_setup_phase_rwd(iv); |
3e134b4c | 743 | //legic_prng_forward(2); |
744 | ||
cc708897 | 745 | int r = legic_write_byte(byte, address, addr_sz); |
3e134b4c | 746 | |
747 | if((r != 0) || BUTTON_PRESS()) { | |
748 | Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index, r); | |
749 | switch_off_tag_rwd(); | |
c71c5ee1 | 750 | LEDsoff(); |
3e134b4c | 751 | return; |
3612a8a8 | 752 | } |
3612a8a8 | 753 | |
c71c5ee1 | 754 | LEDsoff(); |
755 | if ( MF_DBGLEVEL >= 1) DbpString("write successful"); | |
756 | } | |
3612a8a8 | 757 | |
c71c5ee1 | 758 | /* Handle (whether to respond) a frame in tag mode |
759 | * Only called when simulating a tag. | |
760 | */ | |
3612a8a8 | 761 | static void frame_handle_tag(struct legic_frame const * const f) |
762 | { | |
117d9ec2 | 763 | uint8_t *BigBuf = BigBuf_get_addr(); |
764 | ||
3612a8a8 | 765 | /* First Part of Handshake (IV) */ |
766 | if(f->bits == 7) { | |
c71c5ee1 | 767 | |
3612a8a8 | 768 | LED_C_ON(); |
c71c5ee1 | 769 | |
770 | prng_timer->TC_CCR = AT91C_TC_SWTRG; | |
771 | while(prng_timer->TC_CV > 1) ; | |
772 | ||
3612a8a8 | 773 | legic_prng_init(f->data); |
774 | frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1b */ | |
775 | legic_state = STATE_IV; | |
776 | legic_read_count = 0; | |
777 | legic_prng_bc = 0; | |
778 | legic_prng_iv = f->data; | |
779 | ||
780 | /* TIMEOUT */ | |
c71c5ee1 | 781 | ResetClock(); |
782 | ||
783 | //while(timer->TC_CV < 280); | |
784 | WAIT(280) | |
3612a8a8 | 785 | return; |
3612a8a8 | 786 | } |
787 | ||
788 | /* 0x19==??? */ | |
789 | if(legic_state == STATE_IV) { | |
cc708897 | 790 | int local_key = get_key_stream(3, 6); |
791 | int xored = 0x39 ^ local_key; | |
792 | if((f->bits == 6) && (f->data == xored)) { | |
3612a8a8 | 793 | legic_state = STATE_CON; |
794 | ||
795 | /* TIMEOUT */ | |
c71c5ee1 | 796 | ResetClock(); |
797 | ||
798 | //while(timer->TC_CV < 200); | |
799 | WAIT(200) | |
800 | ||
3612a8a8 | 801 | return; |
802 | } else { | |
803 | legic_state = STATE_DISCON; | |
804 | LED_C_OFF(); | |
cc708897 | 805 | Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored); |
3612a8a8 | 806 | return; |
807 | } | |
808 | } | |
809 | ||
810 | /* Read */ | |
811 | if(f->bits == 11) { | |
812 | if(legic_state == STATE_CON) { | |
cc708897 | 813 | int key = get_key_stream(2, 11); //legic_phase_drift, 11); |
3612a8a8 | 814 | int addr = f->data ^ key; addr = addr >> 1; |
117d9ec2 | 815 | int data = BigBuf[addr]; |
3612a8a8 | 816 | int hash = LegicCRC(addr, data, 11) << 8; |
117d9ec2 | 817 | BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr; |
3612a8a8 | 818 | legic_read_count++; |
819 | ||
820 | //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c); | |
821 | legic_prng_forward(legic_reqresp_drift); | |
822 | ||
823 | frame_send_tag(hash | data, 12, 1); | |
824 | ||
c71c5ee1 | 825 | /* TIMEOUT */ |
826 | ResetClock(); | |
827 | ||
cc708897 | 828 | legic_prng_forward(2); |
c71c5ee1 | 829 | //while(timer->TC_CV < 180); |
830 | WAIT(180) | |
831 | ||
3612a8a8 | 832 | return; |
833 | } | |
834 | } | |
835 | ||
836 | /* Write */ | |
837 | if(f->bits == 23) { | |
838 | int key = get_key_stream(-1, 23); //legic_frame_drift, 23); | |
839 | int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff; | |
840 | int data = f->data ^ key; data = data >> 11; data = data & 0xff; | |
841 | ||
842 | /* write command */ | |
843 | legic_state = STATE_DISCON; | |
844 | LED_C_OFF(); | |
845 | Dbprintf("write - addr: %x, data: %x", addr, data); | |
846 | return; | |
847 | } | |
848 | ||
849 | if(legic_state != STATE_DISCON) { | |
850 | Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count); | |
851 | int i; | |
852 | Dbprintf("IV: %03.3x", legic_prng_iv); | |
853 | for(i = 0; i<legic_read_count; i++) { | |
117d9ec2 | 854 | Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]); |
3612a8a8 | 855 | } |
856 | ||
857 | for(i = -1; i<legic_read_count; i++) { | |
858 | uint32_t t; | |
117d9ec2 | 859 | t = BigBuf[OFFSET_LOG+256+i*4]; |
860 | t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8; | |
861 | t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16; | |
862 | t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24; | |
3612a8a8 | 863 | |
864 | Dbprintf("Cycles: %u, Frame Length: %u, Time: %u", | |
117d9ec2 | 865 | BigBuf[OFFSET_LOG+128+i], |
866 | BigBuf[OFFSET_LOG+384+i], | |
3612a8a8 | 867 | t); |
868 | } | |
869 | } | |
870 | legic_state = STATE_DISCON; | |
871 | legic_read_count = 0; | |
872 | SpinDelay(10); | |
873 | LED_C_OFF(); | |
874 | return; | |
875 | } | |
876 | ||
877 | /* Read bit by bit untill full frame is received | |
878 | * Call to process frame end answer | |
879 | */ | |
c71c5ee1 | 880 | static void emit(int bit) { |
881 | ||
882 | switch (bit) { | |
883 | case 1: | |
884 | frame_append_bit(¤t_frame, 1); | |
885 | break; | |
886 | case 0: | |
887 | frame_append_bit(¤t_frame, 0); | |
888 | break; | |
889 | default: | |
890 | if(current_frame.bits <= 4) { | |
891 | frame_clean(¤t_frame); | |
892 | } else { | |
893 | frame_handle_tag(¤t_frame); | |
894 | frame_clean(¤t_frame); | |
895 | } | |
896 | WDT_HIT(); | |
897 | break; | |
898 | } | |
3612a8a8 | 899 | } |
900 | ||
901 | void LegicRfSimulate(int phase, int frame, int reqresp) | |
902 | { | |
903 | /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode, | |
904 | * modulation mode set to 212kHz subcarrier. We are getting the incoming raw | |
905 | * envelope waveform on DIN and should send our response on DOUT. | |
906 | * | |
907 | * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll | |
908 | * measure the time between two rising edges on DIN, and no encoding on the | |
909 | * subcarrier from card to reader, so we'll just shift out our verbatim data | |
910 | * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear, | |
911 | * seems to be 300us-ish. | |
912 | */ | |
913 | ||
c71c5ee1 | 914 | legic_phase_drift = phase; |
915 | legic_frame_drift = frame; | |
916 | legic_reqresp_drift = reqresp; | |
917 | ||
918 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); | |
919 | SetAdcMuxFor(GPIO_MUXSEL_HIPKD); | |
920 | FpgaSetupSsc(); | |
921 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K); | |
922 | ||
923 | /* Bitbang the receiver */ | |
924 | AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; | |
925 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; | |
926 | ||
927 | setup_timer(); | |
928 | crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); | |
929 | ||
930 | int old_level = 0; | |
931 | int active = 0; | |
932 | legic_state = STATE_DISCON; | |
933 | ||
934 | LED_B_ON(); | |
935 | DbpString("Starting Legic emulator, press button to end"); | |
3612a8a8 | 936 | |
c71c5ee1 | 937 | while(!BUTTON_PRESS() && !usb_poll_validate_length()) { |
938 | int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); | |
939 | int time = timer->TC_CV; | |
940 | ||
941 | if(level != old_level) { | |
942 | if(level == 1) { | |
943 | timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
944 | ||
945 | if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) { | |
946 | /* 1 bit */ | |
947 | emit(1); | |
948 | active = 1; | |
949 | LED_A_ON(); | |
950 | } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) { | |
951 | /* 0 bit */ | |
952 | emit(0); | |
953 | active = 1; | |
954 | LED_A_ON(); | |
955 | } else if (active) { | |
956 | /* invalid */ | |
957 | emit(-1); | |
958 | active = 0; | |
959 | LED_A_OFF(); | |
960 | } | |
961 | } | |
962 | } | |
3612a8a8 | 963 | |
c71c5ee1 | 964 | /* Frame end */ |
965 | if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) { | |
966 | emit(-1); | |
967 | active = 0; | |
968 | LED_A_OFF(); | |
969 | } | |
a2b1414f | 970 | |
c71c5ee1 | 971 | if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) { |
972 | timer->TC_CCR = AT91C_TC_CLKDIS; | |
973 | } | |
974 | ||
975 | old_level = level; | |
976 | WDT_HIT(); | |
977 | } | |
978 | if ( MF_DBGLEVEL >= 1) DbpString("Stopped"); | |
979 | LEDsoff(); | |
980 | } | |
3e134b4c | 981 | |
982 | //----------------------------------------------------------------------------- | |
983 | //----------------------------------------------------------------------------- | |
984 | ||
985 | ||
986 | //----------------------------------------------------------------------------- | |
987 | // Code up a string of octets at layer 2 (including CRC, we don't generate | |
988 | // that here) so that they can be transmitted to the reader. Doesn't transmit | |
989 | // them yet, just leaves them ready to send in ToSend[]. | |
990 | //----------------------------------------------------------------------------- | |
991 | // static void CodeLegicAsTag(const uint8_t *cmd, int len) | |
992 | // { | |
993 | // int i; | |
994 | ||
995 | // ToSendReset(); | |
996 | ||
997 | // // Transmit a burst of ones, as the initial thing that lets the | |
998 | // // reader get phase sync. This (TR1) must be > 80/fs, per spec, | |
999 | // // but tag that I've tried (a Paypass) exceeds that by a fair bit, | |
1000 | // // so I will too. | |
1001 | // for(i = 0; i < 20; i++) { | |
1002 | // ToSendStuffBit(1); | |
1003 | // ToSendStuffBit(1); | |
1004 | // ToSendStuffBit(1); | |
1005 | // ToSendStuffBit(1); | |
1006 | // } | |
1007 | ||
1008 | // // Send SOF. | |
1009 | // for(i = 0; i < 10; i++) { | |
1010 | // ToSendStuffBit(0); | |
1011 | // ToSendStuffBit(0); | |
1012 | // ToSendStuffBit(0); | |
1013 | // ToSendStuffBit(0); | |
1014 | // } | |
1015 | // for(i = 0; i < 2; i++) { | |
1016 | // ToSendStuffBit(1); | |
1017 | // ToSendStuffBit(1); | |
1018 | // ToSendStuffBit(1); | |
1019 | // ToSendStuffBit(1); | |
1020 | // } | |
1021 | ||
1022 | // for(i = 0; i < len; i++) { | |
1023 | // int j; | |
1024 | // uint8_t b = cmd[i]; | |
1025 | ||
1026 | // // Start bit | |
1027 | // ToSendStuffBit(0); | |
1028 | // ToSendStuffBit(0); | |
1029 | // ToSendStuffBit(0); | |
1030 | // ToSendStuffBit(0); | |
1031 | ||
1032 | // // Data bits | |
1033 | // for(j = 0; j < 8; j++) { | |
1034 | // if(b & 1) { | |
1035 | // ToSendStuffBit(1); | |
1036 | // ToSendStuffBit(1); | |
1037 | // ToSendStuffBit(1); | |
1038 | // ToSendStuffBit(1); | |
1039 | // } else { | |
1040 | // ToSendStuffBit(0); | |
1041 | // ToSendStuffBit(0); | |
1042 | // ToSendStuffBit(0); | |
1043 | // ToSendStuffBit(0); | |
1044 | // } | |
1045 | // b >>= 1; | |
1046 | // } | |
1047 | ||
1048 | // // Stop bit | |
1049 | // ToSendStuffBit(1); | |
1050 | // ToSendStuffBit(1); | |
1051 | // ToSendStuffBit(1); | |
1052 | // ToSendStuffBit(1); | |
1053 | // } | |
1054 | ||
1055 | // // Send EOF. | |
1056 | // for(i = 0; i < 10; i++) { | |
1057 | // ToSendStuffBit(0); | |
1058 | // ToSendStuffBit(0); | |
1059 | // ToSendStuffBit(0); | |
1060 | // ToSendStuffBit(0); | |
1061 | // } | |
1062 | // for(i = 0; i < 2; i++) { | |
1063 | // ToSendStuffBit(1); | |
1064 | // ToSendStuffBit(1); | |
1065 | // ToSendStuffBit(1); | |
1066 | // ToSendStuffBit(1); | |
1067 | // } | |
1068 | ||
1069 | // // Convert from last byte pos to length | |
1070 | // ToSendMax++; | |
1071 | // } | |
1072 | ||
1073 | //----------------------------------------------------------------------------- | |
1074 | // The software UART that receives commands from the reader, and its state | |
1075 | // variables. | |
1076 | //----------------------------------------------------------------------------- | |
1077 | static struct { | |
1078 | enum { | |
1079 | STATE_UNSYNCD, | |
1080 | STATE_GOT_FALLING_EDGE_OF_SOF, | |
1081 | STATE_AWAITING_START_BIT, | |
1082 | STATE_RECEIVING_DATA | |
1083 | } state; | |
1084 | uint16_t shiftReg; | |
1085 | int bitCnt; | |
1086 | int byteCnt; | |
1087 | int byteCntMax; | |
1088 | int posCnt; | |
1089 | uint8_t *output; | |
1090 | } Uart; | |
1091 | ||
1092 | /* Receive & handle a bit coming from the reader. | |
1093 | * | |
1094 | * This function is called 4 times per bit (every 2 subcarrier cycles). | |
1095 | * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us | |
1096 | * | |
1097 | * LED handling: | |
1098 | * LED A -> ON once we have received the SOF and are expecting the rest. | |
1099 | * LED A -> OFF once we have received EOF or are in error state or unsynced | |
1100 | * | |
1101 | * Returns: true if we received a EOF | |
1102 | * false if we are still waiting for some more | |
1103 | */ | |
1104 | // static RAMFUNC int HandleLegicUartBit(uint8_t bit) | |
1105 | // { | |
1106 | // switch(Uart.state) { | |
1107 | // case STATE_UNSYNCD: | |
1108 | // if(!bit) { | |
1109 | // // we went low, so this could be the beginning of an SOF | |
1110 | // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF; | |
1111 | // Uart.posCnt = 0; | |
1112 | // Uart.bitCnt = 0; | |
1113 | // } | |
1114 | // break; | |
1115 | ||
1116 | // case STATE_GOT_FALLING_EDGE_OF_SOF: | |
1117 | // Uart.posCnt++; | |
1118 | // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit | |
1119 | // if(bit) { | |
1120 | // if(Uart.bitCnt > 9) { | |
1121 | // // we've seen enough consecutive | |
1122 | // // zeros that it's a valid SOF | |
1123 | // Uart.posCnt = 0; | |
1124 | // Uart.byteCnt = 0; | |
1125 | // Uart.state = STATE_AWAITING_START_BIT; | |
1126 | // LED_A_ON(); // Indicate we got a valid SOF | |
1127 | // } else { | |
1128 | // // didn't stay down long enough | |
1129 | // // before going high, error | |
1130 | // Uart.state = STATE_UNSYNCD; | |
1131 | // } | |
1132 | // } else { | |
1133 | // // do nothing, keep waiting | |
1134 | // } | |
1135 | // Uart.bitCnt++; | |
1136 | // } | |
1137 | // if(Uart.posCnt >= 4) Uart.posCnt = 0; | |
1138 | // if(Uart.bitCnt > 12) { | |
1139 | // // Give up if we see too many zeros without | |
1140 | // // a one, too. | |
1141 | // LED_A_OFF(); | |
1142 | // Uart.state = STATE_UNSYNCD; | |
1143 | // } | |
1144 | // break; | |
1145 | ||
1146 | // case STATE_AWAITING_START_BIT: | |
1147 | // Uart.posCnt++; | |
1148 | // if(bit) { | |
1149 | // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs | |
1150 | // // stayed high for too long between | |
1151 | // // characters, error | |
1152 | // Uart.state = STATE_UNSYNCD; | |
1153 | // } | |
1154 | // } else { | |
1155 | // // falling edge, this starts the data byte | |
1156 | // Uart.posCnt = 0; | |
1157 | // Uart.bitCnt = 0; | |
1158 | // Uart.shiftReg = 0; | |
1159 | // Uart.state = STATE_RECEIVING_DATA; | |
1160 | // } | |
1161 | // break; | |
1162 | ||
1163 | // case STATE_RECEIVING_DATA: | |
1164 | // Uart.posCnt++; | |
1165 | // if(Uart.posCnt == 2) { | |
1166 | // // time to sample a bit | |
1167 | // Uart.shiftReg >>= 1; | |
1168 | // if(bit) { | |
1169 | // Uart.shiftReg |= 0x200; | |
1170 | // } | |
1171 | // Uart.bitCnt++; | |
1172 | // } | |
1173 | // if(Uart.posCnt >= 4) { | |
1174 | // Uart.posCnt = 0; | |
1175 | // } | |
1176 | // if(Uart.bitCnt == 10) { | |
1177 | // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001)) | |
1178 | // { | |
1179 | // // this is a data byte, with correct | |
1180 | // // start and stop bits | |
1181 | // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff; | |
1182 | // Uart.byteCnt++; | |
1183 | ||
1184 | // if(Uart.byteCnt >= Uart.byteCntMax) { | |
1185 | // // Buffer overflowed, give up | |
1186 | // LED_A_OFF(); | |
1187 | // Uart.state = STATE_UNSYNCD; | |
1188 | // } else { | |
1189 | // // so get the next byte now | |
1190 | // Uart.posCnt = 0; | |
1191 | // Uart.state = STATE_AWAITING_START_BIT; | |
1192 | // } | |
1193 | // } else if (Uart.shiftReg == 0x000) { | |
1194 | // // this is an EOF byte | |
1195 | // LED_A_OFF(); // Finished receiving | |
1196 | // Uart.state = STATE_UNSYNCD; | |
1197 | // if (Uart.byteCnt != 0) { | |
1198 | // return TRUE; | |
1199 | // } | |
1200 | // } else { | |
1201 | // // this is an error | |
1202 | // LED_A_OFF(); | |
1203 | // Uart.state = STATE_UNSYNCD; | |
1204 | // } | |
1205 | // } | |
1206 | // break; | |
1207 | ||
1208 | // default: | |
1209 | // LED_A_OFF(); | |
1210 | // Uart.state = STATE_UNSYNCD; | |
1211 | // break; | |
1212 | // } | |
1213 | ||
1214 | // return FALSE; | |
1215 | // } | |
1216 | ||
1217 | ||
f7b42573 | 1218 | static void UartReset() { |
1219 | Uart.byteCntMax = 3; | |
3e134b4c | 1220 | Uart.state = STATE_UNSYNCD; |
1221 | Uart.byteCnt = 0; | |
1222 | Uart.bitCnt = 0; | |
1223 | Uart.posCnt = 0; | |
f7b42573 | 1224 | memset(Uart.output, 0x00, 3); |
3e134b4c | 1225 | } |
1226 | ||
f7b42573 | 1227 | // static void UartInit(uint8_t *data) { |
3e134b4c | 1228 | // Uart.output = data; |
1229 | // UartReset(); | |
1230 | // } | |
1231 | ||
1232 | //============================================================================= | |
1233 | // An LEGIC reader. We take layer two commands, code them | |
1234 | // appropriately, and then send them to the tag. We then listen for the | |
1235 | // tag's response, which we leave in the buffer to be demodulated on the | |
1236 | // PC side. | |
1237 | //============================================================================= | |
1238 | ||
1239 | static struct { | |
1240 | enum { | |
1241 | DEMOD_UNSYNCD, | |
1242 | DEMOD_PHASE_REF_TRAINING, | |
1243 | DEMOD_AWAITING_FALLING_EDGE_OF_SOF, | |
1244 | DEMOD_GOT_FALLING_EDGE_OF_SOF, | |
1245 | DEMOD_AWAITING_START_BIT, | |
1246 | DEMOD_RECEIVING_DATA | |
1247 | } state; | |
1248 | int bitCount; | |
1249 | int posCount; | |
1250 | int thisBit; | |
1251 | uint16_t shiftReg; | |
1252 | uint8_t *output; | |
1253 | int len; | |
1254 | int sumI; | |
1255 | int sumQ; | |
1256 | } Demod; | |
1257 | ||
1258 | /* | |
1259 | * Handles reception of a bit from the tag | |
1260 | * | |
1261 | * This function is called 2 times per bit (every 4 subcarrier cycles). | |
1262 | * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us | |
1263 | * | |
1264 | * LED handling: | |
1265 | * LED C -> ON once we have received the SOF and are expecting the rest. | |
1266 | * LED C -> OFF once we have received EOF or are unsynced | |
1267 | * | |
1268 | * Returns: true if we received a EOF | |
1269 | * false if we are still waiting for some more | |
1270 | * | |
1271 | */ | |
1272 | ||
1273 | #ifndef SUBCARRIER_DETECT_THRESHOLD | |
1274 | # define SUBCARRIER_DETECT_THRESHOLD 8 | |
1275 | #endif | |
1276 | ||
1277 | // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq))) | |
1278 | #ifndef CHECK_FOR_SUBCARRIER | |
1279 | # define CHECK_FOR_SUBCARRIER() { v = MAX(ai, aq) + MIN(halfci, halfcq); } | |
1280 | #endif | |
1281 | ||
1282 | // The soft decision on the bit uses an estimate of just the | |
1283 | // quadrant of the reference angle, not the exact angle. | |
1284 | // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq))) | |
1285 | #define MAKE_SOFT_DECISION() { \ | |
1286 | if(Demod.sumI > 0) \ | |
1287 | v = ci; \ | |
1288 | else \ | |
1289 | v = -ci; \ | |
1290 | \ | |
1291 | if(Demod.sumQ > 0) \ | |
1292 | v += cq; \ | |
1293 | else \ | |
1294 | v -= cq; \ | |
1295 | \ | |
1296 | } | |
1297 | ||
1298 | static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq) | |
1299 | { | |
1300 | int v = 0; | |
1301 | int ai = ABS(ci); | |
1302 | int aq = ABS(cq); | |
1303 | int halfci = (ai >> 1); | |
1304 | int halfcq = (aq >> 1); | |
1305 | ||
1306 | switch(Demod.state) { | |
1307 | case DEMOD_UNSYNCD: | |
1308 | ||
1309 | CHECK_FOR_SUBCARRIER() | |
1310 | ||
1311 | if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected | |
1312 | Demod.state = DEMOD_PHASE_REF_TRAINING; | |
1313 | Demod.sumI = ci; | |
1314 | Demod.sumQ = cq; | |
1315 | Demod.posCount = 1; | |
1316 | } | |
1317 | break; | |
1318 | ||
1319 | case DEMOD_PHASE_REF_TRAINING: | |
1320 | if(Demod.posCount < 8) { | |
1321 | ||
1322 | CHECK_FOR_SUBCARRIER() | |
1323 | ||
1324 | if (v > SUBCARRIER_DETECT_THRESHOLD) { | |
1325 | // set the reference phase (will code a logic '1') by averaging over 32 1/fs. | |
1326 | // note: synchronization time > 80 1/fs | |
1327 | Demod.sumI += ci; | |
1328 | Demod.sumQ += cq; | |
1329 | ++Demod.posCount; | |
1330 | } else { | |
1331 | // subcarrier lost | |
1332 | Demod.state = DEMOD_UNSYNCD; | |
1333 | } | |
1334 | } else { | |
1335 | Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF; | |
1336 | } | |
1337 | break; | |
1338 | ||
1339 | case DEMOD_AWAITING_FALLING_EDGE_OF_SOF: | |
1340 | ||
1341 | MAKE_SOFT_DECISION() | |
1342 | ||
1343 | //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq ); | |
1344 | // logic '0' detected | |
1345 | if (v <= 0) { | |
1346 | ||
1347 | Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF; | |
1348 | ||
1349 | // start of SOF sequence | |
1350 | Demod.posCount = 0; | |
1351 | } else { | |
1352 | // maximum length of TR1 = 200 1/fs | |
1353 | if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD; | |
1354 | } | |
1355 | ++Demod.posCount; | |
1356 | break; | |
1357 | ||
1358 | case DEMOD_GOT_FALLING_EDGE_OF_SOF: | |
1359 | ++Demod.posCount; | |
1360 | ||
1361 | MAKE_SOFT_DECISION() | |
1362 | ||
1363 | if(v > 0) { | |
1364 | // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges | |
1365 | if(Demod.posCount < 10*2) { | |
1366 | Demod.state = DEMOD_UNSYNCD; | |
1367 | } else { | |
1368 | LED_C_ON(); // Got SOF | |
1369 | Demod.state = DEMOD_AWAITING_START_BIT; | |
1370 | Demod.posCount = 0; | |
1371 | Demod.len = 0; | |
1372 | } | |
1373 | } else { | |
1374 | // low phase of SOF too long (> 12 etu) | |
1375 | if(Demod.posCount > 13*2) { | |
1376 | Demod.state = DEMOD_UNSYNCD; | |
1377 | LED_C_OFF(); | |
1378 | } | |
1379 | } | |
1380 | break; | |
1381 | ||
1382 | case DEMOD_AWAITING_START_BIT: | |
1383 | ++Demod.posCount; | |
1384 | ||
1385 | MAKE_SOFT_DECISION() | |
1386 | ||
1387 | if(v > 0) { | |
1388 | // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs | |
1389 | if(Demod.posCount > 3*2) { | |
1390 | Demod.state = DEMOD_UNSYNCD; | |
1391 | LED_C_OFF(); | |
1392 | } | |
1393 | } else { | |
1394 | // start bit detected | |
1395 | Demod.bitCount = 0; | |
1396 | Demod.posCount = 1; // this was the first half | |
1397 | Demod.thisBit = v; | |
1398 | Demod.shiftReg = 0; | |
1399 | Demod.state = DEMOD_RECEIVING_DATA; | |
1400 | } | |
1401 | break; | |
1402 | ||
1403 | case DEMOD_RECEIVING_DATA: | |
1404 | ||
1405 | MAKE_SOFT_DECISION() | |
1406 | ||
1407 | if(Demod.posCount == 0) { | |
1408 | // first half of bit | |
1409 | Demod.thisBit = v; | |
1410 | Demod.posCount = 1; | |
1411 | } else { | |
1412 | // second half of bit | |
1413 | Demod.thisBit += v; | |
1414 | Demod.shiftReg >>= 1; | |
1415 | // logic '1' | |
1416 | if(Demod.thisBit > 0) | |
1417 | Demod.shiftReg |= 0x200; | |
1418 | ||
1419 | ++Demod.bitCount; | |
1420 | ||
1421 | if(Demod.bitCount == 10) { | |
1422 | ||
1423 | uint16_t s = Demod.shiftReg; | |
1424 | ||
1425 | if((s & 0x200) && !(s & 0x001)) { | |
1426 | // stop bit == '1', start bit == '0' | |
1427 | uint8_t b = (s >> 1); | |
1428 | Demod.output[Demod.len] = b; | |
1429 | ++Demod.len; | |
1430 | Demod.state = DEMOD_AWAITING_START_BIT; | |
1431 | } else { | |
1432 | Demod.state = DEMOD_UNSYNCD; | |
1433 | LED_C_OFF(); | |
1434 | ||
1435 | if(s == 0x000) { | |
1436 | // This is EOF (start, stop and all data bits == '0' | |
1437 | return TRUE; | |
1438 | } | |
1439 | } | |
1440 | } | |
1441 | Demod.posCount = 0; | |
1442 | } | |
1443 | break; | |
1444 | ||
1445 | default: | |
1446 | Demod.state = DEMOD_UNSYNCD; | |
1447 | LED_C_OFF(); | |
1448 | break; | |
1449 | } | |
1450 | return FALSE; | |
1451 | } | |
1452 | ||
1453 | // Clear out the state of the "UART" that receives from the tag. | |
1454 | static void DemodReset() { | |
1455 | Demod.len = 0; | |
1456 | Demod.state = DEMOD_UNSYNCD; | |
1457 | Demod.posCount = 0; | |
1458 | Demod.sumI = 0; | |
1459 | Demod.sumQ = 0; | |
1460 | Demod.bitCount = 0; | |
1461 | Demod.thisBit = 0; | |
1462 | Demod.shiftReg = 0; | |
f7b42573 | 1463 | memset(Demod.output, 0x00, 3); |
3e134b4c | 1464 | } |
1465 | ||
1466 | static void DemodInit(uint8_t *data) { | |
1467 | Demod.output = data; | |
1468 | DemodReset(); | |
1469 | } | |
1470 | ||
1471 | /* | |
1472 | * Demodulate the samples we received from the tag, also log to tracebuffer | |
1473 | * quiet: set to 'TRUE' to disable debug output | |
1474 | */ | |
1475 | #define LEGIC_DMA_BUFFER_SIZE 256 | |
1476 | static void GetSamplesForLegicDemod(int n, bool quiet) | |
1477 | { | |
1478 | int max = 0; | |
1479 | bool gotFrame = FALSE; | |
1480 | int lastRxCounter = LEGIC_DMA_BUFFER_SIZE; | |
1481 | int ci, cq, samples = 0; | |
1482 | ||
1483 | BigBuf_free(); | |
1484 | ||
1485 | // And put the FPGA in the appropriate mode | |
1486 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ); | |
1487 | ||
1488 | // The response (tag -> reader) that we're receiving. | |
1489 | // Set up the demodulator for tag -> reader responses. | |
1490 | DemodInit(BigBuf_malloc(MAX_FRAME_SIZE)); | |
1491 | ||
1492 | // The DMA buffer, used to stream samples from the FPGA | |
1493 | int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE); | |
1494 | int8_t *upTo = dmaBuf; | |
1495 | ||
1496 | // Setup and start DMA. | |
1497 | if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){ | |
1498 | if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting"); | |
1499 | return; | |
1500 | } | |
1501 | ||
1502 | // Signal field is ON with the appropriate LED: | |
1503 | LED_D_ON(); | |
1504 | for(;;) { | |
1505 | int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR; | |
1506 | if(behindBy > max) max = behindBy; | |
1507 | ||
1508 | while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) { | |
1509 | ci = upTo[0]; | |
1510 | cq = upTo[1]; | |
1511 | upTo += 2; | |
1512 | if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) { | |
1513 | upTo = dmaBuf; | |
1514 | AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo; | |
1515 | AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE; | |
1516 | } | |
1517 | lastRxCounter -= 2; | |
1518 | if(lastRxCounter <= 0) | |
1519 | lastRxCounter = LEGIC_DMA_BUFFER_SIZE; | |
1520 | ||
1521 | samples += 2; | |
1522 | ||
1523 | gotFrame = HandleLegicSamplesDemod(ci , cq ); | |
1524 | if ( gotFrame ) | |
1525 | break; | |
1526 | } | |
1527 | ||
1528 | if(samples > n || gotFrame) | |
1529 | break; | |
1530 | } | |
1531 | ||
1532 | FpgaDisableSscDma(); | |
1533 | ||
1534 | if (!quiet && Demod.len == 0) { | |
1535 | Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", | |
1536 | max, | |
1537 | samples, | |
1538 | gotFrame, | |
1539 | Demod.len, | |
1540 | Demod.sumI, | |
1541 | Demod.sumQ | |
1542 | ); | |
1543 | } | |
1544 | ||
1545 | //Tracing | |
1546 | if (Demod.len > 0) { | |
1547 | uint8_t parity[MAX_PARITY_SIZE] = {0x00}; | |
1548 | LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE); | |
1549 | } | |
1550 | } | |
1551 | //----------------------------------------------------------------------------- | |
1552 | // Transmit the command (to the tag) that was placed in ToSend[]. | |
1553 | //----------------------------------------------------------------------------- | |
1554 | static void TransmitForLegic(void) | |
1555 | { | |
1556 | int c; | |
1557 | ||
1558 | FpgaSetupSsc(); | |
1559 | ||
1560 | while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) | |
1561 | AT91C_BASE_SSC->SSC_THR = 0xff; | |
1562 | ||
1563 | // Signal field is ON with the appropriate Red LED | |
1564 | LED_D_ON(); | |
1565 | ||
1566 | // Signal we are transmitting with the Green LED | |
1567 | LED_B_ON(); | |
1568 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD); | |
1569 | ||
1570 | for(c = 0; c < 10;) { | |
1571 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { | |
1572 | AT91C_BASE_SSC->SSC_THR = 0xff; | |
1573 | c++; | |
1574 | } | |
1575 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { | |
1576 | volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; | |
1577 | (void)r; | |
1578 | } | |
1579 | WDT_HIT(); | |
1580 | } | |
1581 | ||
1582 | c = 0; | |
1583 | for(;;) { | |
1584 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { | |
1585 | AT91C_BASE_SSC->SSC_THR = ToSend[c]; | |
1586 | legic_prng_forward(1); // forward the lfsr | |
1587 | c++; | |
1588 | if(c >= ToSendMax) { | |
1589 | break; | |
1590 | } | |
1591 | } | |
1592 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { | |
1593 | volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; | |
1594 | (void)r; | |
1595 | } | |
1596 | WDT_HIT(); | |
1597 | } | |
1598 | LED_B_OFF(); | |
1599 | } | |
1600 | ||
1601 | ||
1602 | //----------------------------------------------------------------------------- | |
1603 | // Code a layer 2 command (string of octets, including CRC) into ToSend[], | |
1604 | // so that it is ready to transmit to the tag using TransmitForLegic(). | |
1605 | //----------------------------------------------------------------------------- | |
bf2cd644 | 1606 | static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits) |
3e134b4c | 1607 | { |
1608 | int i, j; | |
1609 | uint8_t b; | |
1610 | ||
1611 | ToSendReset(); | |
1612 | ||
1613 | // Send SOF | |
bf2cd644 | 1614 | for(i = 0; i < 7; i++) |
3e134b4c | 1615 | ToSendStuffBit(1); |
3e134b4c | 1616 | |
bf2cd644 | 1617 | |
1618 | for(i = 0; i < cmdlen; i++) { | |
3e134b4c | 1619 | // Start bit |
1620 | ToSendStuffBit(0); | |
1621 | ||
1622 | // Data bits | |
1623 | b = cmd[i]; | |
bf2cd644 | 1624 | for(j = 0; j < bits; j++) { |
3e134b4c | 1625 | if(b & 1) { |
1626 | ToSendStuffBit(1); | |
1627 | } else { | |
1628 | ToSendStuffBit(0); | |
1629 | } | |
1630 | b >>= 1; | |
1631 | } | |
1632 | } | |
1633 | ||
1634 | // Convert from last character reference to length | |
1635 | ++ToSendMax; | |
1636 | } | |
1637 | ||
1638 | /** | |
1639 | Convenience function to encode, transmit and trace Legic comms | |
1640 | **/ | |
bf2cd644 | 1641 | static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits) |
3e134b4c | 1642 | { |
bf2cd644 | 1643 | CodeLegicBitsAsReader(cmd, cmdlen, bits); |
3e134b4c | 1644 | TransmitForLegic(); |
1645 | if (tracing) { | |
1646 | uint8_t parity[1] = {0x00}; | |
3e82f956 | 1647 | LogTrace(cmd, cmdlen, 0, 0, parity, TRUE); |
3e134b4c | 1648 | } |
1649 | } | |
1650 | ||
1651 | int ice_legic_select_card() | |
1652 | { | |
1653 | //int cmd_size=0, card_size=0; | |
bf2cd644 | 1654 | uint8_t wakeup[] = { 0x7F }; |
3e134b4c | 1655 | uint8_t getid[] = {0x19}; |
1656 | ||
1657 | legic_prng_init(SESSION_IV); | |
1658 | ||
1659 | // first, wake up the tag, 7bits | |
bf2cd644 | 1660 | CodeAndTransmitLegicAsReader(wakeup, sizeof(wakeup), 7); |
3e134b4c | 1661 | |
1662 | GetSamplesForLegicDemod(1000, TRUE); | |
1663 | ||
1664 | // frame_clean(¤t_frame); | |
1665 | //frame_receive_rwd(¤t_frame, 6, 1); | |
1666 | ||
1667 | legic_prng_forward(1); /* we wait anyways */ | |
1668 | ||
1669 | //while(timer->TC_CV < 387) ; /* ~ 258us */ | |
1670 | //frame_send_rwd(0x19, 6); | |
bf2cd644 | 1671 | CodeAndTransmitLegicAsReader(getid, sizeof(getid), 8); |
3e134b4c | 1672 | GetSamplesForLegicDemod(1000, TRUE); |
1673 | ||
1674 | //if (Demod.len < 14) return 2; | |
1675 | Dbprintf("CARD TYPE: %02x LEN: %d", Demod.output[0], Demod.len); | |
1676 | ||
1677 | switch(Demod.output[0]) { | |
1678 | case 0x1d: | |
1679 | DbpString("MIM 256 card found"); | |
1680 | // cmd_size = 9; | |
1681 | // card_size = 256; | |
1682 | break; | |
1683 | case 0x3d: | |
1684 | DbpString("MIM 1024 card found"); | |
1685 | // cmd_size = 11; | |
1686 | // card_size = 1024; | |
1687 | break; | |
1688 | default: | |
1689 | return -1; | |
1690 | } | |
1691 | ||
1692 | // if(bytes == -1) | |
1693 | // bytes = card_size; | |
1694 | ||
1695 | // if(bytes + offset >= card_size) | |
1696 | // bytes = card_size - offset; | |
1697 | ||
1698 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); | |
1699 | set_tracing(FALSE); | |
1700 | return 1; | |
1701 | } | |
1702 | ||
1703 | // Set up LEGIC communication | |
1704 | void ice_legic_setup() { | |
1705 | ||
1706 | // standard things. | |
1707 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); | |
1708 | BigBuf_free(); BigBuf_Clear_ext(false); | |
1709 | clear_trace(); | |
1710 | set_tracing(TRUE); | |
1711 | DemodReset(); | |
1712 | UartReset(); | |
1713 | ||
1714 | // Set up the synchronous serial port | |
1715 | FpgaSetupSsc(); | |
1716 | ||
1717 | // connect Demodulated Signal to ADC: | |
1718 | SetAdcMuxFor(GPIO_MUXSEL_HIPKD); | |
1719 | ||
1720 | // Signal field is on with the appropriate LED | |
1721 | LED_D_ON(); | |
1722 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD); | |
f7b42573 | 1723 | SpinDelay(20); |
3e134b4c | 1724 | // Start the timer |
1725 | //StartCountSspClk(); | |
1726 | ||
1727 | // initalize CRC | |
1728 | crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); | |
1729 | ||
1730 | // initalize prng | |
1731 | legic_prng_init(0); | |
1732 | } |