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osx: disable app-nap during serial comm (#687)
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e30c654b 1//-----------------------------------------------------------------------------
e30c654b 2// Jonathan Westhues, Sept 2005
bd20f8f4 3//
4// This code is licensed to you under the terms of the GNU GPL, version 2 or,
5// at your option, any later version. See the LICENSE.txt file for the text of
6// the license.
7//-----------------------------------------------------------------------------
8// Utility functions used in many places, not specific to any piece of code.
e30c654b 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
f7e3ed82 12#include "util.h"
9ab7a6c7 13#include "string.h"
9492e0b0 14#include "apps.h"
7d5ebac9 15#include "BigBuf.h"
e30c654b 16
787b5bd8 17
18
19void print_result(char *name, uint8_t *buf, size_t len) {
20 uint8_t *p = buf;
21
22 if ( len % 16 == 0 ) {
23 for(; p-buf < len; p += 16)
24 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
25 name,
26 p-buf,
27 len,
28 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
29 );
30 }
31 else {
32 for(; p-buf < len; p += 8)
33 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
34 }
35}
36
195af472 37size_t nbytes(size_t nbits) {
665775c8 38 return (nbits >> 3)+((nbits % 8) > 0);
195af472 39}
40
81cd0474 41uint32_t SwapBits(uint32_t value, int nrbits) {
42 int i;
43 uint32_t newvalue = 0;
44 for(i = 0; i < nrbits; i++) {
45 newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
46 }
47 return newvalue;
48}
49
f7e3ed82 50void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
e30c654b 51{
52 while (len--) {
f7e3ed82 53 dest[len] = (uint8_t) n;
e30c654b 54 n >>= 8;
55 }
56}
57
f7e3ed82 58uint64_t bytes_to_num(uint8_t* src, size_t len)
e30c654b 59{
60 uint64_t num = 0;
61 while (len--)
62 {
63 num = (num << 8) | (*src);
64 src++;
65 }
66 return num;
67}
68
787b5bd8 69// RotateLeft - Ultralight, Desfire
70void rol(uint8_t *data, const size_t len){
71 uint8_t first = data[0];
72 for (size_t i = 0; i < len-1; i++) {
73 data[i] = data[i+1];
74 }
75 data[len-1] = first;
76}
77void lsl (uint8_t *data, size_t len) {
78 for (size_t n = 0; n < len - 1; n++) {
79 data[n] = (data[n] << 1) | (data[n+1] >> 7);
80 }
81 data[len - 1] <<= 1;
82}
83
e30c654b 84void LEDsoff()
85{
86 LED_A_OFF();
87 LED_B_OFF();
88 LED_C_OFF();
89 LED_D_OFF();
90}
91
92// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
93void LED(int led, int ms)
94{
95 if (led & LED_RED)
96 LED_C_ON();
97 if (led & LED_ORANGE)
98 LED_A_ON();
99 if (led & LED_GREEN)
100 LED_B_ON();
101 if (led & LED_RED2)
102 LED_D_ON();
103
104 if (!ms)
105 return;
106
107 SpinDelay(ms);
108
109 if (led & LED_RED)
110 LED_C_OFF();
111 if (led & LED_ORANGE)
112 LED_A_OFF();
113 if (led & LED_GREEN)
114 LED_B_OFF();
115 if (led & LED_RED2)
116 LED_D_OFF();
117}
118
119
120// Determine if a button is double clicked, single clicked,
121// not clicked, or held down (for ms || 1sec)
122// In general, don't use this function unless you expect a
123// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
124int BUTTON_CLICKED(int ms)
125{
126 // Up to 500ms in between clicks to mean a double click
127 int ticks = (48000 * (ms ? ms : 1000)) >> 10;
128
129 // If we're not even pressed, forget about it!
130 if (!BUTTON_PRESS())
131 return BUTTON_NO_CLICK;
132
133 // Borrow a PWM unit for my real-time clock
134 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
135 // 48 MHz / 1024 gives 46.875 kHz
136 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
137 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
138 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
139
f7e3ed82 140 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 141
142 int letoff = 0;
143 for(;;)
144 {
f7e3ed82 145 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 146
147 // We haven't let off the button yet
148 if (!letoff)
149 {
150 // We just let it off!
151 if (!BUTTON_PRESS())
152 {
153 letoff = 1;
154
155 // reset our timer for 500ms
156 start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
157 ticks = (48000 * (500)) >> 10;
158 }
159
160 // Still haven't let it off
161 else
162 // Have we held down a full second?
f7e3ed82 163 if (now == (uint16_t)(start + ticks))
e30c654b 164 return BUTTON_HOLD;
165 }
166
167 // We already let off, did we click again?
168 else
169 // Sweet, double click!
170 if (BUTTON_PRESS())
171 return BUTTON_DOUBLE_CLICK;
172
173 // Have we ran out of time to double click?
174 else
f7e3ed82 175 if (now == (uint16_t)(start + ticks))
e30c654b 176 // At least we did a single click
177 return BUTTON_SINGLE_CLICK;
178
179 WDT_HIT();
180 }
181
182 // We should never get here
183 return BUTTON_ERROR;
184}
185
186// Determine if a button is held down
187int BUTTON_HELD(int ms)
188{
189 // If button is held for one second
190 int ticks = (48000 * (ms ? ms : 1000)) >> 10;
191
192 // If we're not even pressed, forget about it!
193 if (!BUTTON_PRESS())
194 return BUTTON_NO_CLICK;
195
196 // Borrow a PWM unit for my real-time clock
197 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
198 // 48 MHz / 1024 gives 46.875 kHz
199 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
200 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
201 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
202
f7e3ed82 203 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 204
205 for(;;)
206 {
f7e3ed82 207 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 208
209 // As soon as our button let go, we didn't hold long enough
210 if (!BUTTON_PRESS())
211 return BUTTON_SINGLE_CLICK;
212
213 // Have we waited the full second?
214 else
f7e3ed82 215 if (now == (uint16_t)(start + ticks))
e30c654b 216 return BUTTON_HOLD;
217
218 WDT_HIT();
219 }
220
221 // We should never get here
222 return BUTTON_ERROR;
223}
224
225// attempt at high resolution microsecond timer
226// beware: timer counts in 21.3uS increments (1024/48Mhz)
227void SpinDelayUs(int us)
228{
229 int ticks = (48*us) >> 10;
230
231 // Borrow a PWM unit for my real-time clock
232 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
233 // 48 MHz / 1024 gives 46.875 kHz
234 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
235 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
236 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
237
f7e3ed82 238 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 239
240 for(;;) {
f7e3ed82 241 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
242 if (now == (uint16_t)(start + ticks))
e30c654b 243 return;
244
245 WDT_HIT();
246 }
247}
248
249void SpinDelay(int ms)
250{
251 // convert to uS and call microsecond delay function
252 SpinDelayUs(ms*1000);
253}
254
255/* Similar to FpgaGatherVersion this formats stored version information
256 * into a string representation. It takes a pointer to the struct version_information,
257 * verifies the magic properties, then stores a formatted string, prefixed by
258 * prefix in dst.
259 */
260void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
261{
262 struct version_information *v = (struct version_information*)version_information;
263 dst[0] = 0;
2ed270a8 264 strncat(dst, prefix, len-1);
e30c654b 265 if(v->magic != VERSION_INFORMATION_MAGIC) {
8e074056 266 strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);
e30c654b 267 return;
268 }
269 if(v->versionversion != 1) {
8e074056 270 strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);
e30c654b 271 return;
272 }
273 if(!v->present) {
8e074056 274 strncat(dst, "Version information not available\n", len - strlen(dst) - 1);
e30c654b 275 return;
276 }
277
cba867f2 278 strncat(dst, v->gitversion, len - strlen(dst) - 1);
e30c654b 279 if(v->clean == 0) {
cba867f2 280 strncat(dst, "-unclean", len - strlen(dst) - 1);
e30c654b 281 } else if(v->clean == 2) {
cba867f2 282 strncat(dst, "-suspect", len - strlen(dst) - 1);
e30c654b 283 }
284
cba867f2
MHS
285 strncat(dst, " ", len - strlen(dst) - 1);
286 strncat(dst, v->buildtime, len - strlen(dst) - 1);
8e074056 287 strncat(dst, "\n", len - strlen(dst) - 1);
e30c654b 288}
9ca155ba 289
4058a2d7 290
9ca155ba
M
291// -------------------------------------------------------------------------
292// timer lib
293// -------------------------------------------------------------------------
294// test procedure:
295//
296// ti = GetTickCount();
297// SpinDelay(1000);
298// ti = GetTickCount() - ti;
299// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
300
301void StartTickCount()
302{
bfb01844 303 // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
304 // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
305 uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
306 // set RealTimeCounter divider to count at 1kHz:
307 AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
308 // note: worst case precision is approx 2.5%
9ca155ba
M
309}
310
4058a2d7 311
9ca155ba
M
312/*
313* Get the current count.
314*/
315uint32_t RAMFUNC GetTickCount(){
8f51ddb0 316 return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
9ca155ba
M
317}
318
4058a2d7 319
8f51ddb0
M
320// -------------------------------------------------------------------------
321// microseconds timer
322// -------------------------------------------------------------------------
323void StartCountUS()
324{
325 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
326// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
327 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
328
329 // fast clock
330 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
331 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
332 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
333 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
334 AT91C_BASE_TC0->TC_RA = 1;
335 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
336
337 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
338 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
1c611bbd 339
8f51ddb0
M
340 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
341 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
342 AT91C_BASE_TCB->TCB_BCR = 1;
1c611bbd 343 }
8f51ddb0 344
4058a2d7 345
8f51ddb0 346uint32_t RAMFUNC GetCountUS(){
e04475c4 347 return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); //was /15) * 10);
8f51ddb0
M
348}
349
4058a2d7 350
8f51ddb0
M
351static uint32_t GlobalUsCounter = 0;
352
353uint32_t RAMFUNC GetDeltaCountUS(){
354 uint32_t g_cnt = GetCountUS();
355 uint32_t g_res = g_cnt - GlobalUsCounter;
356 GlobalUsCounter = g_cnt;
357 return g_res;
358}
359
360
1c611bbd 361// -------------------------------------------------------------------------
7bc95e2e 362// Timer for iso14443 commands. Uses ssp_clk from FPGA
1c611bbd 363// -------------------------------------------------------------------------
7bc95e2e 364void StartCountSspClk()
1c611bbd 365{
366 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers
367 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
368 | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
369 | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
370
371 // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
372 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
373 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
374 | AT91C_TC_CPCSTOP // Stop clock on RC compare
375 | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
7bc95e2e 376 | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
1c611bbd 377 | AT91C_TC_ENETRG // Enable external trigger event
378 | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
379 | AT91C_TC_WAVE // Waveform Mode
380 | AT91C_TC_AEEVT_SET // Set TIOA1 on external event
381 | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
382 AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
383
384 // use TC0 to count TIOA1 pulses
7bc95e2e 385 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
1c611bbd 386 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
387 | AT91C_TC_WAVE // Waveform Mode
388 | AT91C_TC_WAVESEL_UP // just count
389 | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
390 | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
391 AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
392 AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
393
394 // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
395 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
396 AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
397 | AT91C_TC_WAVE // Waveform Mode
398 | AT91C_TC_WAVESEL_UP; // just count
399
1c611bbd 400 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
401 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
402 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
9492e0b0 403
7bc95e2e 404 //
4058a2d7 405 // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14443 mode, otherwise SSC_FRAME and SSC_CLK signals would not be present
7bc95e2e 406 //
407 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
9492e0b0 408 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
7bc95e2e 409 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
410 // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
411 // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
1c611bbd 412 AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
7bc95e2e 413 // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
414 // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
415 // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
416 // (just started with the transfer of the 4th Bit).
417 // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
418 // we can use the counter.
4058a2d7 419 while (AT91C_BASE_TC0->TC_CV < 0xFFFF);
420 // Note: needs one more SSP_CLK cycle (1.18 us) until TC2 resets. Don't call GetCountSspClk() that soon.
1c611bbd 421}
4058a2d7 422
423
e04475c4 424void ResetSspClk(void) {
425 //enable clock of timer and software trigger
426 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
427 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
428 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
429 while (AT91C_BASE_TC2->TC_CV > 0);
430}
4058a2d7 431
432
7bc95e2e 433uint32_t RAMFUNC GetCountSspClk(){
1c611bbd 434 uint32_t tmp_count;
435 tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
7bc95e2e 436 if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
1c611bbd 437 return (AT91C_BASE_TC2->TC_CV << 16);
438 }
439 else {
440 return tmp_count;
441 }
442}
7bc95e2e 443
4058a2d7 444
e04475c4 445// -------------------------------------------------------------------------
8ff31e93 446// Timer for bitbanging, or LF stuff when you need a very precis timer
e04475c4 447// 1us = 1.5ticks
448// -------------------------------------------------------------------------
449void StartTicks(void){
8ff31e93 450 // initialization of the timer
e04475c4 451 AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
452 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
8ff31e93
A
453
454 // disable TC0 and TC1 for re-configuration
e04475c4 455 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
8ff31e93
A
456 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
457
458 // first configure TC1 (higher, 0xFFFF0000) 16 bit counter
459 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // just connect to TIOA0 from TC0
460 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // re-enable timer and wait for TC0
461
462 // second configure TC0 (lower, 0x0000FFFF) 16 bit counter
e04475c4 463 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
8ff31e93
A
464 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO |
465 AT91C_TC_ACPA_CLEAR | // RA comperator clears TIOA (carry bit)
466 AT91C_TC_ACPC_SET | // RC comperator sets TIOA (carry bit)
467 AT91C_TC_ASWTRG_SET; // SWTriger sets TIOA (carry bit)
468 AT91C_BASE_TC0->TC_RC = 0; // set TIOA (carry bit) on overflow, return to zero
469 AT91C_BASE_TC0->TC_RA = 1; // clear carry bit on next clock cycle
470 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // reset and re-enable timer
471
472 // synchronized startup procedure
473 while (AT91C_BASE_TC0->TC_CV > 0); // wait until TC0 returned to zero
474 while (AT91C_BASE_TC0->TC_CV < 2); // and has started (TC_CV > TC_RA, now TC1 is cleared)
475
476 // return to zero
477 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
478 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
479 while (AT91C_BASE_TC0->TC_CV > 0);
480}
e04475c4 481
8ff31e93
A
482
483uint32_t GetTicks(void) {
484 uint32_t hi, lo;
485
486 do {
487 hi = AT91C_BASE_TC1->TC_CV;
488 lo = AT91C_BASE_TC0->TC_CV;
489 } while(hi != AT91C_BASE_TC1->TC_CV);
490
491 return (hi << 16) | lo;
e04475c4 492}
493
4058a2d7 494
e04475c4 495// Wait - Spindelay in ticks.
496// if called with a high number, this will trigger the WDT...
497void WaitTicks(uint32_t ticks){
498 if ( ticks == 0 ) return;
8ff31e93
A
499 ticks += GetTicks();
500 while (GetTicks() < ticks);
e04475c4 501}
4058a2d7 502
503
e04475c4 504// Wait / Spindelay in us (microseconds)
505// 1us = 1.5ticks.
506void WaitUS(uint16_t us){
913a54a8 507 WaitTicks( (uint32_t)us * 3 / 2 ) ;
e04475c4 508}
4058a2d7 509
510
e04475c4 511void WaitMS(uint16_t ms){
913a54a8 512 WaitTicks( (uint32_t)ms * 1500 );
e04475c4 513}
4058a2d7 514
515
e04475c4 516// Starts Clock and waits until its reset
517void ResetTicks(void){
e04475c4 518 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
8ff31e93
A
519 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
520 while (AT91C_BASE_TC0->TC_CV > 0);
e04475c4 521}
4058a2d7 522
523
e04475c4 524void ResetTimer(AT91PS_TC timer){
525 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
526 while(timer->TC_CV > 0) ;
527}
4058a2d7 528
529
e04475c4 530// stop clock
531void StopTicks(void){
532 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
533 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
534}
535
4058a2d7 536
f9c1dcd9
MF
537static uint64_t next_random = 1;
538
539/* Generates a (non-cryptographically secure) 32-bit random number.
540 *
541 * We don't have an implementation of the "rand" function or a clock to seed it
542 * with, so we just call GetTickCount the first time to seed ourselves.
543 */
544uint32_t prand() {
545 if (next_random == 1) {
546 next_random = GetTickCount();
547 }
548
549 next_random = next_random * 6364136223846793005 + 1;
550 return (uint32_t)(next_random >> 32) % 0xffffffff;
551}
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