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ba06a4b6 | 1 | //----------------------------------------------------------------------------- |
2 | // The way that we connect things when transmitting a command to an ISO | |
3 | // 15693 tag, using 100% modulation only for now. | |
4 | // | |
5 | // Jonathan Westhues, April 2006 | |
6 | //----------------------------------------------------------------------------- | |
7 | ||
8 | module hi_read_tx( | |
9 | pck0, ck_1356meg, ck_1356megb, | |
10 | pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4, | |
11 | adc_d, adc_clk, | |
12 | ssp_frame, ssp_din, ssp_dout, ssp_clk, | |
13 | cross_hi, cross_lo, | |
14 | dbg, | |
15 | shallow_modulation | |
16 | ); | |
17 | input pck0, ck_1356meg, ck_1356megb; | |
18 | output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4; | |
19 | input [7:0] adc_d; | |
20 | output adc_clk; | |
21 | input ssp_dout; | |
22 | output ssp_frame, ssp_din, ssp_clk; | |
23 | input cross_hi, cross_lo; | |
24 | output dbg; | |
25 | input shallow_modulation; | |
26 | ||
27 | // The high-frequency stuff. For now, for testing, just bring out the carrier, | |
28 | // and allow the ARM to modulate it over the SSP. | |
29 | reg pwr_hi; | |
30 | reg pwr_oe1; | |
31 | reg pwr_oe2; | |
32 | reg pwr_oe3; | |
33 | reg pwr_oe4; | |
34 | always @(ck_1356megb or ssp_dout or shallow_modulation) | |
35 | begin | |
36 | if(shallow_modulation) | |
37 | begin | |
38 | pwr_hi <= ck_1356megb; | |
39 | pwr_oe1 <= ~ssp_dout; | |
40 | pwr_oe2 <= ~ssp_dout; | |
41 | pwr_oe3 <= ~ssp_dout; | |
42 | pwr_oe4 <= 1'b0; | |
43 | end | |
44 | else | |
45 | begin | |
46 | pwr_hi <= ck_1356megb & ssp_dout; | |
47 | pwr_oe1 <= 1'b0; | |
48 | pwr_oe2 <= 1'b0; | |
49 | pwr_oe3 <= 1'b0; | |
50 | pwr_oe4 <= 1'b0; | |
51 | end | |
52 | end | |
53 | ||
54 | // Then just divide the 13.56 MHz clock down to produce appropriate clocks | |
55 | // for the synchronous serial port. | |
56 | ||
57 | reg [6:0] hi_div_by_128; | |
58 | ||
59 | always @(posedge ck_1356meg) | |
60 | hi_div_by_128 <= hi_div_by_128 + 1; | |
61 | ||
62 | assign ssp_clk = hi_div_by_128[6]; | |
63 | ||
64 | reg [2:0] hi_byte_div; | |
65 | ||
66 | always @(negedge ssp_clk) | |
67 | hi_byte_div <= hi_byte_div + 1; | |
68 | ||
69 | assign ssp_frame = (hi_byte_div == 3'b000); | |
70 | ||
71 | // Implement a hysteresis to give out the received signal on | |
72 | // ssp_din. Sample at fc. | |
73 | assign adc_clk = ck_1356meg; | |
74 | ||
75 | // ADC data appears on the rising edge, so sample it on the falling edge | |
76 | reg after_hysteresis; | |
77 | always @(negedge adc_clk) | |
78 | begin | |
79 | if(& adc_d[7:0]) after_hysteresis <= 1'b1; | |
80 | else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0; | |
81 | end | |
82 | ||
83 | ||
84 | assign ssp_din = after_hysteresis; | |
85 | ||
86 | assign pwr_lo = 1'b0; | |
87 | assign dbg = ssp_din; | |
88 | ||
89 | endmodule |