]> git.zerfleddert.de Git - proxmark3-svn/blame - armsrc/lfops.c
Bugfixes for LF FDX
[proxmark3-svn] / armsrc / lfops.c
CommitLineData
e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
779d9a0e 7// Tags supported here so far are Texas Instruments (TI), HID, EM4x05, EM410x
e09f21fa 8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
3606ac0a 19#include "protocols.h"
506672c4 20#include "usb_cdc.h" // for usb_poll_validate_length
fc52fbd4 21#include "fpgaloader.h"
e09f21fa 22
23/**
24 * Function to do a modulation and then get samples.
25 * @param delay_off
26 * @param period_0
27 * @param period_1
28 * @param command
29 */
21a615cb 30void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
e09f21fa 31{
779d9a0e 32 // start timer
61e96805 33 StartTicks();
e09f21fa 34
779d9a0e 35 // use lf config settings
36 sample_config *sc = getSamplingConfig();
e09f21fa 37
2896e490 38 // Make sure the tag is reset
e09f21fa 39 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
61e96805 41 WaitMS(2500);
e09f21fa 42
2896e490 43 // clear read buffer (after fpga bitstream loaded...)
44 BigBuf_Clear_keep_EM();
45
779d9a0e 46 // power on
47 LFSetupFPGAForADC(sc->divisor, 1);
e09f21fa 48
49 // And a little more time for the tag to fully power up
61e96805 50 WaitMS(2000);
51 // if delay_off = 0 then just bitbang 1 = antenna on 0 = off for respective periods.
52 bool bitbang = delay_off == 0;
e0165dcf 53 // now modulate the reader field
61e96805 54
55 if (bitbang) {
779d9a0e 56 // HACK it appears the loop and if statements take up about 7us so adjust waits accordingly...
61e96805 57 uint8_t hack_cnt = 7;
58 if (period_0 < hack_cnt || period_1 < hack_cnt) {
779d9a0e 59 DbpString("Warning periods cannot be less than 7us in bit bang mode");
61e96805 60 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
61 LED_D_OFF();
62 return;
63 }
779d9a0e 64
65 // hack2 needed--- it appears to take about 8-16us to turn the antenna back on
66 // leading to ~ 1 to 2 125khz samples extra in every off period
67 // so we should test for last 0 before next 1 and reduce period_0 by this extra amount...
68 // but is this time different for every antenna or other hw builds??? more testing needed
69
70 // prime cmd_len to save time comparing strings while modulating
61e96805 71 int cmd_len = 0;
72 while(command[cmd_len] != '\0' && command[cmd_len] != ' ')
73 cmd_len++;
74
75 int counter = 0;
76 bool off = false;
77 for (counter = 0; counter < cmd_len; counter++) {
61e96805 78 // if cmd = 0 then turn field off
79 if (command[counter] == '0') {
80 // if field already off leave alone (affects timing otherwise)
81 if (off == false) {
82 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
83 LED_D_OFF();
84 off = true;
85 }
779d9a0e 86 // note we appear to take about 7us to switch over (or run the if statements/loop...)
61e96805 87 WaitUS(period_0-hack_cnt);
88 // else if cmd = 1 then turn field on
89 } else {
90 // if field already on leave alone (affects timing otherwise)
91 if (off) {
779d9a0e 92 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
61e96805 93 LED_D_ON();
94 off = false;
95 }
779d9a0e 96 // note we appear to take about 7us to switch over (or run the if statements/loop...)
61e96805 97 WaitUS(period_1-hack_cnt);
98 }
99 }
100 } else { // old mode of cmd read using delay as off period
101 while(*command != '\0' && *command != ' ') {
102 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
103 LED_D_OFF();
104 WaitUS(delay_off);
779d9a0e 105 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
61e96805 106 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
107 LED_D_ON();
108 if(*(command++) == '0') {
109 WaitUS(period_0);
110 } else {
111 WaitUS(period_1);
112 }
113 }
e0165dcf 114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
115 LED_D_OFF();
61e96805 116 WaitUS(delay_off);
779d9a0e 117 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
e0165dcf 118 }
e09f21fa 119
e0165dcf 120 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
e09f21fa 121
e0165dcf 122 // now do the read
b9957414 123 DoAcquisition_config(false, 0);
779d9a0e 124
125 // Turn off antenna
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
127 // tell client we are done
128 cmd_send(CMD_ACK,0,0,0,0,0);
e09f21fa 129}
130
e09f21fa 131/* blank r/w tag data stream
132...0000000000000000 01111111
1331010101010101010101010101010101010101010101010101010101010101010
1340011010010100001
13501111111
136101010101010101[0]000...
137
138[5555fe852c5555555555555555fe0000]
139*/
140void ReadTItag(void)
141{
e0165dcf 142 // some hardcoded initial params
143 // when we read a TI tag we sample the zerocross line at 2Mhz
144 // TI tags modulate a 1 as 16 cycles of 123.2Khz
145 // TI tags modulate a 0 as 16 cycles of 134.2Khz
e09f21fa 146 #define FSAMPLE 2000000
147 #define FREQLO 123200
148 #define FREQHI 134200
149
e0165dcf 150 signed char *dest = (signed char *)BigBuf_get_addr();
151 uint16_t n = BigBuf_max_traceLen();
152 // 128 bit shift register [shift3:shift2:shift1:shift0]
153 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
154
155 int i, cycles=0, samples=0;
156 // how many sample points fit in 16 cycles of each frequency
157 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
158 // when to tell if we're close enough to one freq or another
159 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
160
161 // TI tags charge at 134.2Khz
162 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
163 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
164
165 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
166 // connects to SSP_DIN and the SSP_DOUT logic level controls
167 // whether we're modulating the antenna (high)
168 // or listening to the antenna (low)
169 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
170
171 // get TI tag data into the buffer
172 AcquireTiType();
173
174 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
175
176 for (i=0; i<n-1; i++) {
177 // count cycles by looking for lo to hi zero crossings
178 if ( (dest[i]<0) && (dest[i+1]>0) ) {
179 cycles++;
180 // after 16 cycles, measure the frequency
181 if (cycles>15) {
182 cycles=0;
183 samples=i-samples; // number of samples in these 16 cycles
184
185 // TI bits are coming to us lsb first so shift them
186 // right through our 128 bit right shift register
187 shift0 = (shift0>>1) | (shift1 << 31);
188 shift1 = (shift1>>1) | (shift2 << 31);
189 shift2 = (shift2>>1) | (shift3 << 31);
190 shift3 >>= 1;
191
192 // check if the cycles fall close to the number
193 // expected for either the low or high frequency
194 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
195 // low frequency represents a 1
196 shift3 |= (1<<31);
197 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
198 // high frequency represents a 0
199 } else {
200 // probably detected a gay waveform or noise
201 // use this as gaydar or discard shift register and start again
202 shift3 = shift2 = shift1 = shift0 = 0;
203 }
204 samples = i;
205
206 // for each bit we receive, test if we've detected a valid tag
207
208 // if we see 17 zeroes followed by 6 ones, we might have a tag
209 // remember the bits are backwards
210 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
211 // if start and end bytes match, we have a tag so break out of the loop
212 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
213 cycles = 0xF0B; //use this as a flag (ugly but whatever)
214 break;
215 }
216 }
217 }
218 }
219 }
220
221 // if flag is set we have a tag
222 if (cycles!=0xF0B) {
223 DbpString("Info: No valid tag detected.");
224 } else {
225 // put 64 bit data into shift1 and shift0
226 shift0 = (shift0>>24) | (shift1 << 8);
227 shift1 = (shift1>>24) | (shift2 << 8);
228
229 // align 16 bit crc into lower half of shift2
230 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
231
232 // if r/w tag, check ident match
e09f21fa 233 if (shift3 & (1<<15) ) {
e0165dcf 234 DbpString("Info: TI tag is rewriteable");
235 // only 15 bits compare, last bit of ident is not valid
e09f21fa 236 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
e0165dcf 237 DbpString("Error: Ident mismatch!");
238 } else {
239 DbpString("Info: TI tag ident is valid");
240 }
241 } else {
242 DbpString("Info: TI tag is readonly");
243 }
244
245 // WARNING the order of the bytes in which we calc crc below needs checking
246 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
247 // bytes in reverse or something
248 // calculate CRC
249 uint32_t crc=0;
250
251 crc = update_crc16(crc, (shift0)&0xff);
252 crc = update_crc16(crc, (shift0>>8)&0xff);
253 crc = update_crc16(crc, (shift0>>16)&0xff);
254 crc = update_crc16(crc, (shift0>>24)&0xff);
255 crc = update_crc16(crc, (shift1)&0xff);
256 crc = update_crc16(crc, (shift1>>8)&0xff);
257 crc = update_crc16(crc, (shift1>>16)&0xff);
258 crc = update_crc16(crc, (shift1>>24)&0xff);
259
260 Dbprintf("Info: Tag data: %x%08x, crc=%x",
261 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
262 if (crc != (shift2&0xffff)) {
263 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
264 } else {
265 DbpString("Info: CRC is good");
266 }
267 }
e09f21fa 268}
269
270void WriteTIbyte(uint8_t b)
271{
e0165dcf 272 int i = 0;
273
274 // modulate 8 bits out to the antenna
275 for (i=0; i<8; i++)
276 {
277 if (b&(1<<i)) {
278 // stop modulating antenna
279 LOW(GPIO_SSC_DOUT);
280 SpinDelayUs(1000);
281 // modulate antenna
282 HIGH(GPIO_SSC_DOUT);
283 SpinDelayUs(1000);
284 } else {
285 // stop modulating antenna
286 LOW(GPIO_SSC_DOUT);
287 SpinDelayUs(300);
288 // modulate antenna
289 HIGH(GPIO_SSC_DOUT);
290 SpinDelayUs(1700);
291 }
292 }
e09f21fa 293}
294
295void AcquireTiType(void)
296{
e0165dcf 297 int i, j, n;
298 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
299 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
e09f21fa 300 #define TIBUFLEN 1250
301
e0165dcf 302 // clear buffer
e09f21fa 303 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
709665b5 304 BigBuf_Clear_ext(false);
e0165dcf 305
306 // Set up the synchronous serial port
307 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
308 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
309
310 // steal this pin from the SSP and use it to control the modulation
311 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
312 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
313
314 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
315 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
316
317 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
318 // 48/2 = 24 MHz clock must be divided by 12
319 AT91C_BASE_SSC->SSC_CMR = 12;
320
321 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
322 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
323 AT91C_BASE_SSC->SSC_TCMR = 0;
324 AT91C_BASE_SSC->SSC_TFMR = 0;
325
326 LED_D_ON();
327
328 // modulate antenna
329 HIGH(GPIO_SSC_DOUT);
330
331 // Charge TI tag for 50ms.
332 SpinDelay(50);
333
334 // stop modulating antenna and listen
335 LOW(GPIO_SSC_DOUT);
336
337 LED_D_OFF();
338
339 i = 0;
340 for(;;) {
341 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
342 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
343 i++; if(i >= TIBUFLEN) break;
344 }
345 WDT_HIT();
346 }
347
348 // return stolen pin to SSP
349 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
350 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
351
352 char *dest = (char *)BigBuf_get_addr();
353 n = TIBUFLEN*32;
354 // unpack buffer
355 for (i=TIBUFLEN-1; i>=0; i--) {
356 for (j=0; j<32; j++) {
357 if(BigBuf[i] & (1 << j)) {
358 dest[--n] = 1;
359 } else {
360 dest[--n] = -1;
361 }
362 }
363 }
e09f21fa 364}
365
366// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
367// if crc provided, it will be written with the data verbatim (even if bogus)
368// if not provided a valid crc will be computed from the data and written.
369void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
370{
fff58476 371 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
e0165dcf 372 if(crc == 0) {
373 crc = update_crc16(crc, (idlo)&0xff);
374 crc = update_crc16(crc, (idlo>>8)&0xff);
375 crc = update_crc16(crc, (idlo>>16)&0xff);
376 crc = update_crc16(crc, (idlo>>24)&0xff);
377 crc = update_crc16(crc, (idhi)&0xff);
378 crc = update_crc16(crc, (idhi>>8)&0xff);
379 crc = update_crc16(crc, (idhi>>16)&0xff);
380 crc = update_crc16(crc, (idhi>>24)&0xff);
381 }
382 Dbprintf("Writing to tag: %x%08x, crc=%x",
383 (unsigned int) idhi, (unsigned int) idlo, crc);
384
385 // TI tags charge at 134.2Khz
386 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
387 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
388 // connects to SSP_DIN and the SSP_DOUT logic level controls
389 // whether we're modulating the antenna (high)
390 // or listening to the antenna (low)
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
392 LED_A_ON();
393
394 // steal this pin from the SSP and use it to control the modulation
395 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
397
398 // writing algorithm:
399 // a high bit consists of a field off for 1ms and field on for 1ms
400 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
401 // initiate a charge time of 50ms (field on) then immediately start writing bits
402 // start by writing 0xBB (keyword) and 0xEB (password)
403 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
404 // finally end with 0x0300 (write frame)
405 // all data is sent lsb firts
406 // finish with 15ms programming time
407
408 // modulate antenna
409 HIGH(GPIO_SSC_DOUT);
410 SpinDelay(50); // charge time
411
412 WriteTIbyte(0xbb); // keyword
413 WriteTIbyte(0xeb); // password
414 WriteTIbyte( (idlo )&0xff );
415 WriteTIbyte( (idlo>>8 )&0xff );
416 WriteTIbyte( (idlo>>16)&0xff );
417 WriteTIbyte( (idlo>>24)&0xff );
418 WriteTIbyte( (idhi )&0xff );
419 WriteTIbyte( (idhi>>8 )&0xff );
420 WriteTIbyte( (idhi>>16)&0xff );
421 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
422 WriteTIbyte( (crc )&0xff ); // crc lo
423 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
424 WriteTIbyte(0x00); // write frame lo
425 WriteTIbyte(0x03); // write frame hi
426 HIGH(GPIO_SSC_DOUT);
427 SpinDelay(50); // programming time
428
429 LED_A_OFF();
430
431 // get TI tag data into the buffer
432 AcquireTiType();
433
434 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
72c5877a 435 DbpString("Now use `lf ti read` to check");
e09f21fa 436}
437
438void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
439{
e0165dcf 440 int i;
441 uint8_t *tab = BigBuf_get_addr();
e09f21fa 442
8c8317a5 443 //note FpgaDownloadAndGo destroys the bigbuf so be sure this is called before now...
444 //FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
e0165dcf 445 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
e09f21fa 446
e0165dcf 447 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
e09f21fa 448
e0165dcf 449 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
450 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
e09f21fa 451
709665b5 452 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
453 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
e09f21fa 454
e0165dcf 455 i = 0;
456 for(;;) {
457 //wait until SSC_CLK goes HIGH
f2081c43 458 int ii = 0;
e0165dcf 459 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
f2081c43 460 //only check every 1000th time (usb_poll_validate_length on some systems was too slow)
461 if ( ii == 1000 ) {
462 if (BUTTON_PRESS() || usb_poll_validate_length() ) {
463 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
464 DbpString("Stopped");
465 return;
466 }
467 ii=0;
e0165dcf 468 }
469 WDT_HIT();
f2081c43 470 ii++;
e0165dcf 471 }
472 if (ledcontrol)
473 LED_D_ON();
474
475 if(tab[i])
476 OPEN_COIL();
477 else
478 SHORT_COIL();
479
480 if (ledcontrol)
481 LED_D_OFF();
f2081c43 482 ii=0;
e0165dcf 483 //wait until SSC_CLK goes LOW
484 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
f2081c43 485 //only check every 1000th time (usb_poll_validate_length on some systems was too slow)
486 if ( ii == 1000 ) {
487 if (BUTTON_PRESS() || usb_poll_validate_length() ) {
488 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
489 DbpString("Stopped");
490 return;
491 }
492 ii=0;
e0165dcf 493 }
494 WDT_HIT();
f2081c43 495 ii++;
e0165dcf 496 }
497
498 i++;
499 if(i == period) {
500
501 i = 0;
502 if (gap) {
503 SHORT_COIL();
504 SpinDelayUs(gap);
505 }
506 }
89696b8b 507
e0165dcf 508 }
e09f21fa 509}
510
e09f21fa 511#define DEBUG_FRAME_CONTENTS 1
512void SimulateTagLowFrequencyBidir(int divisor, int t0)
513{
514}
515
516// compose fc/8 fc/10 waveform (FSK2)
517static void fc(int c, int *n)
518{
e0165dcf 519 uint8_t *dest = BigBuf_get_addr();
520 int idx;
521
522 // for when we want an fc8 pattern every 4 logical bits
523 if(c==0) {
524 dest[((*n)++)]=1;
525 dest[((*n)++)]=1;
526 dest[((*n)++)]=1;
527 dest[((*n)++)]=1;
528 dest[((*n)++)]=0;
529 dest[((*n)++)]=0;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 }
533
534 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
535 if(c==8) {
536 for (idx=0; idx<6; idx++) {
537 dest[((*n)++)]=1;
538 dest[((*n)++)]=1;
539 dest[((*n)++)]=1;
540 dest[((*n)++)]=1;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 }
546 }
547
548 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
549 if(c==10) {
550 for (idx=0; idx<5; idx++) {
551 dest[((*n)++)]=1;
552 dest[((*n)++)]=1;
553 dest[((*n)++)]=1;
554 dest[((*n)++)]=1;
555 dest[((*n)++)]=1;
556 dest[((*n)++)]=0;
557 dest[((*n)++)]=0;
558 dest[((*n)++)]=0;
559 dest[((*n)++)]=0;
560 dest[((*n)++)]=0;
561 }
562 }
e09f21fa 563}
564// compose fc/X fc/Y waveform (FSKx)
712ebfa6 565static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 566{
e0165dcf 567 uint8_t *dest = BigBuf_get_addr();
568 uint8_t halfFC = fc/2;
569 uint8_t wavesPerClock = clock/fc;
570 uint8_t mod = clock % fc; //modifier
571 uint8_t modAdj = fc/mod; //how often to apply modifier
44964fd1 572 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=true;
e0165dcf 573 // loop through clock - step field clock
574 for (uint8_t idx=0; idx < wavesPerClock; idx++){
575 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
576 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
577 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
578 *n += fc;
579 }
580 if (mod>0) (*modCnt)++;
581 if ((mod>0) && modAdjOk){ //fsk2
582 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
583 memset(dest+(*n), 0, fc-halfFC);
584 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
585 *n += fc;
586 }
587 }
588 if (mod>0 && !modAdjOk){ //fsk1
589 memset(dest+(*n), 0, mod-(mod/2));
590 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
591 *n += mod;
592 }
e09f21fa 593}
594
595// prepare a waveform pattern in the buffer based on the ID given then
596// simulate a HID tag until the button is pressed
be59094d 597void CmdHIDsimTAG(int hi2, int hi, int lo, int ledcontrol)
e09f21fa 598{
e0165dcf 599 int n=0, i=0;
600 /*
601 HID tag bitstream format
602 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
603 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
604 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
605 A fc8 is inserted before every 4 bits
606 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
607 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
608 */
609
be59094d 610 if (hi2>0x0FFFFFFF) {
611 DbpString("Tags can only have 44 or 84 bits. - USE lf simfsk for larger tags");
e0165dcf 612 return;
613 }
f2081c43 614 // set LF so we don't kill the bigbuf we are setting with simulation data.
615 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
616
e0165dcf 617 fc(0,&n);
618 // special start of frame marker containing invalid bit sequences
619 fc(8, &n); fc(8, &n); // invalid
620 fc(8, &n); fc(10, &n); // logical 0
621 fc(10, &n); fc(10, &n); // invalid
622 fc(8, &n); fc(10, &n); // logical 0
623
624 WDT_HIT();
be59094d 625 if (hi2 > 0 || hi > 0xFFF){
626 // manchester encode bits 91 to 64 (91-84 are part of the header)
627 for (i=27; i>=0; i--) {
628 if ((i%4)==3) fc(0,&n);
629 if ((hi2>>i)&1) {
630 fc(10, &n); fc(8, &n); // low-high transition
631 } else {
632 fc(8, &n); fc(10, &n); // high-low transition
633 }
634 }
635 WDT_HIT();
636 // manchester encode bits 63 to 32
637 for (i=31; i>=0; i--) {
638 if ((i%4)==3) fc(0,&n);
639 if ((hi>>i)&1) {
640 fc(10, &n); fc(8, &n); // low-high transition
641 } else {
642 fc(8, &n); fc(10, &n); // high-low transition
643 }
644 }
645 } else {
646 // manchester encode bits 43 to 32
647 for (i=11; i>=0; i--) {
648 if ((i%4)==3) fc(0,&n);
649 if ((hi>>i)&1) {
650 fc(10, &n); fc(8, &n); // low-high transition
651 } else {
652 fc(8, &n); fc(10, &n); // high-low transition
653 }
e0165dcf 654 }
655 }
656
657 WDT_HIT();
658 // manchester encode bits 31 to 0
659 for (i=31; i>=0; i--) {
660 if ((i%4)==3) fc(0,&n);
661 if ((lo>>i)&1) {
662 fc(10, &n); fc(8, &n); // low-high transition
663 } else {
664 fc(8, &n); fc(10, &n); // high-low transition
665 }
666 }
667
668 if (ledcontrol)
669 LED_A_ON();
670 SimulateTagLowFrequency(n, 0, ledcontrol);
671
672 if (ledcontrol)
673 LED_A_OFF();
e09f21fa 674}
675
676// prepare a waveform pattern in the buffer based on the ID given then
677// simulate a FSK tag until the button is pressed
678// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
679void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
680{
e0165dcf 681 int ledcontrol=1;
682 int n=0, i=0;
683 uint8_t fcHigh = arg1 >> 8;
684 uint8_t fcLow = arg1 & 0xFF;
685 uint16_t modCnt = 0;
686 uint8_t clk = arg2 & 0xFF;
687 uint8_t invert = (arg2 >> 8) & 1;
688
f2081c43 689 // set LF so we don't kill the bigbuf we are setting with simulation data.
690 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
691
e0165dcf 692 for (i=0; i<size; i++){
693 if (BitStream[i] == invert){
694 fcAll(fcLow, &n, clk, &modCnt);
695 } else {
696 fcAll(fcHigh, &n, clk, &modCnt);
697 }
698 }
699 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
700 /*Dbprintf("DEBUG: First 32:");
701 uint8_t *dest = BigBuf_get_addr();
702 i=0;
703 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
704 i+=16;
705 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
706 */
707 if (ledcontrol)
708 LED_A_ON();
709
710 SimulateTagLowFrequency(n, 0, ledcontrol);
711
712 if (ledcontrol)
713 LED_A_OFF();
e09f21fa 714}
715
716// compose ask waveform for one bit(ASK)
e0165dcf 717static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
e09f21fa 718{
e0165dcf 719 uint8_t *dest = BigBuf_get_addr();
720 uint8_t halfClk = clock/2;
721 // c = current bit 1 or 0
722 if (manchester==1){
723 memset(dest+(*n), c, halfClk);
724 memset(dest+(*n) + halfClk, c^1, halfClk);
725 } else {
726 memset(dest+(*n), c, clock);
727 }
728 *n += clock;
e09f21fa 729}
730
b41534d1 731static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
732{
e0165dcf 733 uint8_t *dest = BigBuf_get_addr();
734 uint8_t halfClk = clock/2;
735 if (c){
736 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
737 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
738 } else {
739 memset(dest+(*n), c ^ *phase, clock);
740 *phase ^= 1;
741 }
39611e3d 742 *n += clock;
b41534d1 743}
744
29ada8fc 745static void stAskSimBit(int *n, uint8_t clock) {
746 uint8_t *dest = BigBuf_get_addr();
747 uint8_t halfClk = clock/2;
748 //ST = .5 high .5 low 1.5 high .5 low 1 high
749 memset(dest+(*n), 1, halfClk);
750 memset(dest+(*n) + halfClk, 0, halfClk);
751 memset(dest+(*n) + clock, 1, clock + halfClk);
752 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
753 memset(dest+(*n) + clock*3, 1, clock);
754 *n += clock*4;
755}
756
e09f21fa 757// args clock, ask/man or askraw, invert, transmission separator
758void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
759{
e0165dcf 760 int ledcontrol = 1;
761 int n=0, i=0;
762 uint8_t clk = (arg1 >> 8) & 0xFF;
2b3af97d 763 uint8_t encoding = arg1 & 0xFF;
e0165dcf 764 uint8_t separator = arg2 & 1;
765 uint8_t invert = (arg2 >> 8) & 1;
766
f2081c43 767 // set LF so we don't kill the bigbuf we are setting with simulation data.
768 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
769
e0165dcf 770 if (encoding==2){ //biphase
771 uint8_t phase=0;
772 for (i=0; i<size; i++){
773 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
774 }
39611e3d 775 if (phase==1) { //run a second set inverted to keep phase in check
e0165dcf 776 for (i=0; i<size; i++){
777 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
778 }
779 }
780 } else { // ask/manchester || ask/raw
781 for (i=0; i<size; i++){
782 askSimBit(BitStream[i]^invert, &n, clk, encoding);
783 }
7666f460 784 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for ask/raw || biphase phase)
e0165dcf 785 for (i=0; i<size; i++){
786 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
787 }
788 }
789 }
29ada8fc 790 if (separator==1 && encoding == 1)
791 stAskSimBit(&n, clk);
792 else if (separator==1)
793 Dbprintf("sorry but separator option not yet available");
e0165dcf 794
795 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
796 //DEBUG
797 //Dbprintf("First 32:");
798 //uint8_t *dest = BigBuf_get_addr();
799 //i=0;
800 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
801 //i+=16;
802 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
39611e3d 803
709665b5 804 if (ledcontrol) LED_A_ON();
e0165dcf 805 SimulateTagLowFrequency(n, 0, ledcontrol);
709665b5 806 if (ledcontrol) LED_A_OFF();
e09f21fa 807}
808
809//carrier can be 2,4 or 8
810static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
811{
e0165dcf 812 uint8_t *dest = BigBuf_get_addr();
813 uint8_t halfWave = waveLen/2;
814 //uint8_t idx;
815 int i = 0;
816 if (phaseChg){
817 // write phase change
818 memset(dest+(*n), *curPhase^1, halfWave);
819 memset(dest+(*n) + halfWave, *curPhase, halfWave);
820 *n += waveLen;
821 *curPhase ^= 1;
822 i += waveLen;
823 }
824 //write each normal clock wave for the clock duration
825 for (; i < clk; i+=waveLen){
826 memset(dest+(*n), *curPhase, halfWave);
827 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
828 *n += waveLen;
829 }
e09f21fa 830}
831
832// args clock, carrier, invert,
833void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
834{
e0165dcf 835 int ledcontrol=1;
836 int n=0, i=0;
837 uint8_t clk = arg1 >> 8;
838 uint8_t carrier = arg1 & 0xFF;
839 uint8_t invert = arg2 & 0xFF;
840 uint8_t curPhase = 0;
f2081c43 841 // set LF so we don't kill the bigbuf we are setting with simulation data.
842 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
843
e0165dcf 844 for (i=0; i<size; i++){
845 if (BitStream[i] == curPhase){
44964fd1 846 pskSimBit(carrier, &n, clk, &curPhase, false);
e0165dcf 847 } else {
44964fd1 848 pskSimBit(carrier, &n, clk, &curPhase, true);
e0165dcf 849 }
850 }
851 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
852 //Dbprintf("DEBUG: First 32:");
853 //uint8_t *dest = BigBuf_get_addr();
854 //i=0;
855 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
856 //i+=16;
857 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
858
709665b5 859 if (ledcontrol) LED_A_ON();
e0165dcf 860 SimulateTagLowFrequency(n, 0, ledcontrol);
709665b5 861 if (ledcontrol) LED_A_OFF();
e09f21fa 862}
863
864// loop to get raw HID waveform then FSK demodulate the TAG ID from it
be59094d 865void CmdHIDdemodFSK(int findone, int *high2, int *high, int *low, int ledcontrol)
e09f21fa 866{
e0165dcf 867 uint8_t *dest = BigBuf_get_addr();
2eec55c8 868 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
869 size_t size;
e0165dcf 870 uint32_t hi2=0, hi=0, lo=0;
871 int idx=0;
1c70664a 872 int dummyIdx = 0;
e0165dcf 873 // Configure to go in 125Khz listen mode
874 LFSetupFPGAForADC(95, true);
e09f21fa 875
3cec7061 876 //clear read buffer
29b75739 877 BigBuf_Clear_keep_EM();
3cec7061 878
d10e08ae 879 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 880 WDT_HIT();
881 if (ledcontrol) LED_A_ON();
e09f21fa 882
883 DoAcquisition_default(-1,true);
884 // FSK demodulator
2eec55c8 885 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
886 size = 50*128*2; //big enough to catch 2 sequences of largest format
1c70664a 887 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo, &dummyIdx);
e0165dcf 888
2eec55c8 889 if (idx>0 && lo>0 && (size==96 || size==192)){
fc7a78f2 890 uint8_t bitlen = 0;
891 uint32_t fc = 0;
892 uint32_t cardnum = 0;
893 bool decoded = false;
894
2eec55c8 895 // go over previously decoded manchester data and decode into usable tag ID
fc7a78f2 896 if ((hi2 & 0x000FFFF) != 0){ //extra large HID tags 88/192 bits
897 uint32_t bp = hi2 & 0x000FFFFF;
898 bitlen = 63;
899 while (bp > 0) {
900 bp = bp >> 1;
901 bitlen++;
902 }
903 } else if ((hi >> 6) > 0) {
904 uint32_t bp = hi;
905 bitlen = 31;
906 while (bp > 0) {
907 bp = bp >> 1;
908 bitlen++;
909 }
910 } else if (((hi >> 5) & 1) == 0) {
911 bitlen = 37;
912 } else if ((hi & 0x0000001F) > 0 ) {
913 uint32_t bp = (hi & 0x0000001F);
914 bitlen = 31;
915 while (bp > 0) {
916 bp = bp >> 1;
917 bitlen++;
918 }
919 } else {
920 uint32_t bp = lo;
921 bitlen = 0;
922 while (bp > 0) {
923 bp = bp >> 1;
924 bitlen++;
925 }
926 }
927 switch (bitlen){
928 case 26:
929 cardnum = (lo>>1)&0xFFFF;
930 fc = (lo>>17)&0xFF;
931 decoded = true;
932 break;
933 case 35:
934 cardnum = (lo>>1)&0xFFFFF;
935 fc = ((hi&1)<<11)|(lo>>21);
936 decoded = true;
937 break;
e0165dcf 938 }
fc7a78f2 939
940 if (hi2 != 0) //extra large HID tags 88/192 bits
941 Dbprintf("TAG ID: %x%08x%08x (%d)",
942 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
943 else
944 Dbprintf("TAG ID: %x%08x (%d)",
945 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
946
947 if (decoded)
948 Dbprintf("Format Len: %dbits - FC: %d - Card: %d",
949 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
950
e0165dcf 951 if (findone){
952 if (ledcontrol) LED_A_OFF();
be59094d 953 *high2 = hi2;
e0165dcf 954 *high = hi;
955 *low = lo;
89696b8b 956 break;
e0165dcf 957 }
958 // reset
e0165dcf 959 }
2eec55c8 960 hi2 = hi = lo = idx = 0;
e0165dcf 961 WDT_HIT();
962 }
89696b8b 963
964 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
e0165dcf 965 DbpString("Stopped");
966 if (ledcontrol) LED_A_OFF();
e09f21fa 967}
968
dbf6e824
CY
969// loop to get raw HID waveform then FSK demodulate the TAG ID from it
970void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
971{
972 uint8_t *dest = BigBuf_get_addr();
dbf6e824 973 size_t size;
1c70664a 974 int idx=0, dummyIdx=0;
3cec7061 975 //clear read buffer
29b75739 976 BigBuf_Clear_keep_EM();
dbf6e824
CY
977 // Configure to go in 125Khz listen mode
978 LFSetupFPGAForADC(95, true);
979
d10e08ae 980 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
dbf6e824
CY
981
982 WDT_HIT();
983 if (ledcontrol) LED_A_ON();
984
985 DoAcquisition_default(-1,true);
986 // FSK demodulator
dbf6e824 987 size = 50*128*2; //big enough to catch 2 sequences of largest format
1c70664a 988 idx = AWIDdemodFSK(dest, &size, &dummyIdx);
dbf6e824 989
709665b5 990 if (idx<=0 || size!=96) continue;
991 // Index map
992 // 0 10 20 30 40 50 60
993 // | | | | | | |
994 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
995 // -----------------------------------------------------------------------------
996 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
997 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
998 // |---26 bit---| |-----117----||-------------142-------------|
999 // b = format bit len, o = odd parity of last 3 bits
1000 // f = facility code, c = card number
1001 // w = wiegand parity
1002 // (26 bit format shown)
1003
1004 //get raw ID before removing parities
1005 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
1006 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
1007 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
1008
1009 size = removeParity(dest, idx+8, 4, 1, 88);
1010 if (size != 66) continue;
1011 // ok valid card found!
1012
1013 // Index map
1014 // 0 10 20 30 40 50 60
1015 // | | | | | | |
1016 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
1017 // -----------------------------------------------------------------------------
1018 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
1019 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
1020 // |26 bit| |-117--| |-----142------|
1021 // b = format bit len, o = odd parity of last 3 bits
1022 // f = facility code, c = card number
1023 // w = wiegand parity
1024 // (26 bit format shown)
1025
1026 uint32_t fc = 0;
1027 uint32_t cardnum = 0;
1028 uint32_t code1 = 0;
1029 uint32_t code2 = 0;
1030 uint8_t fmtLen = bytebits_to_byte(dest,8);
1031 if (fmtLen==26){
1032 fc = bytebits_to_byte(dest+9, 8);
1033 cardnum = bytebits_to_byte(dest+17, 16);
1034 code1 = bytebits_to_byte(dest+8,fmtLen);
1035 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
1036 } else {
1037 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
1038 if (fmtLen>32){
1039 code1 = bytebits_to_byte(dest+8,fmtLen-32);
1040 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
1041 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
1042 } else{
1043 code1 = bytebits_to_byte(dest+8,fmtLen);
1044 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
dbf6e824 1045 }
dbf6e824 1046 }
709665b5 1047 if (findone){
1048 if (ledcontrol) LED_A_OFF();
89696b8b 1049 break;
709665b5 1050 }
1051 // reset
dbf6e824
CY
1052 idx = 0;
1053 WDT_HIT();
1054 }
89696b8b 1055 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
dbf6e824
CY
1056 DbpString("Stopped");
1057 if (ledcontrol) LED_A_OFF();
1058}
1059
e09f21fa 1060void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
1061{
e0165dcf 1062 uint8_t *dest = BigBuf_get_addr();
1063
1064 size_t size=0, idx=0;
1065 int clk=0, invert=0, errCnt=0, maxErr=20;
1066 uint32_t hi=0;
1067 uint64_t lo=0;
3cec7061 1068 //clear read buffer
29b75739 1069 BigBuf_Clear_keep_EM();
e0165dcf 1070 // Configure to go in 125Khz listen mode
1071 LFSetupFPGAForADC(95, true);
1072
d10e08ae 1073 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 1074
1075 WDT_HIT();
1076 if (ledcontrol) LED_A_ON();
1077
1078 DoAcquisition_default(-1,true);
1079 size = BigBuf_max_traceLen();
e0165dcf 1080 //askdemod and manchester decode
2eec55c8 1081 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
fef74fdc 1082 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
e0165dcf 1083 WDT_HIT();
1084
2eec55c8 1085 if (errCnt<0) continue;
1086
1087 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
1088 if (errCnt){
1089 if (size>64){
1090 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
1091 hi,
1092 (uint32_t)(lo>>32),
1093 (uint32_t)lo,
1094 (uint32_t)(lo&0xFFFF),
1095 (uint32_t)((lo>>16LL) & 0xFF),
1096 (uint32_t)(lo & 0xFFFFFF));
1097 } else {
1098 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
1099 (uint32_t)(lo>>32),
1100 (uint32_t)lo,
1101 (uint32_t)(lo&0xFFFF),
1102 (uint32_t)((lo>>16LL) & 0xFF),
1103 (uint32_t)(lo & 0xFFFFFF));
e0165dcf 1104 }
2eec55c8 1105
e0165dcf 1106 if (findone){
1107 if (ledcontrol) LED_A_OFF();
1108 *high=lo>>32;
1109 *low=lo & 0xFFFFFFFF;
89696b8b 1110 break;
e0165dcf 1111 }
e0165dcf 1112 }
1113 WDT_HIT();
2eec55c8 1114 hi = lo = size = idx = 0;
1115 clk = invert = errCnt = 0;
e0165dcf 1116 }
89696b8b 1117 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
e0165dcf 1118 DbpString("Stopped");
1119 if (ledcontrol) LED_A_OFF();
e09f21fa 1120}
1121
1122void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1123{
e0165dcf 1124 uint8_t *dest = BigBuf_get_addr();
1125 int idx=0;
1126 uint32_t code=0, code2=0;
1127 uint8_t version=0;
1128 uint8_t facilitycode=0;
1129 uint16_t number=0;
1c70664a 1130 int dummyIdx=0;
3cec7061 1131 //clear read buffer
29b75739 1132 BigBuf_Clear_keep_EM();
e0165dcf 1133 // Configure to go in 125Khz listen mode
1134 LFSetupFPGAForADC(95, true);
1135
d10e08ae 1136 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 1137 WDT_HIT();
1138 if (ledcontrol) LED_A_ON();
e09f21fa 1139 DoAcquisition_default(-1,true);
1140 //fskdemod and get start index
e0165dcf 1141 WDT_HIT();
1c70664a 1142 idx = IOdemodFSK(dest, BigBuf_max_traceLen(), &dummyIdx);
2eec55c8 1143 if (idx<0) continue;
1144 //valid tag found
1145
1146 //Index map
1147 //0 10 20 30 40 50 60
1148 //| | | | | | |
1149 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1150 //-----------------------------------------------------------------------------
1151 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
1152 //
1153 //XSF(version)facility:codeone+codetwo
1154 //Handle the data
1155 if(findone){ //only print binary if we are doing one
1156 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1157 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1158 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1159 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1160 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1161 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1162 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1163 }
1164 code = bytebits_to_byte(dest+idx,32);
1165 code2 = bytebits_to_byte(dest+idx+32,32);
1166 version = bytebits_to_byte(dest+idx+27,8); //14,4
1167 facilitycode = bytebits_to_byte(dest+idx+18,8);
1168 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1169
1170 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
1171 // if we're only looking for one tag
1172 if (findone){
1173 if (ledcontrol) LED_A_OFF();
1174 //LED_A_OFF();
1175 *high=code;
1176 *low=code2;
89696b8b 1177 break;
e0165dcf 1178 }
2eec55c8 1179 code=code2=0;
1180 version=facilitycode=0;
1181 number=0;
1182 idx=0;
1183
e0165dcf 1184 WDT_HIT();
1185 }
89696b8b 1186 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
e0165dcf 1187 DbpString("Stopped");
1188 if (ledcontrol) LED_A_OFF();
e09f21fa 1189}
1190
1191/*------------------------------
3606ac0a 1192 * T5555/T5557/T5567/T5577 routines
e09f21fa 1193 *------------------------------
709665b5 1194 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1195 *
3606ac0a 1196 * Relevant communication times in microsecond
e09f21fa 1197 * To compensate antenna falling times shorten the write times
1198 * and enlarge the gap ones.
7cfc777b 1199 * Q5 tags seems to have issues when these values changes.
e09f21fa 1200 */
4a3f1a37 1201#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1202#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1203#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1204#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
6fe5c94b 1205#define READ_GAP 15*8
7cfc777b 1206
1207void TurnReadLFOn(int delay) {
1208 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1209 // Give it a bit of time for the resonant antenna to settle.
b97311b1 1210 WaitUS(delay); //155*8 //50*8
7cfc777b 1211}
13d77ef9 1212
e09f21fa 1213// Write one bit to card
7cfc777b 1214void T55xxWriteBit(int bit) {
7cfc777b 1215 if (!bit)
3606ac0a 1216 TurnReadLFOn(WRITE_0);
e0165dcf 1217 else
3606ac0a 1218 TurnReadLFOn(WRITE_1);
e0165dcf 1219 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
b97311b1 1220 WaitUS(WRITE_GAP);
e09f21fa 1221}
1222
66837a03 1223// Send T5577 reset command then read stream (see if we can identify the start of the stream)
1224void T55xxResetRead(void) {
1225 LED_A_ON();
9f669cb2 1226 //clear buffer now so it does not interfere with timing later
29b75739 1227 BigBuf_Clear_keep_EM();
9f669cb2 1228
66837a03 1229 // Set up FPGA, 125kHz
1230 LFSetupFPGAForADC(95, true);
b97311b1 1231 StartTicks();
1232 // make sure tag is fully powered up...
1233 WaitMS(5);
1234
66837a03 1235 // Trigger T55x7 in mode.
1236 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
b97311b1 1237 WaitUS(START_GAP);
66837a03 1238
1239 // reset tag - op code 00
1240 T55xxWriteBit(0);
1241 T55xxWriteBit(0);
1242
66837a03 1243 TurnReadLFOn(READ_GAP);
1244
1245 // Acquisition
217cfb6b 1246 DoPartialAcquisition(0, true, BigBuf_max_traceLen(), 0);
66837a03 1247
1248 // Turn the field off
1249 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1250 cmd_send(CMD_ACK,0,0,0,0,0);
1251 LED_A_OFF();
1252}
1253
e09f21fa 1254// Write one card block in page 0, no lock
66837a03 1255void T55xxWriteBlockExt(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
7cfc777b 1256 LED_A_ON();
be2d41b7 1257 bool PwdMode = arg & 0x1;
1258 uint8_t Page = (arg & 0x2)>>1;
b97311b1 1259 bool testMode = arg & 0x4;
e0165dcf 1260 uint32_t i = 0;
1261
1262 // Set up FPGA, 125kHz
f4eadf8a 1263 LFSetupFPGAForADC(95, true);
b97311b1 1264 StartTicks();
1265 // make sure tag is fully powered up...
1266 WaitMS(5);
7cfc777b 1267 // Trigger T55x7 in mode.
e0165dcf 1268 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
b97311b1 1269 WaitUS(START_GAP);
e0165dcf 1270
b97311b1 1271 if (testMode) Dbprintf("TestMODE");
1272 // Std Opcode 10
1273 T55xxWriteBit(testMode ? 0 : 1);
1274 T55xxWriteBit(testMode ? 1 : Page); //Page 0
2229ee89 1275
1276 if (PwdMode) {
7cfc777b 1277 // Send Pwd
e0165dcf 1278 for (i = 0x80000000; i != 0; i >>= 1)
1279 T55xxWriteBit(Pwd & i);
1280 }
7cfc777b 1281 // Send Lock bit
e0165dcf 1282 T55xxWriteBit(0);
1283
7cfc777b 1284 // Send Data
e0165dcf 1285 for (i = 0x80000000; i != 0; i >>= 1)
1286 T55xxWriteBit(Data & i);
1287
7cfc777b 1288 // Send Block number
e0165dcf 1289 for (i = 0x04; i != 0; i >>= 1)
1290 T55xxWriteBit(Block & i);
1291
7cfc777b 1292 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
e0165dcf 1293 // so wait a little more)
b97311b1 1294
1295 // "there is a clock delay before programming"
2229ee89 1296 // - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
b97311b1 1297 // so we should wait 1 clock + 5.6ms then read response?
2229ee89 1298 // but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
b97311b1 1299 if (testMode) {
2229ee89 1300 //TESTMODE TIMING TESTS:
1301 // <566us does nothing
1302 // 566-568 switches between wiping to 0s and doing nothing
1303 // 5184 wipes and allows 1 block to be programmed.
1304 // indefinite power on wipes and then programs all blocks with bitshifted data sent.
1305 TurnReadLFOn(5184);
b97311b1 1306
b97311b1 1307 } else {
1308 TurnReadLFOn(20 * 1000);
be2d41b7 1309 //could attempt to do a read to confirm write took
1310 // as the tag should repeat back the new block
1311 // until it is reset, but to confirm it we would
b97311b1 1312 // need to know the current block 0 config mode for
1313 // modulation clock an other details to demod the response...
1314 // response should be (for t55x7) a 0 bit then (ST if on)
1315 // block data written in on repeat until reset.
e09f21fa 1316
2229ee89 1317 //DoPartialAcquisition(20, true, 12000);
1318 }
1319
7cfc777b 1320 // turn field off
1321 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
7cfc777b 1322 LED_A_OFF();
13d77ef9 1323}
1324
66837a03 1325// Write one card block in page 0, no lock
1326void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
1327 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1328 cmd_send(CMD_ACK,0,0,0,0,0);
1329}
1330
db829602 1331// Read one card block in page [page]
8e99ec25 1332void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
7cfc777b 1333 LED_A_ON();
be2d41b7 1334 bool PwdMode = arg0 & 0x1;
1335 uint8_t Page = (arg0 & 0x2) >> 1;
e0165dcf 1336 uint32_t i = 0;
bf85d22f 1337 bool RegReadMode = (Block == 0xFF);//regular read mode
e0165dcf 1338
7cfc777b 1339 //clear buffer now so it does not interfere with timing later
1340 BigBuf_Clear_ext(false);
f4eadf8a 1341
7cfc777b 1342 //make sure block is at max 7
1343 Block &= 0x7;
1344
0c8200f1 1345 // Set up FPGA, 125kHz to power up the tag
f4eadf8a 1346 LFSetupFPGAForADC(95, true);
b97311b1 1347 StartTicks();
1348 // make sure tag is fully powered up...
1349 WaitMS(5);
0c8200f1 1350 // Trigger T55x7 Direct Access Mode with start gap
e0165dcf 1351 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
b97311b1 1352 WaitUS(START_GAP);
e0165dcf 1353
3606ac0a 1354 // Opcode 1[page]
e0165dcf 1355 T55xxWriteBit(1);
be2d41b7 1356 T55xxWriteBit(Page); //Page 0
7cfc777b 1357
be2d41b7 1358 if (PwdMode){
7cfc777b 1359 // Send Pwd
e0165dcf 1360 for (i = 0x80000000; i != 0; i >>= 1)
1361 T55xxWriteBit(Pwd & i);
1362 }
be2d41b7 1363 // Send a zero bit separation
1364 T55xxWriteBit(0);
7cfc777b 1365
be2d41b7 1366 // Send Block number (if direct access mode)
1367 if (!RegReadMode)
8e99ec25 1368 for (i = 0x04; i != 0; i >>= 1)
1369 T55xxWriteBit(Block & i);
e0165dcf 1370
1371 // Turn field on to read the response
bf85d22f 1372 // 137*8 seems to get to the start of data pretty well...
1373 // but we want to go past the start and let the repeating data settle in...
1374 TurnReadLFOn(210*8);
f4eadf8a 1375
7cfc777b 1376 // Acquisition
b97311b1 1377 // Now do the acquisition
217cfb6b 1378 DoPartialAcquisition(0, true, 12000, 0);
b97311b1 1379
7cfc777b 1380 // Turn the field off
e0165dcf 1381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
7cfc777b 1382 cmd_send(CMD_ACK,0,0,0,0,0);
1383 LED_A_OFF();
e09f21fa 1384}
1385
be2d41b7 1386void T55xxWakeUp(uint32_t Pwd){
1387 LED_B_ON();
1388 uint32_t i = 0;
1389
1390 // Set up FPGA, 125kHz
1391 LFSetupFPGAForADC(95, true);
b97311b1 1392 StartTicks();
1393 // make sure tag is fully powered up...
1394 WaitMS(5);
be2d41b7 1395
1396 // Trigger T55x7 Direct Access Mode
1397 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
b97311b1 1398 WaitUS(START_GAP);
be2d41b7 1399
1400 // Opcode 10
1401 T55xxWriteBit(1);
1402 T55xxWriteBit(0); //Page 0
1403
1404 // Send Pwd
1405 for (i = 0x80000000; i != 0; i >>= 1)
1406 T55xxWriteBit(Pwd & i);
1407
1408 // Turn and leave field on to let the begin repeating transmission
1409 TurnReadLFOn(20*1000);
1410}
e09f21fa 1411
1412/*-------------- Cloning routines -----------*/
3606ac0a 1413
1414void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1415 // write last block first and config block last (if included)
66837a03 1416 for (uint8_t i = numblocks+startblock; i > startblock; i--) {
66837a03 1417 T55xxWriteBlockExt(blockdata[i-1],i-1,0,0);
1418 }
3606ac0a 1419}
1420
5f84531b
SS
1421// Copy a HID-like card (e.g. HID Proximity, Paradox) to a T55x7 compatible card
1422void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT, uint8_t preamble) {
3606ac0a 1423 uint32_t data[] = {0,0,0,0,0,0,0};
3606ac0a 1424 uint8_t last_block = 0;
e0165dcf 1425
3606ac0a 1426 if (longFMT) {
e0165dcf 1427 // Ensure no more than 84 bits supplied
1428 if (hi2>0xFFFFF) {
1429 DbpString("Tags can only have 84 bits.");
1430 return;
1431 }
1432 // Build the 6 data blocks for supplied 84bit ID
1433 last_block = 6;
5f84531b
SS
1434 // load preamble & long format identifier (9E manchester encoded)
1435 data[1] = (preamble << 24) | 0x96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
3606ac0a 1436 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1437 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1438 data[3] = manchesterEncode2Bytes(hi >> 16);
1439 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1440 data[5] = manchesterEncode2Bytes(lo >> 16);
1441 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
5f84531b 1442 } else {
e0165dcf 1443 // Ensure no more than 44 bits supplied
1444 if (hi>0xFFF) {
1445 DbpString("Tags can only have 44 bits.");
1446 return;
1447 }
e0165dcf 1448 // Build the 3 data blocks for supplied 44bit ID
1449 last_block = 3;
3606ac0a 1450 // load preamble
5f84531b 1451 data[1] = (preamble << 24) | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
3606ac0a 1452 data[2] = manchesterEncode2Bytes(lo >> 16);
1453 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
e0165dcf 1454 }
3606ac0a 1455 // load chip config block
1456 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
e0165dcf 1457
76346455 1458 //TODO add selection of chip for Q5 or T55x7
1459 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1460
e0165dcf 1461 LED_D_ON();
1462 // Program the data blocks for supplied ID
1463 // and the block 0 for HID format
3606ac0a 1464 WriteT55xx(data, 0, last_block+1);
e0165dcf 1465
1466 LED_D_OFF();
1467
1468 DbpString("DONE!");
e09f21fa 1469}
1470
9f669cb2 1471void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
3606ac0a 1472 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
76346455 1473 //TODO add selection of chip for Q5 or T55x7
1474 // data[0] = (((64-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
e09f21fa 1475
e0165dcf 1476 LED_D_ON();
1477 // Program the data blocks for supplied ID
3606ac0a 1478 // and the block 0 config
1479 WriteT55xx(data, 0, 3);
e09f21fa 1480
e0165dcf 1481 LED_D_OFF();
e09f21fa 1482
e0165dcf 1483 DbpString("DONE!");
e09f21fa 1484}
1485
3606ac0a 1486// Clone Indala 64-bit tag by UID to T55x7
1487void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1488 //Program the 2 data blocks for supplied 64bit UID
1489 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1490 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
76346455 1491 //TODO add selection of chip for Q5 or T55x7
1492 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1493
3606ac0a 1494 WriteT55xx(data, 0, 3);
1495 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1496 // T5567WriteBlock(0x603E1042,0);
1497 DbpString("DONE!");
1498}
1499// Clone Indala 224-bit tag by UID to T55x7
66837a03 1500void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
3606ac0a 1501 //Program the 7 data blocks for supplied 224bit UID
1502 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1503 // and the block 0 for Indala224 format
1dae9811 1504 //Config for Indala (RF/32;PSK2 with RF/2;Maxblock=7)
1505 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK2 | (7 << T55x7_MAXBLOCK_SHIFT);
76346455 1506 //TODO add selection of chip for Q5 or T55x7
1dae9811 1507 // data[0] = (((32-2)>>1)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK2 | 7 << T5555_MAXBLOCK_SHIFT;
3606ac0a 1508 WriteT55xx(data, 0, 8);
1509 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1510 // T5567WriteBlock(0x603E10E2,0);
1511 DbpString("DONE!");
1512}
709665b5 1513// clone viking tag to T55xx
1514void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1515 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
b97311b1 1516 if (Q5) data[0] = T5555_SET_BITRATE(32) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
709665b5 1517 // Program the data blocks for supplied ID and the block 0 config
1518 WriteT55xx(data, 0, 3);
1519 LED_D_OFF();
1520 cmd_send(CMD_ACK,0,0,0,0,0);
1521}
3606ac0a 1522
e09f21fa 1523// Define 9bit header for EM410x tags
3606ac0a 1524#define EM410X_HEADER 0x1FF
e09f21fa 1525#define EM410X_ID_LENGTH 40
1526
66837a03 1527void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
e0165dcf 1528 int i, id_bit;
1529 uint64_t id = EM410X_HEADER;
1530 uint64_t rev_id = 0; // reversed ID
1531 int c_parity[4]; // column parity
1532 int r_parity = 0; // row parity
1533 uint32_t clock = 0;
1534
1535 // Reverse ID bits given as parameter (for simpler operations)
1536 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1537 if (i < 32) {
1538 rev_id = (rev_id << 1) | (id_lo & 1);
1539 id_lo >>= 1;
1540 } else {
1541 rev_id = (rev_id << 1) | (id_hi & 1);
1542 id_hi >>= 1;
1543 }
1544 }
1545
1546 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1547 id_bit = rev_id & 1;
1548
1549 if (i % 4 == 0) {
1550 // Don't write row parity bit at start of parsing
1551 if (i)
1552 id = (id << 1) | r_parity;
1553 // Start counting parity for new row
1554 r_parity = id_bit;
1555 } else {
1556 // Count row parity
1557 r_parity ^= id_bit;
1558 }
1559
1560 // First elements in column?
1561 if (i < 4)
1562 // Fill out first elements
1563 c_parity[i] = id_bit;
1564 else
1565 // Count column parity
1566 c_parity[i % 4] ^= id_bit;
1567
1568 // Insert ID bit
1569 id = (id << 1) | id_bit;
1570 rev_id >>= 1;
1571 }
1572
1573 // Insert parity bit of last row
1574 id = (id << 1) | r_parity;
1575
1576 // Fill out column parity at the end of tag
1577 for (i = 0; i < 4; ++i)
1578 id = (id << 1) | c_parity[i];
1579
1580 // Add stop bit
1581 id <<= 1;
1582
1583 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1584 LED_D_ON();
1585
1586 // Write EM410x ID
72c5877a 1587 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
76346455 1588
1589 clock = (card & 0xFF00) >> 8;
1590 clock = (clock == 0) ? 64 : clock;
1591 Dbprintf("Clock rate: %d", clock);
1592 if (card & 0xFF) { //t55x7
1593 clock = GetT55xxClockBit(clock);
3606ac0a 1594 if (clock == 0) {
e0165dcf 1595 Dbprintf("Invalid clock rate: %d", clock);
1596 return;
1597 }
3606ac0a 1598 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
76346455 1599 } else { //t5555 (Q5)
b97311b1 1600 data[0] = T5555_SET_BITRATE(clock) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
e0165dcf 1601 }
3606ac0a 1602
1603 WriteT55xx(data, 0, 3);
e0165dcf 1604
1605 LED_D_OFF();
1606 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1607 (uint32_t)(id >> 32), (uint32_t)id);
e09f21fa 1608}
1609
e09f21fa 1610//-----------------------------------
1611// EM4469 / EM4305 routines
1612//-----------------------------------
1613#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1614#define FWD_CMD_WRITE 0xA
1615#define FWD_CMD_READ 0x9
1616#define FWD_CMD_DISABLE 0x5
1617
e09f21fa 1618uint8_t forwardLink_data[64]; //array of forwarded bits
1619uint8_t * forward_ptr; //ptr for forward message preparation
1620uint8_t fwd_bit_sz; //forwardlink bit counter
1621uint8_t * fwd_write_ptr; //forwardlink bit pointer
1622
1623//====================================================================
1624// prepares command bits
1625// see EM4469 spec
1626//====================================================================
1627//--------------------------------------------------------------------
db829602 1628// VALUES TAKEN FROM EM4x function: SendForward
1629// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1630// WRITE_GAP = 128; (16*8)
1631// WRITE_1 = 256 32*8; (32*8)
1632
1633// These timings work for 4469/4269/4305 (with the 55*8 above)
1634// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1635
e09f21fa 1636uint8_t Prepare_Cmd( uint8_t cmd ) {
e09f21fa 1637
e0165dcf 1638 *forward_ptr++ = 0; //start bit
1639 *forward_ptr++ = 0; //second pause for 4050 code
e09f21fa 1640
e0165dcf 1641 *forward_ptr++ = cmd;
1642 cmd >>= 1;
1643 *forward_ptr++ = cmd;
1644 cmd >>= 1;
1645 *forward_ptr++ = cmd;
1646 cmd >>= 1;
1647 *forward_ptr++ = cmd;
e09f21fa 1648
e0165dcf 1649 return 6; //return number of emited bits
e09f21fa 1650}
1651
1652//====================================================================
1653// prepares address bits
1654// see EM4469 spec
1655//====================================================================
e09f21fa 1656uint8_t Prepare_Addr( uint8_t addr ) {
e09f21fa 1657
e0165dcf 1658 register uint8_t line_parity;
e09f21fa 1659
e0165dcf 1660 uint8_t i;
1661 line_parity = 0;
1662 for(i=0;i<6;i++) {
1663 *forward_ptr++ = addr;
1664 line_parity ^= addr;
1665 addr >>= 1;
1666 }
e09f21fa 1667
e0165dcf 1668 *forward_ptr++ = (line_parity & 1);
e09f21fa 1669
e0165dcf 1670 return 7; //return number of emited bits
e09f21fa 1671}
1672
1673//====================================================================
1674// prepares data bits intreleaved with parity bits
1675// see EM4469 spec
1676//====================================================================
e09f21fa 1677uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
e0165dcf 1678
1679 register uint8_t line_parity;
1680 register uint8_t column_parity;
1681 register uint8_t i, j;
1682 register uint16_t data;
1683
1684 data = data_low;
1685 column_parity = 0;
1686
1687 for(i=0; i<4; i++) {
1688 line_parity = 0;
1689 for(j=0; j<8; j++) {
1690 line_parity ^= data;
1691 column_parity ^= (data & 1) << j;
1692 *forward_ptr++ = data;
1693 data >>= 1;
1694 }
1695 *forward_ptr++ = line_parity;
1696 if(i == 1)
1697 data = data_hi;
1698 }
1699
1700 for(j=0; j<8; j++) {
1701 *forward_ptr++ = column_parity;
1702 column_parity >>= 1;
1703 }
1704 *forward_ptr = 0;
1705
1706 return 45; //return number of emited bits
e09f21fa 1707}
1708
1709//====================================================================
1710// Forward Link send function
1711// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1712// fwd_bit_count set with number of bits to be sent
1713//====================================================================
1714void SendForward(uint8_t fwd_bit_count) {
1715
e0165dcf 1716 fwd_write_ptr = forwardLink_data;
1717 fwd_bit_sz = fwd_bit_count;
1718
40c6a02b 1719 // Set up FPGA, 125kHz or 95 divisor
7cfc777b 1720 LFSetupFPGAForADC(95, true);
fa1e00cf 1721
e0165dcf 1722 // force 1st mod pulse (start gap must be longer for 4305)
1723 fwd_bit_sz--; //prepare next bit modulation
1724 fwd_write_ptr++;
1725 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
62a38cc8 1726 WaitUS(55*8); //55 cycles off (8us each)for 4305 //another reader has 37 here...
e0165dcf 1727 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
62a38cc8 1728 WaitUS(18*8); //18 cycles on (8us each)
e0165dcf 1729
1730 // now start writting
1731 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1732 if(((*fwd_write_ptr++) & 1) == 1)
40c6a02b 1733 WaitUS(32*8); //32 cycles at 125Khz (8us each)
e0165dcf 1734 else {
1735 //These timings work for 4469/4269/4305 (with the 55*8 above)
1736 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
62a38cc8 1737 WaitUS(23*8); //23 cycles off (8us each)
e0165dcf 1738 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
62a38cc8 1739 WaitUS(18*8); //18 cycles on (8us each)
e0165dcf 1740 }
1741 }
e09f21fa 1742}
1743
1744void EM4xLogin(uint32_t Password) {
1745
e0165dcf 1746 uint8_t fwd_bit_count;
e09f21fa 1747
e0165dcf 1748 forward_ptr = forwardLink_data;
1749 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1750 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
e09f21fa 1751
e0165dcf 1752 SendForward(fwd_bit_count);
e09f21fa 1753
e0165dcf 1754 //Wait for command to complete
1755 SpinDelay(20);
e09f21fa 1756}
1757
1758void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1759
e0165dcf 1760 uint8_t fwd_bit_count;
7cfc777b 1761
1762 // Clear destination buffer before sending the command
709665b5 1763 BigBuf_Clear_ext(false);
e0165dcf 1764
7666f460 1765 LED_A_ON();
40c6a02b 1766 StartTicks();
e0165dcf 1767 //If password mode do login
1768 if (PwdMode == 1) EM4xLogin(Pwd);
1769
1770 forward_ptr = forwardLink_data;
1771 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1772 fwd_bit_count += Prepare_Addr( Address );
1773
e0165dcf 1774 SendForward(fwd_bit_count);
40c6a02b 1775 WaitUS(400);
e0165dcf 1776 // Now do the acquisition
217cfb6b 1777 DoPartialAcquisition(20, true, 6000, 1000);
7666f460 1778
e0165dcf 1779 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
7666f460 1780 LED_A_OFF();
7cfc777b 1781 cmd_send(CMD_ACK,0,0,0,0,0);
e09f21fa 1782}
1783
7666f460 1784void EM4xWriteWord(uint32_t flag, uint32_t Data, uint32_t Pwd) {
1785
1786 bool PwdMode = (flag & 0xF);
1787 uint8_t Address = (flag >> 8) & 0xFF;
e0165dcf 1788 uint8_t fwd_bit_count;
e09f21fa 1789
7666f460 1790 //clear buffer now so it does not interfere with timing later
1791 BigBuf_Clear_ext(false);
1792
1793 LED_A_ON();
40c6a02b 1794 StartTicks();
e0165dcf 1795 //If password mode do login
7666f460 1796 if (PwdMode) EM4xLogin(Pwd);
e09f21fa 1797
e0165dcf 1798 forward_ptr = forwardLink_data;
1799 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1800 fwd_bit_count += Prepare_Addr( Address );
1801 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
e09f21fa 1802
e0165dcf 1803 SendForward(fwd_bit_count);
e09f21fa 1804
e0165dcf 1805 //Wait for write to complete
a37228c8 1806 //SpinDelay(10);
7666f460 1807
40c6a02b 1808 WaitUS(6500);
7666f460 1809 //Capture response if one exists
217cfb6b 1810 DoPartialAcquisition(20, true, 6000, 1000);
7666f460 1811
e0165dcf 1812 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
7666f460 1813 LED_A_OFF();
1814 cmd_send(CMD_ACK,0,0,0,0,0);
e09f21fa 1815}
e04475c4 1816/*
1817Reading a COTAG.
1818
1819COTAG needs the reader to send a startsequence and the card has an extreme slow datarate.
1820because of this, we can "sample" the data signal but we interpreate it to Manchester direct.
1821
1822READER START SEQUENCE:
1823burst 800 us, gap 2.2 msecs
1824burst 3.6 msecs gap 2.2 msecs
1825burst 800 us gap 2.2 msecs
1826pulse 3.6 msecs
1827
1828This triggers a COTAG tag to response
1829*/
1830void Cotag(uint32_t arg0) {
1831
1832#define OFF { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); }
1833#define ON(x) { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); }
1834
1835 uint8_t rawsignal = arg0 & 0xF;
1836
1837 LED_A_ON();
1838
1839 // Switching to LF image on FPGA. This might empty BigBuff
1840 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1841
1842 //clear buffer now so it does not interfere with timing later
1843 BigBuf_Clear_ext(false);
1844
1845 // Set up FPGA, 132kHz to power up the tag
1846 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89);
1847 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1848
1849 // Connect the A/D to the peak-detected low-frequency path.
1850 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1851
1852 // Now set up the SSC to get the ADC samples that are now streaming at us.
6a5d4e17 1853 FpgaSetupSsc(FPGA_MAJOR_MODE_LF_ADC);
e04475c4 1854
1855 // start clock - 1.5ticks is 1us
1856 StartTicks();
1857
1858 //send COTAG start pulse
1859 ON(740) OFF
1860 ON(3330) OFF
1861 ON(740) OFF
1862 ON(1000)
1863
1864 switch(rawsignal) {
1865 case 0: doCotagAcquisition(50000); break;
1866 case 1: doCotagAcquisitionManchester(); break;
b9957414 1867 case 2: DoAcquisition_config(true, 0); break;
e04475c4 1868 }
1869
1870 // Turn the field off
1871 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1872 cmd_send(CMD_ACK,0,0,0,0,0);
1873 LED_A_OFF();
1874}
Impressum, Datenschutz