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Bugfixes for LF FDX
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e30c654b 1//-----------------------------------------------------------------------------
e30c654b 2// Jonathan Westhues, Sept 2005
bd20f8f4 3//
4// This code is licensed to you under the terms of the GNU GPL, version 2 or,
5// at your option, any later version. See the LICENSE.txt file for the text of
6// the license.
7//-----------------------------------------------------------------------------
8// Utility functions used in many places, not specific to any piece of code.
e30c654b 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
f7e3ed82 12#include "util.h"
9ab7a6c7 13#include "string.h"
9492e0b0 14#include "apps.h"
7d5ebac9 15#include "BigBuf.h"
e30c654b 16
787b5bd8 17
18
19void print_result(char *name, uint8_t *buf, size_t len) {
20 uint8_t *p = buf;
21
22 if ( len % 16 == 0 ) {
23 for(; p-buf < len; p += 16)
24 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
25 name,
26 p-buf,
27 len,
28 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
29 );
30 }
31 else {
32 for(; p-buf < len; p += 8)
33 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
34 }
35}
36
195af472 37size_t nbytes(size_t nbits) {
665775c8 38 return (nbits >> 3)+((nbits % 8) > 0);
195af472 39}
40
81cd0474 41uint32_t SwapBits(uint32_t value, int nrbits) {
42 int i;
43 uint32_t newvalue = 0;
44 for(i = 0; i < nrbits; i++) {
45 newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
46 }
47 return newvalue;
48}
49
f7e3ed82 50void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
e30c654b 51{
52 while (len--) {
f7e3ed82 53 dest[len] = (uint8_t) n;
e30c654b 54 n >>= 8;
55 }
56}
57
f7e3ed82 58uint64_t bytes_to_num(uint8_t* src, size_t len)
e30c654b 59{
60 uint64_t num = 0;
61 while (len--)
62 {
63 num = (num << 8) | (*src);
64 src++;
65 }
66 return num;
67}
68
787b5bd8 69// RotateLeft - Ultralight, Desfire
70void rol(uint8_t *data, const size_t len){
71 uint8_t first = data[0];
72 for (size_t i = 0; i < len-1; i++) {
73 data[i] = data[i+1];
74 }
75 data[len-1] = first;
76}
77void lsl (uint8_t *data, size_t len) {
78 for (size_t n = 0; n < len - 1; n++) {
79 data[n] = (data[n] << 1) | (data[n+1] >> 7);
80 }
81 data[len - 1] <<= 1;
82}
83
e30c654b 84void LEDsoff()
85{
86 LED_A_OFF();
87 LED_B_OFF();
88 LED_C_OFF();
89 LED_D_OFF();
90}
91
3d057cfb
SG
92void LEDson()
93{
94 LED_A_ON();
95 LED_B_ON();
96 LED_C_ON();
97 LED_D_ON();
98}
99
100void LEDsinvert()
101{
102 LED_A_INV();
103 LED_B_INV();
104 LED_C_INV();
105 LED_D_INV();
106}
107
e30c654b 108// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
109void LED(int led, int ms)
110{
111 if (led & LED_RED)
112 LED_C_ON();
113 if (led & LED_ORANGE)
114 LED_A_ON();
115 if (led & LED_GREEN)
116 LED_B_ON();
117 if (led & LED_RED2)
118 LED_D_ON();
119
120 if (!ms)
121 return;
122
123 SpinDelay(ms);
124
125 if (led & LED_RED)
126 LED_C_OFF();
127 if (led & LED_ORANGE)
128 LED_A_OFF();
129 if (led & LED_GREEN)
130 LED_B_OFF();
131 if (led & LED_RED2)
132 LED_D_OFF();
133}
134
135
136// Determine if a button is double clicked, single clicked,
137// not clicked, or held down (for ms || 1sec)
138// In general, don't use this function unless you expect a
139// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
140int BUTTON_CLICKED(int ms)
141{
142 // Up to 500ms in between clicks to mean a double click
143 int ticks = (48000 * (ms ? ms : 1000)) >> 10;
144
145 // If we're not even pressed, forget about it!
146 if (!BUTTON_PRESS())
147 return BUTTON_NO_CLICK;
148
149 // Borrow a PWM unit for my real-time clock
150 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
151 // 48 MHz / 1024 gives 46.875 kHz
152 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
153 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
154 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
155
f7e3ed82 156 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 157
158 int letoff = 0;
159 for(;;)
160 {
f7e3ed82 161 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 162
163 // We haven't let off the button yet
164 if (!letoff)
165 {
166 // We just let it off!
167 if (!BUTTON_PRESS())
168 {
169 letoff = 1;
170
171 // reset our timer for 500ms
172 start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
173 ticks = (48000 * (500)) >> 10;
174 }
175
176 // Still haven't let it off
177 else
178 // Have we held down a full second?
f7e3ed82 179 if (now == (uint16_t)(start + ticks))
e30c654b 180 return BUTTON_HOLD;
181 }
182
183 // We already let off, did we click again?
184 else
185 // Sweet, double click!
186 if (BUTTON_PRESS())
187 return BUTTON_DOUBLE_CLICK;
188
189 // Have we ran out of time to double click?
190 else
f7e3ed82 191 if (now == (uint16_t)(start + ticks))
e30c654b 192 // At least we did a single click
193 return BUTTON_SINGLE_CLICK;
194
195 WDT_HIT();
196 }
197
198 // We should never get here
199 return BUTTON_ERROR;
200}
201
202// Determine if a button is held down
203int BUTTON_HELD(int ms)
204{
205 // If button is held for one second
206 int ticks = (48000 * (ms ? ms : 1000)) >> 10;
207
208 // If we're not even pressed, forget about it!
209 if (!BUTTON_PRESS())
210 return BUTTON_NO_CLICK;
211
212 // Borrow a PWM unit for my real-time clock
213 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
214 // 48 MHz / 1024 gives 46.875 kHz
215 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
216 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
217 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
218
f7e3ed82 219 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 220
221 for(;;)
222 {
f7e3ed82 223 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 224
225 // As soon as our button let go, we didn't hold long enough
226 if (!BUTTON_PRESS())
227 return BUTTON_SINGLE_CLICK;
228
229 // Have we waited the full second?
230 else
f7e3ed82 231 if (now == (uint16_t)(start + ticks))
e30c654b 232 return BUTTON_HOLD;
233
234 WDT_HIT();
235 }
236
237 // We should never get here
238 return BUTTON_ERROR;
239}
240
241// attempt at high resolution microsecond timer
242// beware: timer counts in 21.3uS increments (1024/48Mhz)
243void SpinDelayUs(int us)
244{
245 int ticks = (48*us) >> 10;
246
247 // Borrow a PWM unit for my real-time clock
248 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
249 // 48 MHz / 1024 gives 46.875 kHz
250 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
251 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
252 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
253
f7e3ed82 254 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b 255
256 for(;;) {
f7e3ed82 257 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
258 if (now == (uint16_t)(start + ticks))
e30c654b 259 return;
260
261 WDT_HIT();
262 }
263}
264
265void SpinDelay(int ms)
266{
267 // convert to uS and call microsecond delay function
268 SpinDelayUs(ms*1000);
269}
270
271/* Similar to FpgaGatherVersion this formats stored version information
272 * into a string representation. It takes a pointer to the struct version_information,
273 * verifies the magic properties, then stores a formatted string, prefixed by
274 * prefix in dst.
275 */
276void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
277{
278 struct version_information *v = (struct version_information*)version_information;
279 dst[0] = 0;
2ed270a8 280 strncat(dst, prefix, len-1);
e30c654b 281 if(v->magic != VERSION_INFORMATION_MAGIC) {
8e074056 282 strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);
e30c654b 283 return;
284 }
285 if(v->versionversion != 1) {
8e074056 286 strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);
e30c654b 287 return;
288 }
289 if(!v->present) {
8e074056 290 strncat(dst, "Version information not available\n", len - strlen(dst) - 1);
e30c654b 291 return;
292 }
293
cba867f2 294 strncat(dst, v->gitversion, len - strlen(dst) - 1);
e30c654b 295 if(v->clean == 0) {
cba867f2 296 strncat(dst, "-unclean", len - strlen(dst) - 1);
e30c654b 297 } else if(v->clean == 2) {
cba867f2 298 strncat(dst, "-suspect", len - strlen(dst) - 1);
e30c654b 299 }
300
cba867f2
MHS
301 strncat(dst, " ", len - strlen(dst) - 1);
302 strncat(dst, v->buildtime, len - strlen(dst) - 1);
8e074056 303 strncat(dst, "\n", len - strlen(dst) - 1);
e30c654b 304}
9ca155ba 305
4058a2d7 306
9ca155ba
M
307// -------------------------------------------------------------------------
308// timer lib
309// -------------------------------------------------------------------------
310// test procedure:
311//
312// ti = GetTickCount();
313// SpinDelay(1000);
314// ti = GetTickCount() - ti;
315// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
316
317void StartTickCount()
318{
bfb01844 319 // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
320 // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
321 uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
322 // set RealTimeCounter divider to count at 1kHz:
323 AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
324 // note: worst case precision is approx 2.5%
9ca155ba
M
325}
326
4058a2d7 327
9ca155ba
M
328/*
329* Get the current count.
330*/
331uint32_t RAMFUNC GetTickCount(){
8f51ddb0 332 return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
9ca155ba
M
333}
334
4058a2d7 335
8f51ddb0
M
336// -------------------------------------------------------------------------
337// microseconds timer
338// -------------------------------------------------------------------------
339void StartCountUS()
340{
341 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
342// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
343 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
344
345 // fast clock
346 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
347 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
348 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
349 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
350 AT91C_BASE_TC0->TC_RA = 1;
351 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
352
353 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
354 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
1c611bbd 355
8f51ddb0
M
356 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
357 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
358 AT91C_BASE_TCB->TCB_BCR = 1;
1c611bbd 359 }
8f51ddb0 360
4058a2d7 361
8f51ddb0 362uint32_t RAMFUNC GetCountUS(){
e04475c4 363 return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); //was /15) * 10);
8f51ddb0
M
364}
365
4058a2d7 366
8f51ddb0
M
367static uint32_t GlobalUsCounter = 0;
368
369uint32_t RAMFUNC GetDeltaCountUS(){
370 uint32_t g_cnt = GetCountUS();
371 uint32_t g_res = g_cnt - GlobalUsCounter;
372 GlobalUsCounter = g_cnt;
373 return g_res;
374}
375
376
1c611bbd 377// -------------------------------------------------------------------------
7bc95e2e 378// Timer for iso14443 commands. Uses ssp_clk from FPGA
1c611bbd 379// -------------------------------------------------------------------------
7bc95e2e 380void StartCountSspClk()
1c611bbd 381{
382 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers
383 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
384 | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
385 | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
386
387 // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
388 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
389 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
390 | AT91C_TC_CPCSTOP // Stop clock on RC compare
391 | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
8c6cca0b 392 | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16 ... 13,56MHz/4)
1c611bbd 393 | AT91C_TC_ENETRG // Enable external trigger event
394 | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
395 | AT91C_TC_WAVE // Waveform Mode
396 | AT91C_TC_AEEVT_SET // Set TIOA1 on external event
397 | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
8c6cca0b 398 AT91C_BASE_TC1->TC_RC = 0x02; // RC Compare value = 0x02
1c611bbd 399
400 // use TC0 to count TIOA1 pulses
7bc95e2e 401 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
1c611bbd 402 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
403 | AT91C_TC_WAVE // Waveform Mode
404 | AT91C_TC_WAVESEL_UP // just count
405 | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
406 | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
407 AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
408 AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
409
410 // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
411 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
412 AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
413 | AT91C_TC_WAVE // Waveform Mode
414 | AT91C_TC_WAVESEL_UP; // just count
415
1c611bbd 416 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
417 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
418 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
9492e0b0 419
7bc95e2e 420 //
8c6cca0b 421 // synchronize the counter with the ssp_frame signal. Note: FPGA must be in a FPGA mode with SSC transfer, otherwise SSC_FRAME and SSC_CLK signals would not be present
7bc95e2e 422 //
423 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
9492e0b0 424 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
7bc95e2e 425 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
426 // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
427 // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
1c611bbd 428 AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
7bc95e2e 429 // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
430 // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
431 // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
432 // (just started with the transfer of the 4th Bit).
433 // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
434 // we can use the counter.
4058a2d7 435 while (AT91C_BASE_TC0->TC_CV < 0xFFFF);
436 // Note: needs one more SSP_CLK cycle (1.18 us) until TC2 resets. Don't call GetCountSspClk() that soon.
1c611bbd 437}
4058a2d7 438
439
e04475c4 440void ResetSspClk(void) {
441 //enable clock of timer and software trigger
442 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
443 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
444 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
445 while (AT91C_BASE_TC2->TC_CV > 0);
446}
4058a2d7 447
448
8c6cca0b 449uint32_t GetCountSspClk(){
450 uint32_t hi, lo;
451
452 do {
453 hi = AT91C_BASE_TC2->TC_CV;
454 lo = AT91C_BASE_TC0->TC_CV;
455 } while(hi != AT91C_BASE_TC2->TC_CV);
456
457 return (hi << 16) | lo;
1c611bbd 458}
7bc95e2e 459
4058a2d7 460
e04475c4 461// -------------------------------------------------------------------------
8ff31e93 462// Timer for bitbanging, or LF stuff when you need a very precis timer
e04475c4 463// 1us = 1.5ticks
464// -------------------------------------------------------------------------
465void StartTicks(void){
8ff31e93 466 // initialization of the timer
e04475c4 467 AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
468 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
8ff31e93
A
469
470 // disable TC0 and TC1 for re-configuration
e04475c4 471 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
8ff31e93
A
472 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
473
474 // first configure TC1 (higher, 0xFFFF0000) 16 bit counter
475 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // just connect to TIOA0 from TC0
476 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // re-enable timer and wait for TC0
477
478 // second configure TC0 (lower, 0x0000FFFF) 16 bit counter
e04475c4 479 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
8ff31e93
A
480 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO |
481 AT91C_TC_ACPA_CLEAR | // RA comperator clears TIOA (carry bit)
482 AT91C_TC_ACPC_SET | // RC comperator sets TIOA (carry bit)
483 AT91C_TC_ASWTRG_SET; // SWTriger sets TIOA (carry bit)
484 AT91C_BASE_TC0->TC_RC = 0; // set TIOA (carry bit) on overflow, return to zero
485 AT91C_BASE_TC0->TC_RA = 1; // clear carry bit on next clock cycle
486 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // reset and re-enable timer
487
488 // synchronized startup procedure
489 while (AT91C_BASE_TC0->TC_CV > 0); // wait until TC0 returned to zero
490 while (AT91C_BASE_TC0->TC_CV < 2); // and has started (TC_CV > TC_RA, now TC1 is cleared)
491
492 // return to zero
493 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
494 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
495 while (AT91C_BASE_TC0->TC_CV > 0);
496}
e04475c4 497
8ff31e93
A
498
499uint32_t GetTicks(void) {
500 uint32_t hi, lo;
501
502 do {
503 hi = AT91C_BASE_TC1->TC_CV;
504 lo = AT91C_BASE_TC0->TC_CV;
505 } while(hi != AT91C_BASE_TC1->TC_CV);
506
507 return (hi << 16) | lo;
e04475c4 508}
509
4058a2d7 510
e04475c4 511// Wait - Spindelay in ticks.
512// if called with a high number, this will trigger the WDT...
513void WaitTicks(uint32_t ticks){
514 if ( ticks == 0 ) return;
8ff31e93
A
515 ticks += GetTicks();
516 while (GetTicks() < ticks);
e04475c4 517}
4058a2d7 518
519
e04475c4 520// Wait / Spindelay in us (microseconds)
521// 1us = 1.5ticks.
522void WaitUS(uint16_t us){
913a54a8 523 WaitTicks( (uint32_t)us * 3 / 2 ) ;
e04475c4 524}
4058a2d7 525
526
e04475c4 527void WaitMS(uint16_t ms){
913a54a8 528 WaitTicks( (uint32_t)ms * 1500 );
e04475c4 529}
4058a2d7 530
531
e04475c4 532// Starts Clock and waits until its reset
533void ResetTicks(void){
e04475c4 534 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
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A
535 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
536 while (AT91C_BASE_TC0->TC_CV > 0);
e04475c4 537}
4058a2d7 538
539
e04475c4 540void ResetTimer(AT91PS_TC timer){
541 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
542 while(timer->TC_CV > 0) ;
543}
4058a2d7 544
545
e04475c4 546// stop clock
547void StopTicks(void){
548 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
549 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
550}
551
4058a2d7 552
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MF
553static uint64_t next_random = 1;
554
555/* Generates a (non-cryptographically secure) 32-bit random number.
556 *
557 * We don't have an implementation of the "rand" function or a clock to seed it
558 * with, so we just call GetTickCount the first time to seed ourselves.
559 */
560uint32_t prand() {
561 if (next_random == 1) {
562 next_random = GetTickCount();
563 }
564
565 next_random = next_random * 6364136223846793005 + 1;
566 return (uint32_t)(next_random >> 32) % 0xffffffff;
567}
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