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1 | //-----------------------------------------------------------------------------\r |
2 | // For reading TI tags, we need to place the FPGA in pass through mode\r |
3 | // and pass everything through to the ARM\r |
4 | //-----------------------------------------------------------------------------\r |
5 | \r |
6 | module lo_passthru(\r |
7 | pck0, ck_1356meg, ck_1356megb,\r |
8 | pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r |
9 | adc_d, adc_clk,\r |
10 | ssp_frame, ssp_din, ssp_dout, ssp_clk,\r |
11 | cross_hi, cross_lo,\r |
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12 | dbg, divisor\r |
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13 | );\r |
14 | input pck0, ck_1356meg, ck_1356megb;\r |
15 | output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r |
16 | input [7:0] adc_d;\r |
17 | output adc_clk;\r |
18 | input ssp_dout;\r |
19 | output ssp_frame, ssp_din, ssp_clk;\r |
20 | input cross_hi, cross_lo;\r |
21 | output dbg;\r |
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22 | input [7:0] divisor;\r |
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23 | \r |
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24 | reg [7:0] pck_divider;\r |
25 | reg ant_lo;\r |
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26 | \r |
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27 | // this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo\r |
28 | // which is high for (divisor+1) pck0 cycles and low for the same duration\r |
29 | // ant_lo is therefore a 50% duty cycle clock signal with a frequency of\r |
30 | // 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk\r |
31 | always @(posedge pck0)\r |
32 | begin\r |
33 | if(pck_divider == divisor[7:0])\r |
34 | begin\r |
35 | pck_divider <= 8'd0;\r |
36 | ant_lo = !ant_lo;\r |
37 | end\r |
38 | else\r |
39 | begin\r |
40 | pck_divider <= pck_divider + 1;\r |
41 | end\r |
42 | end\r |
43 | \r |
44 | // the antenna is modulated when ssp_dout = 1, when 0 the\r |
45 | // antenna drivers stop modulating and go into listen mode\r |
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46 | assign pwr_oe3 = 1'b0;\r |
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47 | assign pwr_oe1 = ssp_dout;\r |
48 | assign pwr_oe2 = ssp_dout;\r |
49 | assign pwr_oe4 = ssp_dout;\r |
50 | assign pwr_lo = ant_lo && ssp_dout;\r |
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51 | assign pwr_hi = 1'b0;\r |
52 | assign adc_clk = 1'b0;\r |
53 | assign ssp_din = cross_lo;\r |
54 | assign dbg = cross_lo;\r |
55 | \r |
56 | endmodule\r |