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1 | `include "lo_read.v"\r |
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2 | /*\r |
3 | pck0 - input main 24Mhz clock (PLL / 4)\r |
4 | [7:0] adc_d - input data from A/D converter\r |
5 | lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)\r |
6 | \r |
7 | pwr_lo - output to coil drivers (ssp_clk / 8)\r |
8 | adc_clk - output A/D clock signal\r |
9 | ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)\r |
10 | ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r |
11 | ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )\r |
12 | \r |
13 | ck_1356meg - input unused\r |
14 | ck_1356megb - input unused\r |
15 | ssp_dout - input unused\r |
16 | cross_hi - input unused\r |
17 | cross_lo - input unused\r |
18 | \r |
19 | pwr_hi - output unused, tied low\r |
20 | pwr_oe1 - output unused, undefined\r |
21 | pwr_oe2 - output unused, undefined\r |
22 | pwr_oe3 - output unused, undefined\r |
23 | pwr_oe4 - output unused, undefined\r |
24 | dbg - output alias for adc_clk\r |
25 | */\r |
26 | \r |
27 | module testbed_lo_read;\r |
28 | reg pck0;\r |
29 | reg [7:0] adc_d;\r |
30 | reg lo_is_125khz;\r |
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31 | reg [15:0] divisor;\r |
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32 | \r |
33 | wire pwr_lo;\r |
34 | wire adc_clk;\r |
35 | wire ck_1356meg;\r |
36 | wire ck_1356megb;\r |
37 | wire ssp_frame;\r |
38 | wire ssp_din;\r |
39 | wire ssp_clk;\r |
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40 | reg ssp_dout;\r |
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41 | wire pwr_hi;\r |
42 | wire pwr_oe1;\r |
43 | wire pwr_oe2;\r |
44 | wire pwr_oe3;\r |
45 | wire pwr_oe4;\r |
46 | wire cross_lo;\r |
47 | wire cross_hi;\r |
48 | wire dbg;\r |
49 | \r |
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50 | lo_read #(5,10) dut(\r |
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51 | .pck0(pck0),\r |
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52 | .ck_1356meg(ck_1356meg),\r |
53 | .ck_1356megb(ck_1356megb),\r |
54 | .pwr_lo(pwr_lo),\r |
55 | .pwr_hi(pwr_hi),\r |
56 | .pwr_oe1(pwr_oe1),\r |
57 | .pwr_oe2(pwr_oe2),\r |
58 | .pwr_oe3(pwr_oe3),\r |
59 | .pwr_oe4(pwr_oe4),\r |
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60 | .adc_d(adc_d),\r |
61 | .adc_clk(adc_clk),\r |
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62 | .ssp_frame(ssp_frame),\r |
63 | .ssp_din(ssp_din),\r |
64 | .ssp_dout(ssp_dout),\r |
65 | .ssp_clk(ssp_clk),\r |
66 | .cross_hi(cross_hi),\r |
67 | .cross_lo(cross_lo),\r |
68 | .dbg(dbg),\r |
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69 | .lo_is_125khz(lo_is_125khz),\r |
70 | .divisor(divisor)\r |
71 | );\r |
72 | \r |
73 | integer idx, i, adc_val=8;\r |
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74 | \r |
75 | // main clock\r |
76 | always #5 pck0 = !pck0;\r |
77 | \r |
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78 | task crank_dut;\r |
79 | begin\r |
80 | @(posedge adc_clk) ;\r |
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81 | adc_d = adc_val;\r |
82 | adc_val = (adc_val *2) + 53;\r |
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83 | end\r |
84 | endtask\r |
85 | \r |
86 | initial begin\r |
87 | \r |
88 | // init inputs\r |
89 | pck0 = 0;\r |
90 | adc_d = 0;\r |
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91 | ssp_dout = 0;\r |
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92 | lo_is_125khz = 1;\r |
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93 | divisor = 255; //min 16, 95=125Khz, max 255\r |
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94 | \r |
95 | // simulate 4 A/D cycles at 125Khz\r |
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96 | for (i = 0 ; i < 8 ; i = i + 1) begin\r |
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97 | crank_dut;\r |
98 | end\r |
99 | $finish;\r |
100 | end\r |
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101 | endmodule // main\r |