]> git.zerfleddert.de Git - proxmark3-svn/blame - fpga/sim.tcl
CHG: moved to header file
[proxmark3-svn] / fpga / sim.tcl
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ba06a4b6 1#------------------------------------------------------------------------------
2# Run the simulation testbench in ModelSim: recompile both Verilog source
3# files, then start the simulation, add a lot of signals to the waveform
4# viewer, and run. I should (TODO) fix the absolute paths at some point.
5#
6# Jonathan Westhues, Mar 2006
7#------------------------------------------------------------------------------
8
9vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v
10vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v
11
12vsim work.fpga_tb
13
14add wave sim:/fpga_tb/adc_clk
15add wave sim:/fpga_tb/adc_d
16add wave sim:/fpga_tb/pwr_lo
17add wave sim:/fpga_tb/ssp_clk
18add wave sim:/fpga_tb/ssp_frame
19add wave sim:/fpga_tb/ssp_din
20add wave sim:/fpga_tb/ssp_dout
21
22add wave sim:/fpga_tb/dut/clk_lo
23add wave sim:/fpga_tb/dut/pck_divider
24add wave sim:/fpga_tb/dut/carrier_divider_lo
25add wave sim:/fpga_tb/dut/conf_word
26
27run 30000
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