6658905f |
1 | #------------------------------------------------------------------------------\r |
2 | # Run the simulation testbench in ModelSim: recompile both Verilog source\r |
3 | # files, then start the simulation, add a lot of signals to the waveform\r |
4 | # viewer, and run. I should (TODO) fix the absolute paths at some point.\r |
5 | #\r |
6 | # Jonathan Westhues, Mar 2006\r |
7 | #------------------------------------------------------------------------------\r |
8 | \r |
9 | vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v\r |
10 | vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v\r |
11 | \r |
12 | vsim work.fpga_tb\r |
13 | \r |
14 | add wave sim:/fpga_tb/adc_clk\r |
15 | add wave sim:/fpga_tb/adc_d\r |
16 | add wave sim:/fpga_tb/pwr_lo\r |
17 | add wave sim:/fpga_tb/ssp_clk\r |
18 | add wave sim:/fpga_tb/ssp_frame\r |
19 | add wave sim:/fpga_tb/ssp_din\r |
20 | add wave sim:/fpga_tb/ssp_dout\r |
21 | \r |
22 | add wave sim:/fpga_tb/dut/clk_lo\r |
23 | add wave sim:/fpga_tb/dut/pck_divider\r |
24 | add wave sim:/fpga_tb/dut/carrier_divider_lo\r |
25 | add wave sim:/fpga_tb/dut/conf_word\r |
26 | \r |
27 | run 30000\r |