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1 | //----------------------------------------------------------------------------- |
2 | // Copyright (C) 2014 iZsh <izsh at fail0verflow.com> |
3 | // |
4 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, |
5 | // at your option, any later version. See the LICENSE.txt file for the text of |
6 | // the license. |
7 | //----------------------------------------------------------------------------- |
8 | module clk_divider(input clk, input [7:0] divisor, output [7:0] div_cnt, output div_clk); |
9 | |
10 | reg [7:0] div_cnt_ = 0; |
11 | reg div_clk_; |
12 | assign div_cnt = div_cnt_; |
13 | assign div_clk = div_clk_; |
14 | |
15 | always @(posedge clk) |
16 | begin |
17 | if(div_cnt == divisor) begin |
18 | div_cnt_ <= 8'd0; |
19 | div_clk_ = !div_clk_; |
20 | end else |
21 | div_cnt_ <= div_cnt_ + 1; |
22 | end |
23 | |
24 | endmodule |
25 | |