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Merge pull request #351 from Fl0-0/CmdEM410xBrute_mingw_fix
[proxmark3-svn] / fpga / hi_sniffer.v
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0472d76d 1module hi_sniffer(
2 pck0, ck_1356meg, ck_1356megb,
3 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
4 adc_d, adc_clk,
5 ssp_frame, ssp_din, ssp_dout, ssp_clk,
6 cross_hi, cross_lo,
7 dbg,
8 xcorr_is_848, snoop, xcorr_quarter_freq // not used.
9);
10 input pck0, ck_1356meg, ck_1356megb;
11 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
12 input [7:0] adc_d;
13 output adc_clk;
14 input ssp_dout;
15 output ssp_frame, ssp_din, ssp_clk;
16 input cross_hi, cross_lo;
17 output dbg;
18 input xcorr_is_848, snoop, xcorr_quarter_freq; // not used.
19
20// We are only snooping, all off.
82d58934 21assign pwr_hi = 1'b0;
22assign pwr_lo = 1'b0;
0472d76d 23assign pwr_oe1 = 1'b0;
24assign pwr_oe2 = 1'b0;
25assign pwr_oe3 = 1'b0;
26assign pwr_oe4 = 1'b0;
27
0472d76d 28reg ssp_frame;
0472d76d 29reg [7:0] adc_d_out = 8'd0;
82d58934 30reg [2:0] ssp_cnt = 3'd0;
0472d76d 31
82d58934 32assign adc_clk = ck_1356meg;
33assign ssp_clk = ~ck_1356meg;
0472d76d 34
82d58934 35always @(posedge ssp_clk)
0472d76d 36begin
82d58934 37 if(ssp_cnt[2:0] == 3'd7)
38 ssp_cnt[2:0] <= 3'd0;
39 else
40 ssp_cnt <= ssp_cnt + 1;
0472d76d 41
82d58934 42 if(ssp_cnt[2:0] == 3'b000) // set frame length
0472d76d 43 begin
82d58934 44 adc_d_out[7:0] <= adc_d;
45 ssp_frame <= 1'b1;
0472d76d 46 end
82d58934 47 else
0472d76d 48 begin
82d58934 49 adc_d_out[7:0] <= {1'b0, adc_d_out[7:1]};
50 ssp_frame <= 1'b0;
0472d76d 51 end
0472d76d 52
82d58934 53end
0472d76d 54
82d58934 55assign ssp_din = adc_d_out[0];
0472d76d 56
57endmodule
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