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add4d470 | 1 | //----------------------------------------------------------------------------- |
2 | // Jonathan Westhues, April 2006 | |
3 | // iZsh <izsh at fail0verflow.com>, 2014 | |
4 | // | |
5 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, | |
6 | // at your option, any later version. See the LICENSE.txt file for the text of | |
7 | // the license. | |
8 | //----------------------------------------------------------------------------- | |
9 | // Routines to load the FPGA image, and then to configure the FPGA's major | |
10 | // mode once it is configured. | |
11 | //----------------------------------------------------------------------------- | |
12 | ||
13 | void FpgaSendCommand(uint16_t cmd, uint16_t v); | |
14 | void FpgaWriteConfWord(uint8_t v); | |
15 | void FpgaDownloadAndGo(int bitstream_version); | |
16 | void FpgaGatherVersion(int bitstream_version, char *dst, int len); | |
17 | void FpgaSetupSsc(void); | |
18 | void SetupSpi(int mode); | |
19 | bool FpgaSetupSscDma(uint8_t *buf, int len); | |
e2012d1b | 20 | void Fpga_print_status(); |
fdcfbdcc | 21 | int FpgaGetCurrent(); |
add4d470 | 22 | #define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; |
23 | #define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; | |
24 | void SetAdcMuxFor(uint32_t whichGpio); | |
25 | ||
fb228974 | 26 | // definitions for multiple FPGA config files support |
27 | #define FPGA_BITSTREAM_MAX 2 // the total number of FPGA bitstreams (configs) | |
28 | #define FPGA_BITSTREAM_ERR 0 | |
29 | #define FPGA_BITSTREAM_LF 1 | |
30 | #define FPGA_BITSTREAM_HF 2 | |
31 | ||
32 | ||
add4d470 | 33 | // Definitions for the FPGA commands. |
34 | #define FPGA_CMD_SET_CONFREG (1<<12) | |
35 | #define FPGA_CMD_SET_DIVISOR (2<<12) | |
36 | #define FPGA_CMD_SET_USER_BYTE1 (3<<12) | |
37 | // Definitions for the FPGA configuration word. | |
38 | // LF | |
39 | #define FPGA_MAJOR_MODE_LF_ADC (0<<5) | |
40 | #define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<5) | |
41 | #define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<5) | |
42 | // HF | |
43 | #define FPGA_MAJOR_MODE_HF_READER_TX (0<<5) | |
44 | #define FPGA_MAJOR_MODE_HF_READER_RX_XCORR (1<<5) | |
45 | #define FPGA_MAJOR_MODE_HF_SIMULATOR (2<<5) | |
46 | #define FPGA_MAJOR_MODE_HF_ISO14443A (3<<5) | |
0472d76d | 47 | #define FPGA_MAJOR_MODE_HF_SNOOP (4<<5) |
add4d470 | 48 | // BOTH |
49 | #define FPGA_MAJOR_MODE_OFF (7<<5) | |
50 | // Options for LF_ADC | |
51 | #define FPGA_LF_ADC_READER_FIELD (1<<0) | |
52 | // Options for LF_EDGE_DETECT | |
53 | #define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD FPGA_CMD_SET_USER_BYTE1 | |
54 | #define FPGA_LF_EDGE_DETECT_READER_FIELD (1<<0) | |
55 | #define FPGA_LF_EDGE_DETECT_TOGGLE_MODE (1<<1) | |
56 | // Options for the HF reader, tx to tag | |
57 | #define FPGA_HF_READER_TX_SHALLOW_MOD (1<<0) | |
58 | // Options for the HF reader, correlating against rx from tag | |
59 | #define FPGA_HF_READER_RX_XCORR_848_KHZ (1<<0) | |
60 | #define FPGA_HF_READER_RX_XCORR_SNOOP (1<<1) | |
3f7aaf24 | 61 | #define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ (1<<2) |
add4d470 | 62 | // Options for the HF simulated tag, how to modulate |
63 | #define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0) | |
64 | #define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0) | |
65 | #define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0) | |
66 | #define FPGA_HF_SIMULATOR_MODULATE_424K (4<<0) | |
67 | #define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5//101 | |
68 | ||
69 | // Options for ISO14443A | |
70 | #define FPGA_HF_ISO14443A_SNIFFER (0<<0) | |
71 | #define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0) | |
72 | #define FPGA_HF_ISO14443A_TAGSIM_MOD (2<<0) | |
73 | #define FPGA_HF_ISO14443A_READER_LISTEN (3<<0) | |
74 | #define FPGA_HF_ISO14443A_READER_MOD (4<<0) |