| 6658905f |
1 | `include "hi_simulate.v"\r |
| 2 | \r |
| 3 | /*\r |
| 4 | pck0 - input main 24Mhz clock (PLL / 4)\r |
| 5 | [7:0] adc_d - input data from A/D converter\r |
| 6 | mod_type - modulation type\r |
| 7 | \r |
| 8 | pwr_lo - output to coil drivers (ssp_clk / 8)\r |
| 9 | adc_clk - output A/D clock signal\r |
| 10 | ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)\r |
| 11 | ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r |
| 12 | ssp_clk - output SSP clock signal\r |
| 13 | \r |
| 14 | ck_1356meg - input unused\r |
| 15 | ck_1356megb - input unused\r |
| 16 | ssp_dout - input unused\r |
| 17 | cross_hi - input unused\r |
| 18 | cross_lo - input unused\r |
| 19 | \r |
| 20 | pwr_hi - output unused, tied low\r |
| 21 | pwr_oe1 - output unused, undefined\r |
| 22 | pwr_oe2 - output unused, undefined\r |
| 23 | pwr_oe3 - output unused, undefined\r |
| 24 | pwr_oe4 - output unused, undefined\r |
| 25 | dbg - output alias for adc_clk\r |
| 26 | */\r |
| 27 | \r |
| 28 | module testbed_hi_simulate;\r |
| 29 | reg pck0;\r |
| 30 | reg [7:0] adc_d;\r |
| 31 | reg mod_type;\r |
| 32 | \r |
| 33 | wire pwr_lo;\r |
| 34 | wire adc_clk;\r |
| 35 | reg ck_1356meg;\r |
| 36 | reg ck_1356megb;\r |
| 37 | wire ssp_frame;\r |
| 38 | wire ssp_din;\r |
| 39 | wire ssp_clk;\r |
| 40 | reg ssp_dout;\r |
| 41 | wire pwr_hi;\r |
| 42 | wire pwr_oe1;\r |
| 43 | wire pwr_oe2;\r |
| 44 | wire pwr_oe3;\r |
| 45 | wire pwr_oe4;\r |
| 46 | wire cross_lo;\r |
| 47 | wire cross_hi;\r |
| 48 | wire dbg;\r |
| 49 | \r |
| 50 | hi_simulate #(5,200) dut(\r |
| 51 | .pck0(pck0),\r |
| 52 | .ck_1356meg(ck_1356meg),\r |
| 53 | .ck_1356megb(ck_1356megb),\r |
| 54 | .pwr_lo(pwr_lo),\r |
| 55 | .pwr_hi(pwr_hi),\r |
| 56 | .pwr_oe1(pwr_oe1),\r |
| 57 | .pwr_oe2(pwr_oe2),\r |
| 58 | .pwr_oe3(pwr_oe3),\r |
| 59 | .pwr_oe4(pwr_oe4),\r |
| 60 | .adc_d(adc_d),\r |
| 61 | .adc_clk(adc_clk),\r |
| 62 | .ssp_frame(ssp_frame),\r |
| 63 | .ssp_din(ssp_din),\r |
| 64 | .ssp_dout(ssp_dout),\r |
| 65 | .ssp_clk(ssp_clk),\r |
| 66 | .cross_hi(cross_hi),\r |
| 67 | .cross_lo(cross_lo),\r |
| 68 | .dbg(dbg),\r |
| 69 | .mod_type(mod_type)\r |
| 70 | );\r |
| 71 | \r |
| 72 | integer idx, i;\r |
| 73 | \r |
| 74 | // main clock\r |
| 75 | always #5 begin \r |
| 76 | ck_1356megb = !ck_1356megb;\r |
| 77 | ck_1356meg = ck_1356megb;\r |
| 78 | end\r |
| 79 | \r |
| 80 | always begin \r |
| 81 | @(negedge adc_clk) ;\r |
| 82 | adc_d = $random;\r |
| 83 | end\r |
| 84 | \r |
| 85 | //crank DUT\r |
| 86 | task crank_dut;\r |
| 87 | begin\r |
| 88 | @(negedge ssp_clk) ;\r |
| 89 | ssp_dout = $random;\r |
| 90 | end\r |
| 91 | endtask\r |
| 92 | \r |
| 93 | initial begin\r |
| 94 | \r |
| 95 | // init inputs\r |
| 96 | ck_1356megb = 0;\r |
| 97 | // random values\r |
| 98 | adc_d = 0;\r |
| 99 | ssp_dout=1;\r |
| 100 | \r |
| 101 | // shallow modulation off\r |
| 102 | mod_type=0;\r |
| 103 | for (i = 0 ; i < 16 ; i = i + 1) begin\r |
| 104 | crank_dut;\r |
| 105 | end\r |
| 106 | \r |
| 107 | // shallow modulation on\r |
| 108 | mod_type=1;\r |
| 109 | for (i = 0 ; i < 16 ; i = i + 1) begin\r |
| 110 | crank_dut;\r |
| 111 | end\r |
| 112 | $finish;\r |
| 113 | end\r |
| 114 | \r |
| 115 | endmodule // main\r |
| 116 | \r |
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