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Commit | Line | Data |
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ba06a4b6 | 1 | `include "hi_simulate.v" |
2 | ||
3 | /* | |
4 | pck0 - input main 24Mhz clock (PLL / 4) | |
5 | [7:0] adc_d - input data from A/D converter | |
6 | mod_type - modulation type | |
7 | ||
8 | pwr_lo - output to coil drivers (ssp_clk / 8) | |
9 | adc_clk - output A/D clock signal | |
10 | ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted) | |
11 | ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first) | |
12 | ssp_clk - output SSP clock signal | |
13 | ||
14 | ck_1356meg - input unused | |
15 | ck_1356megb - input unused | |
16 | ssp_dout - input unused | |
17 | cross_hi - input unused | |
18 | cross_lo - input unused | |
19 | ||
20 | pwr_hi - output unused, tied low | |
21 | pwr_oe1 - output unused, undefined | |
22 | pwr_oe2 - output unused, undefined | |
23 | pwr_oe3 - output unused, undefined | |
24 | pwr_oe4 - output unused, undefined | |
25 | dbg - output alias for adc_clk | |
26 | */ | |
27 | ||
28 | module testbed_hi_simulate; | |
29 | reg pck0; | |
30 | reg [7:0] adc_d; | |
31 | reg mod_type; | |
32 | ||
33 | wire pwr_lo; | |
34 | wire adc_clk; | |
35 | reg ck_1356meg; | |
36 | reg ck_1356megb; | |
37 | wire ssp_frame; | |
38 | wire ssp_din; | |
39 | wire ssp_clk; | |
40 | reg ssp_dout; | |
41 | wire pwr_hi; | |
42 | wire pwr_oe1; | |
43 | wire pwr_oe2; | |
44 | wire pwr_oe3; | |
45 | wire pwr_oe4; | |
46 | wire cross_lo; | |
47 | wire cross_hi; | |
48 | wire dbg; | |
49 | ||
50 | hi_simulate #(5,200) dut( | |
51 | .pck0(pck0), | |
52 | .ck_1356meg(ck_1356meg), | |
53 | .ck_1356megb(ck_1356megb), | |
54 | .pwr_lo(pwr_lo), | |
55 | .pwr_hi(pwr_hi), | |
56 | .pwr_oe1(pwr_oe1), | |
57 | .pwr_oe2(pwr_oe2), | |
58 | .pwr_oe3(pwr_oe3), | |
59 | .pwr_oe4(pwr_oe4), | |
60 | .adc_d(adc_d), | |
61 | .adc_clk(adc_clk), | |
62 | .ssp_frame(ssp_frame), | |
63 | .ssp_din(ssp_din), | |
64 | .ssp_dout(ssp_dout), | |
65 | .ssp_clk(ssp_clk), | |
66 | .cross_hi(cross_hi), | |
67 | .cross_lo(cross_lo), | |
68 | .dbg(dbg), | |
69 | .mod_type(mod_type) | |
70 | ); | |
71 | ||
72 | integer idx, i; | |
73 | ||
74 | // main clock | |
75 | always #5 begin | |
76 | ck_1356megb = !ck_1356megb; | |
77 | ck_1356meg = ck_1356megb; | |
78 | end | |
79 | ||
80 | always begin | |
81 | @(negedge adc_clk) ; | |
82 | adc_d = $random; | |
83 | end | |
84 | ||
85 | //crank DUT | |
86 | task crank_dut; | |
87 | begin | |
88 | @(negedge ssp_clk) ; | |
89 | ssp_dout = $random; | |
90 | end | |
91 | endtask | |
92 | ||
93 | initial begin | |
94 | ||
95 | // init inputs | |
96 | ck_1356megb = 0; | |
97 | // random values | |
98 | adc_d = 0; | |
99 | ssp_dout=1; | |
100 | ||
101 | // shallow modulation off | |
102 | mod_type=0; | |
103 | for (i = 0 ; i < 16 ; i = i + 1) begin | |
104 | crank_dut; | |
105 | end | |
106 | ||
107 | // shallow modulation on | |
108 | mod_type=1; | |
109 | for (i = 0 ; i < 16 ; i = i + 1) begin | |
110 | crank_dut; | |
111 | end | |
112 | $finish; | |
113 | end | |
114 | ||
115 | endmodule // main | |
116 |