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ba06a4b6 | 1 | //----------------------------------------------------------------------------- |
2 | // | |
3 | // Jonathan Westhues, April 2006 | |
4 | //----------------------------------------------------------------------------- | |
5 | ||
6 | module hi_read_rx_xcorr( | |
7 | pck0, ck_1356meg, ck_1356megb, | |
8 | pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4, | |
9 | adc_d, adc_clk, | |
10 | ssp_frame, ssp_din, ssp_dout, ssp_clk, | |
11 | cross_hi, cross_lo, | |
12 | dbg, | |
da586b17 | 13 | xcorr_is_848, snoop |
ba06a4b6 | 14 | ); |
15 | input pck0, ck_1356meg, ck_1356megb; | |
16 | output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4; | |
17 | input [7:0] adc_d; | |
18 | output adc_clk; | |
19 | input ssp_dout; | |
20 | output ssp_frame, ssp_din, ssp_clk; | |
21 | input cross_hi, cross_lo; | |
22 | output dbg; | |
da586b17 | 23 | input xcorr_is_848, snoop; |
ba06a4b6 | 24 | |
25 | // Carrier is steady on through this, unless we're snooping. | |
26 | assign pwr_hi = ck_1356megb & (~snoop); | |
27 | assign pwr_oe1 = 1'b0; | |
ba06a4b6 | 28 | assign pwr_oe3 = 1'b0; |
29 | assign pwr_oe4 = 1'b0; | |
30 | ||
b535053a | 31 | // Clock divider |
32 | reg [0:0] fc_divider; | |
da586b17 | 33 | always @(negedge ck_1356megb) |
b535053a | 34 | fc_divider <= fc_divider + 1; |
35 | wire fc_div2 = fc_divider[0]; | |
36 | ||
37 | reg adc_clk; | |
38 | always @(ck_1356megb) | |
39 | if (xcorr_is_848) | |
40 | adc_clk <= ck_1356megb; | |
41 | else | |
42 | adc_clk <= fc_div2; | |
ba06a4b6 | 43 | |
44 | // When we're a reader, we just need to do the BPSK demod; but when we're an | |
45 | // eavesdropper, we also need to pick out the commands sent by the reader, | |
46 | // using AM. Do this the same way that we do it for the simulated tag. | |
51d4f6f1 | 47 | reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev; |
ba06a4b6 | 48 | reg [11:0] has_been_low_for; |
49 | always @(negedge adc_clk) | |
50 | begin | |
51 | if(& adc_d[7:0]) after_hysteresis <= 1'b1; | |
52 | else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0; | |
53 | ||
54 | if(after_hysteresis) | |
55 | begin | |
56 | has_been_low_for <= 7'b0; | |
57 | end | |
58 | else | |
59 | begin | |
60 | if(has_been_low_for == 12'd4095) | |
61 | begin | |
62 | has_been_low_for <= 12'd0; | |
63 | after_hysteresis <= 1'b1; | |
64 | end | |
65 | else | |
66 | has_been_low_for <= has_been_low_for + 1; | |
67 | end | |
68 | end | |
69 | ||
70 | // Let us report a correlation every 4 subcarrier cycles, or 4*16 samples, | |
71 | // so we need a 6-bit counter. | |
72 | reg [5:0] corr_i_cnt; | |
ba06a4b6 | 73 | // And a couple of registers in which to accumulate the correlations. |
5b95953d | 74 | // we would add at most 32 times adc_d, the result can be held in 13 bits. |
75 | // Need one additional bit because it can be negative as well | |
76 | reg signed [13:0] corr_i_accum; | |
77 | reg signed [13:0] corr_q_accum; | |
ba06a4b6 | 78 | reg signed [7:0] corr_i_out; |
79 | reg signed [7:0] corr_q_out; | |
51d4f6f1 | 80 | // clock and frame signal for communication to ARM |
81 | reg ssp_clk; | |
82 | reg ssp_frame; | |
83 | ||
84 | ||
46734099 | 85 | always @(negedge adc_clk) |
86 | begin | |
46734099 | 87 | corr_i_cnt <= corr_i_cnt + 1; |
88 | end | |
89 | ||
ba06a4b6 | 90 | |
91 | // ADC data appears on the rising edge, so sample it on the falling edge | |
92 | always @(negedge adc_clk) | |
93 | begin | |
94 | // These are the correlators: we correlate against in-phase and quadrature | |
95 | // versions of our reference signal, and keep the (signed) result to | |
96 | // send out later over the SSP. | |
705bfa10 | 97 | if(corr_i_cnt == 6'd0) |
ba06a4b6 | 98 | begin |
99 | if(snoop) | |
100 | begin | |
46734099 | 101 | // Send only 7 most significant bits of tag signal (signed), LSB is reader signal: |
51d4f6f1 | 102 | corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev}; |
103 | corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev}; | |
104 | after_hysteresis_prev_prev <= after_hysteresis; | |
ba06a4b6 | 105 | end |
106 | else | |
107 | begin | |
51d4f6f1 | 108 | // 8 most significant bits of tag signal |
ba06a4b6 | 109 | corr_i_out <= corr_i_accum[13:6]; |
110 | corr_q_out <= corr_q_accum[13:6]; | |
111 | end | |
112 | ||
113 | corr_i_accum <= adc_d; | |
114 | corr_q_accum <= adc_d; | |
ba06a4b6 | 115 | end |
116 | else | |
117 | begin | |
118 | if(corr_i_cnt[3]) | |
119 | corr_i_accum <= corr_i_accum - adc_d; | |
120 | else | |
121 | corr_i_accum <= corr_i_accum + adc_d; | |
122 | ||
51d4f6f1 | 123 | if(corr_i_cnt[3] == corr_i_cnt[2]) // phase shifted by pi/2 |
ba06a4b6 | 124 | corr_q_accum <= corr_q_accum + adc_d; |
51d4f6f1 | 125 | else |
126 | corr_q_accum <= corr_q_accum - adc_d; | |
ba06a4b6 | 127 | |
ba06a4b6 | 128 | end |
129 | ||
130 | // The logic in hi_simulate.v reports 4 samples per bit. We report two | |
131 | // (I, Q) pairs per bit, so we should do 2 samples per pair. | |
705bfa10 | 132 | if(corr_i_cnt == 6'd32) |
ba06a4b6 | 133 | after_hysteresis_prev <= after_hysteresis; |
134 | ||
135 | // Then the result from last time is serialized and send out to the ARM. | |
136 | // We get one report each cycle, and each report is 16 bits, so the | |
137 | // ssp_clk should be the adc_clk divided by 64/16 = 4. | |
138 | ||
139 | if(corr_i_cnt[1:0] == 2'b10) | |
140 | ssp_clk <= 1'b0; | |
141 | ||
142 | if(corr_i_cnt[1:0] == 2'b00) | |
143 | begin | |
144 | ssp_clk <= 1'b1; | |
145 | // Don't shift if we just loaded new data, obviously. | |
b535053a | 146 | if(corr_i_cnt != 6'd0) |
ba06a4b6 | 147 | begin |
148 | corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]}; | |
149 | corr_q_out[7:1] <= corr_q_out[6:0]; | |
150 | end | |
151 | end | |
152 | ||
09c66f1f | 153 | // set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35 |
51d4f6f1 | 154 | // (send two frames with 8 Bits each) |
09c66f1f | 155 | if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000) |
ba06a4b6 | 156 | ssp_frame = 1'b1; |
157 | else | |
158 | ssp_frame = 1'b0; | |
159 | ||
160 | end | |
161 | ||
162 | assign ssp_din = corr_i_out[7]; | |
163 | ||
164 | assign dbg = corr_i_cnt[3]; | |
165 | ||
166 | // Unused. | |
167 | assign pwr_lo = 1'b0; | |
51d4f6f1 | 168 | assign pwr_oe2 = 1'b0; |
ba06a4b6 | 169 | |
170 | endmodule |