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6658905f 1//-----------------------------------------------------------------------------\r
2// The FPGA is responsible for interfacing between the A/D, the coil drivers,\r
3// and the ARM. In the low-frequency modes it passes the data straight\r
4// through, so that the ARM gets raw A/D samples over the SSP. In the high-\r
5// frequency modes, the FPGA might perform some demodulation first, to\r
6// reduce the amount of data that we must send to the ARM.\r
7//\r
8// I am not really an FPGA/ASIC designer, so I am sure that a lot of this\r
9// could be improved.\r
10//\r
11// Jonathan Westhues, March 2006\r
12// Added ISO14443-A support by Gerhard de Koning Gans, April 2008\r
13//-----------------------------------------------------------------------------\r
14\r
15`include "lo_read.v"\r
72acba78 16`include "lo_passthru.v"\r
6658905f 17`include "lo_simulate.v"\r
18`include "hi_read_tx.v"\r
19`include "hi_read_rx_xcorr.v"\r
20`include "hi_simulate.v"\r
21`include "hi_iso14443a.v"\r
22`include "util.v"\r
23\r
24module fpga(\r
30f2a7d3 25 spcki, miso, mosi, ncs,\r
6658905f 26 pck0i, ck_1356meg, ck_1356megb,\r
27 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
28 adc_d, adc_clk, adc_noe,\r
29 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
30 cross_hi, cross_lo,\r
31 dbg\r
32);\r
30f2a7d3 33 input spcki, mosi, ncs;\r
6658905f 34 output miso;\r
35 input pck0i, ck_1356meg, ck_1356megb;\r
36 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
37 input [7:0] adc_d;\r
38 output adc_clk, adc_noe;\r
39 input ssp_dout;\r
40 output ssp_frame, ssp_din, ssp_clk;\r
41 input cross_hi, cross_lo;\r
42 output dbg;\r
43\r
30f2a7d3 44//assign pck0 = pck0i;\r
6658905f 45 IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(\r
46 .O(pck0),\r
47 .I(pck0i)\r
48 );\r
30f2a7d3 49//assign spck = spcki;\r
50 IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(\r
51 .O(spck),\r
52 .I(spcki)\r
53 );\r
6658905f 54//-----------------------------------------------------------------------------\r
55// The SPI receiver. This sets up the configuration word, which the rest of\r
56// the logic looks at to determine how to connect the A/D and the coil\r
57// drivers (i.e., which section gets it). Also assign some symbolic names\r
58// to the configuration bits, for use below.\r
59//-----------------------------------------------------------------------------\r
60\r
30f2a7d3 61reg [15:0] shift_reg;\r
62reg [7:0] divisor;\r
6658905f 63reg [7:0] conf_word;\r
64\r
65// We switch modes between transmitting to the 13.56 MHz tag and receiving\r
66// from it, which means that we must make sure that we can do so without\r
67// glitching, or else we will glitch the transmitted carrier.\r
68always @(posedge ncs)\r
69begin\r
30f2a7d3 70 case(shift_reg[15:12])\r
71 4'b0001: conf_word <= shift_reg[7:0];\r
72 4'b0010: divisor <= shift_reg[7:0];\r
73 endcase\r
6658905f 74end\r
75\r
76always @(posedge spck)\r
77begin\r
78 if(~ncs)\r
79 begin\r
30f2a7d3 80 shift_reg[15:1] <= shift_reg[14:0];\r
81 shift_reg[0] <= mosi;\r
6658905f 82 end\r
83end\r
84\r
85wire [2:0] major_mode;\r
86assign major_mode = conf_word[7:5];\r
87\r
88// For the low-frequency configuration:\r
89wire lo_is_125khz;\r
90assign lo_is_125khz = conf_word[3];\r
91\r
92// For the high-frequency transmit configuration: modulation depth, either\r
93// 100% (just quite driving antenna, steady LOW), or shallower (tri-state\r
94// some fraction of the buffers)\r
95wire hi_read_tx_shallow_modulation;\r
96assign hi_read_tx_shallow_modulation = conf_word[0];\r
97\r
98// For the high-frequency receive correlator: frequency against which to\r
99// correlate.\r
100wire hi_read_rx_xcorr_848;\r
101assign hi_read_rx_xcorr_848 = conf_word[0];\r
102// and whether to drive the coil (reader) or just short it (snooper)\r
103wire hi_read_rx_xcorr_snoop;\r
104assign hi_read_rx_xcorr_snoop = conf_word[1];\r
105\r
8d40aba5 106// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4\r
107wire hi_read_rx_xcorr_quarter;\r
108assign hi_read_rx_xcorr_quarter = conf_word[2];\r
109\r
6658905f 110// For the high-frequency simulated tag: what kind of modulation to use.\r
111wire [2:0] hi_simulate_mod_type;\r
112assign hi_simulate_mod_type = conf_word[2:0];\r
113\r
114//-----------------------------------------------------------------------------\r
115// And then we instantiate the modules corresponding to each of the FPGA's\r
116// major modes, and use muxes to connect the outputs of the active mode to\r
117// the output pins.\r
118//-----------------------------------------------------------------------------\r
119\r
120lo_read lr(\r
121 pck0, ck_1356meg, ck_1356megb,\r
122 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,\r
123 adc_d, lr_adc_clk,\r
124 lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,\r
125 cross_hi, cross_lo,\r
126 lr_dbg,\r
30f2a7d3 127 lo_is_125khz, divisor\r
6658905f 128);\r
129\r
72acba78 130lo_passthru lp(\r
131 pck0, ck_1356meg, ck_1356megb,\r
132 lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,\r
133 adc_d, lp_adc_clk,\r
134 lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,\r
135 cross_hi, cross_lo,\r
8e7a6ce4 136 lp_dbg, divisor\r
72acba78 137);\r
138\r
6658905f 139lo_simulate ls(\r
140 pck0, ck_1356meg, ck_1356megb,\r
141 ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,\r
142 adc_d, ls_adc_clk,\r
143 ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,\r
144 cross_hi, cross_lo,\r
802a3616 145 ls_dbg, divisor\r
6658905f 146);\r
147\r
148hi_read_tx ht(\r
149 pck0, ck_1356meg, ck_1356megb,\r
150 ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,\r
151 adc_d, ht_adc_clk,\r
152 ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,\r
153 cross_hi, cross_lo,\r
154 ht_dbg,\r
155 hi_read_tx_shallow_modulation\r
156);\r
157\r
158hi_read_rx_xcorr hrxc(\r
159 pck0, ck_1356meg, ck_1356megb,\r
160 hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,\r
161 adc_d, hrxc_adc_clk,\r
162 hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,\r
163 cross_hi, cross_lo,\r
164 hrxc_dbg,\r
8d40aba5 165 hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter\r
6658905f 166);\r
167\r
168hi_simulate hs(\r
169 pck0, ck_1356meg, ck_1356megb,\r
170 hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,\r
171 adc_d, hs_adc_clk,\r
172 hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,\r
173 cross_hi, cross_lo,\r
174 hs_dbg,\r
175 hi_simulate_mod_type\r
176);\r
177\r
178hi_iso14443a hisn(\r
179 pck0, ck_1356meg, ck_1356megb,\r
180 hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,\r
181 adc_d, hisn_adc_clk,\r
182 hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,\r
183 cross_hi, cross_lo,\r
184 hisn_dbg,\r
185 hi_simulate_mod_type\r
186);\r
187\r
188// Major modes:\r
189// 000 -- LF reader (generic)\r
190// 001 -- LF simulated tag (generic)\r
191// 010 -- HF reader, transmitting to tag; modulation depth selectable\r
192// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable\r
193// 100 -- HF simulated tag\r
194// 101 -- HF ISO14443-A\r
72acba78 195// 110 -- LF passthrough\r
6658905f 196// 111 -- everything off\r
197\r
72acba78 198mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);\r
199mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);\r
200mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);\r
201mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);\r
202mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);\r
203mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);\r
204mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);\r
205mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);\r
206mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);\r
207mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);\r
208mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);\r
6658905f 209\r
210// In all modes, let the ADC's outputs be enabled.\r
211assign adc_noe = 1'b0;\r
212\r
213endmodule\r
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