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6658905f 1//-----------------------------------------------------------------------------\r
2// The way that we connect things in low-frequency read mode. In this case\r
1c38843b 3// we are generating the unmodulated low frequency carrier.\r
4// The A/D samples at that same rate and the result is serialized.\r
6658905f 5//\r
6// Jonathan Westhues, April 2006\r
7//-----------------------------------------------------------------------------\r
8\r
9module lo_read(\r
10 pck0, ck_1356meg, ck_1356megb,\r
11 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
12 adc_d, adc_clk,\r
13 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
14 cross_hi, cross_lo,\r
15 dbg,\r
30f2a7d3 16 lo_is_125khz, divisor\r
6658905f 17);\r
18 input pck0, ck_1356meg, ck_1356megb;\r
19 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
20 input [7:0] adc_d;\r
21 output adc_clk;\r
22 input ssp_dout;\r
23 output ssp_frame, ssp_din, ssp_clk;\r
24 input cross_hi, cross_lo;\r
25 output dbg;\r
1c38843b 26 input lo_is_125khz; // redundant signal, no longer used anywhere\r
30f2a7d3 27 input [7:0] divisor;\r
6658905f 28\r
6658905f 29reg [7:0] to_arm_shiftreg;\r
30f2a7d3 30reg [7:0] pck_divider;\r
30f2a7d3 31reg ant_lo;\r
6658905f 32\r
1c38843b 33// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo\r
34// which is high for (divisor+1) pck0 cycles and low for the same duration\r
35// ant_lo is therefore a 50% duty cycle clock signal with a frequency of\r
36// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk\r
30f2a7d3 37always @(posedge pck0)\r
6658905f 38begin\r
1c38843b 39 if(pck_divider == divisor[7:0])\r
30f2a7d3 40 begin\r
1c38843b 41 pck_divider <= 8'd0;\r
30f2a7d3 42 ant_lo = !ant_lo;\r
30f2a7d3 43 end\r
44 else\r
45 begin\r
1c38843b 46 pck_divider <= pck_divider + 1;\r
47 end\r
48end\r
49\r
50// this task also runs at pck0 frequency (24Mhz) and is used to serialize\r
51// the ADC output which is then clocked into the ARM SSP.\r
52\r
53// because ant_lo always transitions when pck_divider = 0 we use the\r
54// pck_divider counter to sync our other signals off it\r
55// we read the ADC value when pck_divider=7 and shift it out on counts 8..15\r
56always @(posedge pck0)\r
57begin\r
58 if((pck_divider == 8'd7) && !ant_lo)\r
59 to_arm_shiftreg <= adc_d;\r
60 else\r
61 begin\r
62 to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];\r
63 // simulation showed a glitch occuring due to the LSB of the shifter\r
64 // not being set as we shift bits out\r
65 // this ensures the ssp_din remains low after a transfer and suppresses\r
66 // the glitch that would occur when the last data shifted out ended in\r
67 // a 1 bit and the next data shifted out started with a 0 bit\r
68 to_arm_shiftreg[0] <= 1'b0;\r
30f2a7d3 69 end\r
6658905f 70end\r
71\r
1c38843b 72// ADC samples on falling edge of adc_clk, data available on the rising edge\r
73\r
74// example of ssp transfer of binary value 1100101\r
75// start of transfer is indicated by the rise of the ssp_frame signal\r
76// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into\r
77// the ARM by the falling edge of ssp_clk\r
78// _______________________________\r
79// ssp_frame__| |__\r
80// _______ ___ ___\r
81// ssp_din __| |_______| |___| |______\r
82// _ _ _ _ _ _ _ _ _ _\r
83// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_\r
84\r
85// serialized SSP data is gated by ant_lo to suppress unwanted signal\r
86assign ssp_din = to_arm_shiftreg[7] && !ant_lo;\r
87// SSP clock always runs at 24Mhz\r
88assign ssp_clk = pck0;\r
89// SSP frame is gated by ant_lo and goes high when pck_divider=8..15\r
90assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo;\r
91// unused signals tied low\r
6658905f 92assign pwr_hi = 1'b0;\r
1c38843b 93assign pwr_oe1 = 1'b0;\r
94assign pwr_oe2 = 1'b0;\r
95assign pwr_oe3 = 1'b0;\r
96assign pwr_oe4 = 1'b0;\r
97// this is the antenna driver signal\r
30f2a7d3 98assign pwr_lo = ant_lo;\r
1c38843b 99// ADC clock out of phase with antenna driver\r
30f2a7d3 100assign adc_clk = ~ant_lo;\r
1c38843b 101// ADC clock also routed to debug pin\r
6658905f 102assign dbg = adc_clk;\r
6658905f 103endmodule\r
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