More CRLF -> LF conversion

[proxmark3-svn] / fpga / testbed_fpga.v

`include "fpga.v"\r
\r
module testbed_fpga;\r
    reg spck, mosi, ncs;\r
    wire miso;\r
    reg pck0i, ck_1356meg, ck_1356megb;\r
    wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
    reg [7:0] adc_d;\r
    wire adc_clk, adc_noe;\r
    reg ssp_dout;\r
    wire ssp_frame, ssp_din, ssp_clk;\r
\r
    fpga dut(\r
        spck, miso, mosi, ncs,\r
        pck0i, ck_1356meg, ck_1356megb,\r
        pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
        adc_d, adc_clk, adc_noe,\r
        ssp_frame, ssp_din, ssp_dout, ssp_clk\r
    );\r
\r
	integer i;\r
\r
	initial begin\r
\r
		// init inputs\r
		#5 ncs=1;\r
		#5 spck = 1;\r
		#5 mosi = 1;\r
\r
		#50 ncs=0;\r
		for (i = 0 ;  i < 8 ;  i = i + 1) begin\r
			#5 mosi = $random;\r
			#5 spck = 0;\r
			#5 spck = 1;\r
		end\r
		#5 ncs=1;\r
\r
		#50 ncs=0;\r
		for (i = 0 ;  i < 8 ;  i = i + 1) begin\r
			#5 mosi = $random;\r
			#5 spck = 0;\r
			#5 spck = 1;\r
		end\r
		#5 ncs=1;\r
\r
		#50 mosi=1;\r
		$finish;\r
	end\r
	\r
endmodule // main\r