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[proxmark3-svn] / fpga / testbed_fpga.v
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6658905f 1`include "fpga.v"\r
2\r
3module testbed_fpga;\r
4 reg spck, mosi, ncs;\r
5 wire miso;\r
6 reg pck0i, ck_1356meg, ck_1356megb;\r
7 wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
8 reg [7:0] adc_d;\r
9 wire adc_clk, adc_noe;\r
10 reg ssp_dout;\r
11 wire ssp_frame, ssp_din, ssp_clk;\r
12\r
13 fpga dut(\r
14 spck, miso, mosi, ncs,\r
15 pck0i, ck_1356meg, ck_1356megb,\r
16 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
17 adc_d, adc_clk, adc_noe,\r
18 ssp_frame, ssp_din, ssp_dout, ssp_clk\r
19 );\r
20\r
21 integer i;\r
22\r
23 initial begin\r
24\r
25 // init inputs\r
26 #5 ncs=1;\r
27 #5 spck = 1;\r
28 #5 mosi = 1;\r
29\r
30 #50 ncs=0;\r
31 for (i = 0 ; i < 8 ; i = i + 1) begin\r
32 #5 mosi = $random;\r
33 #5 spck = 0;\r
34 #5 spck = 1;\r
35 end\r
36 #5 ncs=1;\r
37\r
38 #50 ncs=0;\r
39 for (i = 0 ; i < 8 ; i = i + 1) begin\r
40 #5 mosi = $random;\r
41 #5 spck = 0;\r
42 #5 spck = 1;\r
43 end\r
44 #5 ncs=1;\r
45\r
46 #50 mosi=1;\r
47 $finish;\r
48 end\r
49 \r
50endmodule // main\r
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