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[proxmark3-svn] / armsrc / lfops.c
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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
15c4dc5a 6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10
e30c654b 11#include "proxmark3.h"
15c4dc5a 12#include "apps.h"
f7e3ed82 13#include "util.h"
15c4dc5a 14#include "hitag2.h"
15#include "crc16.h"
9ab7a6c7 16#include "string.h"
7db5f1ca 17#include "lfdemod.h"
15c4dc5a 18
b2256785
MHS		 19
20/**
ba1a299c 21* Does the sample acquisition. If threshold is specified, the actual sampling
22* is not commenced until the threshold has been reached.
b2256785
MHS		 23* @param trigger_threshold - the threshold
24* @param silent - is true, now outputs are made. If false, dbprints the status
25*/
f97d4e23 26void DoAcquisition125k_internal(int trigger_threshold,bool silent)
69d88ec4 27{
ae8e8a43
MHS		 28 uint8_t *dest = (uint8_t *)BigBuf;
29 int n = sizeof(BigBuf);
30 int i;
31
32 memset(dest, 0, n);
33 i = 0;
34 for(;;) {
35 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
36 AT91C_BASE_SSC->SSC_THR = 0x43;
37 LED_D_ON();
38 }
39 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
40 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
41 LED_D_OFF();
42 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
43 continue;
44 else
45 trigger_threshold = -1;
46 if (++i >= n) break;
47 }
48 }
49 if(!silent)
50 {
51 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
52 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
53
54 }
69d88ec4 55}
b2256785 56/**
ba1a299c 57* Perform sample aquisition.
b2256785 58*/
f97d4e23 59void DoAcquisition125k(int trigger_threshold)
69d88ec4 60{
ae8e8a43 61 DoAcquisition125k_internal(trigger_threshold, false);
69d88ec4
MHS		 62}
63
b2256785 64/**
ba1a299c 65* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
66* if not already loaded, sets divisor and starts up the antenna.
b2256785
MHS		 67* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
68* 0 or 95 ==> 125 KHz
ba1a299c 69*
b2256785 70**/
b014c96d 71void LFSetupFPGAForADC(int divisor, bool lf_field)
15c4dc5a 72{
ae8e8a43
MHS		 73 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
74 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
75 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
76 else if (divisor == 0)
77 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
78 else
79 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
80
81 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
82
83 // Connect the A/D to the peak-detected low-frequency path.
84 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
85 // Give it a bit of time for the resonant antenna to settle.
86 SpinDelay(50);
87 // Now set up the SSC to get the ADC samples that are now streaming at us.
88 FpgaSetupSsc();
15c4dc5a 89}
b2256785 90/**
ba1a299c 91* Initializes the FPGA, and acquires the samples.
b2256785 92**/
69d88ec4 93void AcquireRawAdcSamples125k(int divisor)
15c4dc5a 94{
ae8e8a43
MHS		 95 LFSetupFPGAForADC(divisor, true);
96 // Now call the acquisition routine
97 DoAcquisition125k_internal(-1,false);
b014c96d 98}
b2256785 99/**
ba1a299c 100* Initializes the FPGA for snoop-mode, and acquires the samples.
b2256785
MHS		 101**/
102
b014c96d 103void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
104{
ae8e8a43
MHS		 105 LFSetupFPGAForADC(divisor, false);
106 DoAcquisition125k(trigger_threshold);
15c4dc5a 107}
108
f7e3ed82 109void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
15c4dc5a 110{
15c4dc5a 111
ae8e8a43
MHS		 112 /* Make sure the tag is reset */
113 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
115 SpinDelay(2500);
e30c654b 116
b2256785 117
ae8e8a43
MHS		 118 int divisor_used = 95; // 125 KHz
119 // see if 'h' was specified
b2256785 120
ae8e8a43
MHS		 121 if (command[strlen((char *) command) - 1] == 'h')
122 divisor_used = 88; // 134.8 KHz
15c4dc5a 123
15c4dc5a 124
ae8e8a43
MHS		 125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
127 // Give it a bit of time for the resonant antenna to settle.
128 SpinDelay(50);
b2256785 129
ae8e8a43
MHS		 130 // And a little more time for the tag to fully power up
131 SpinDelay(2000);
15c4dc5a 132
ae8e8a43
MHS		 133 // Now set up the SSC to get the ADC samples that are now streaming at us.
134 FpgaSetupSsc();
15c4dc5a 135
ae8e8a43
MHS		 136 // now modulate the reader field
137 while(*command != '\0' && *command != ' ') {
138 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
139 LED_D_OFF();
140 SpinDelayUs(delay_off);
141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
15c4dc5a 142
ae8e8a43
MHS		 143 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
144 LED_D_ON();
145 if(*(command++) == '0')
146 SpinDelayUs(period_0);
147 else
148 SpinDelayUs(period_1);
149 }
150 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
151 LED_D_OFF();
152 SpinDelayUs(delay_off);
153 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
15c4dc5a 154
ae8e8a43 155 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
15c4dc5a 156
ae8e8a43
MHS		 157 // now do the read
158 DoAcquisition125k(-1);
15c4dc5a 159}
160
161/* blank r/w tag data stream
162...0000000000000000 01111111
1631010101010101010101010101010101010101010101010101010101010101010
1640011010010100001
16501111111
166101010101010101[0]000...
167
168[5555fe852c5555555555555555fe0000]
169*/
170void ReadTItag(void)
171{
ae8e8a43
MHS		 172 // some hardcoded initial params
173 // when we read a TI tag we sample the zerocross line at 2Mhz
174 // TI tags modulate a 1 as 16 cycles of 123.2Khz
175 // TI tags modulate a 0 as 16 cycles of 134.2Khz
ba1a299c 176 #define FSAMPLE 2000000
177 #define FREQLO 123200
178 #define FREQHI 134200
ae8e8a43
MHS		 179
180 signed char *dest = (signed char *)BigBuf;
181 int n = sizeof(BigBuf);
ae8e8a43
MHS		 182 // 128 bit shift register [shift3:shift2:shift1:shift0]
183 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
184
185 int i, cycles=0, samples=0;
186 // how many sample points fit in 16 cycles of each frequency
187 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
188 // when to tell if we're close enough to one freq or another
189 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
190
191 // TI tags charge at 134.2Khz
192 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
193 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
194
195 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
196 // connects to SSP_DIN and the SSP_DOUT logic level controls
197 // whether we're modulating the antenna (high)
198 // or listening to the antenna (low)
199 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
200
201 // get TI tag data into the buffer
202 AcquireTiType();
203
204 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
205
206 for (i=0; i<n-1; i++) {
207 // count cycles by looking for lo to hi zero crossings
208 if ( (dest[i]<0) && (dest[i+1]>0) ) {
209 cycles++;
210 // after 16 cycles, measure the frequency
211 if (cycles>15) {
212 cycles=0;
213 samples=i-samples; // number of samples in these 16 cycles
214
215 // TI bits are coming to us lsb first so shift them
216 // right through our 128 bit right shift register
217 shift0 = (shift0>>1) | (shift1 << 31);
218 shift1 = (shift1>>1) | (shift2 << 31);
219 shift2 = (shift2>>1) | (shift3 << 31);
220 shift3 >>= 1;
221
222 // check if the cycles fall close to the number
223 // expected for either the low or high frequency
224 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
225 // low frequency represents a 1
226 shift3 |= (1<<31);
227 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
228 // high frequency represents a 0
229 } else {
230 // probably detected a gay waveform or noise
231 // use this as gaydar or discard shift register and start again
232 shift3 = shift2 = shift1 = shift0 = 0;
233 }
234 samples = i;
235
236 // for each bit we receive, test if we've detected a valid tag
237
238 // if we see 17 zeroes followed by 6 ones, we might have a tag
239 // remember the bits are backwards
240 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
241 // if start and end bytes match, we have a tag so break out of the loop
242 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
243 cycles = 0xF0B; //use this as a flag (ugly but whatever)
244 break;
245 }
246 }
247 }
248 }
249 }
250
251 // if flag is set we have a tag
252 if (cycles!=0xF0B) {
253 DbpString("Info: No valid tag detected.");
254 } else {
255 // put 64 bit data into shift1 and shift0
256 shift0 = (shift0>>24) | (shift1 << 8);
257 shift1 = (shift1>>24) | (shift2 << 8);
258
259 // align 16 bit crc into lower half of shift2
260 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
261
262 // if r/w tag, check ident match
ba1a299c 263 if (shift3 & (1<<15) ) {
ae8e8a43
MHS		 264 DbpString("Info: TI tag is rewriteable");
265 // only 15 bits compare, last bit of ident is not valid
ba1a299c 266 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
ae8e8a43
MHS		 267 DbpString("Error: Ident mismatch!");
268 } else {
269 DbpString("Info: TI tag ident is valid");
270 }
271 } else {
272 DbpString("Info: TI tag is readonly");
273 }
274
275 // WARNING the order of the bytes in which we calc crc below needs checking
276 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
277 // bytes in reverse or something
278 // calculate CRC
279 uint32_t crc=0;
280
281 crc = update_crc16(crc, (shift0)&0xff);
282 crc = update_crc16(crc, (shift0>>8)&0xff);
283 crc = update_crc16(crc, (shift0>>16)&0xff);
284 crc = update_crc16(crc, (shift0>>24)&0xff);
285 crc = update_crc16(crc, (shift1)&0xff);
286 crc = update_crc16(crc, (shift1>>8)&0xff);
287 crc = update_crc16(crc, (shift1>>16)&0xff);
288 crc = update_crc16(crc, (shift1>>24)&0xff);
289
290 Dbprintf("Info: Tag data: %x%08x, crc=%x",
291 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
292 if (crc != (shift2&0xffff)) {
293 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
294 } else {
295 DbpString("Info: CRC is good");
296 }
297 }
15c4dc5a 298}
299
f7e3ed82 300void WriteTIbyte(uint8_t b)
15c4dc5a 301{
ae8e8a43
MHS		 302 int i = 0;
303
304 // modulate 8 bits out to the antenna
305 for (i=0; i<8; i++)
306 {
307 if (b&(1<<i)) {
308 // stop modulating antenna
309 LOW(GPIO_SSC_DOUT);
310 SpinDelayUs(1000);
311 // modulate antenna
312 HIGH(GPIO_SSC_DOUT);
313 SpinDelayUs(1000);
314 } else {
315 // stop modulating antenna
316 LOW(GPIO_SSC_DOUT);
317 SpinDelayUs(300);
318 // modulate antenna
319 HIGH(GPIO_SSC_DOUT);
320 SpinDelayUs(1700);
321 }
322 }
15c4dc5a 323}
324
325void AcquireTiType(void)
326{
ae8e8a43
MHS		 327 int i, j, n;
328 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
329 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
ba1a299c 330 #define TIBUFLEN 1250
ae8e8a43
MHS		 331
332 // clear buffer
333 memset(BigBuf,0,sizeof(BigBuf));
334
335 // Set up the synchronous serial port
336 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
337 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
338
339 // steal this pin from the SSP and use it to control the modulation
340 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
341 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
342
343 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
344 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
345
346 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
347 // 48/2 = 24 MHz clock must be divided by 12
348 AT91C_BASE_SSC->SSC_CMR = 12;
349
350 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
351 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
352 AT91C_BASE_SSC->SSC_TCMR = 0;
353 AT91C_BASE_SSC->SSC_TFMR = 0;
354
355 LED_D_ON();
356
357 // modulate antenna
358 HIGH(GPIO_SSC_DOUT);
359
360 // Charge TI tag for 50ms.
361 SpinDelay(50);
362
363 // stop modulating antenna and listen
364 LOW(GPIO_SSC_DOUT);
365
366 LED_D_OFF();
367
368 i = 0;
369 for(;;) {
370 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
371 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
372 i++; if(i >= TIBUFLEN) break;
373 }
374 WDT_HIT();
375 }
376
377 // return stolen pin to SSP
378 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
379 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
380
381 char *dest = (char *)BigBuf;
382 n = TIBUFLEN*32;
383 // unpack buffer
384 for (i=TIBUFLEN-1; i>=0; i--) {
385 for (j=0; j<32; j++) {
386 if(BigBuf[i] & (1 << j)) {
387 dest[--n] = 1;
388 } else {
389 dest[--n] = -1;
390 }
391 }
392 }
15c4dc5a 393}
394
395// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
396// if crc provided, it will be written with the data verbatim (even if bogus)
397// if not provided a valid crc will be computed from the data and written.
f7e3ed82 398void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
15c4dc5a 399{
ae8e8a43
MHS		 400 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
401 if(crc == 0) {
402 crc = update_crc16(crc, (idlo)&0xff);
403 crc = update_crc16(crc, (idlo>>8)&0xff);
404 crc = update_crc16(crc, (idlo>>16)&0xff);
405 crc = update_crc16(crc, (idlo>>24)&0xff);
406 crc = update_crc16(crc, (idhi)&0xff);
407 crc = update_crc16(crc, (idhi>>8)&0xff);
408 crc = update_crc16(crc, (idhi>>16)&0xff);
409 crc = update_crc16(crc, (idhi>>24)&0xff);
410 }
411 Dbprintf("Writing to tag: %x%08x, crc=%x",
412 (unsigned int) idhi, (unsigned int) idlo, crc);
413
414 // TI tags charge at 134.2Khz
415 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
416 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
417 // connects to SSP_DIN and the SSP_DOUT logic level controls
418 // whether we're modulating the antenna (high)
419 // or listening to the antenna (low)
420 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
421 LED_A_ON();
422
423 // steal this pin from the SSP and use it to control the modulation
424 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
425 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
426
427 // writing algorithm:
428 // a high bit consists of a field off for 1ms and field on for 1ms
429 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
430 // initiate a charge time of 50ms (field on) then immediately start writing bits
431 // start by writing 0xBB (keyword) and 0xEB (password)
432 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
433 // finally end with 0x0300 (write frame)
434 // all data is sent lsb firts
435 // finish with 15ms programming time
436
437 // modulate antenna
438 HIGH(GPIO_SSC_DOUT);
439 SpinDelay(50); // charge time
440
441 WriteTIbyte(0xbb); // keyword
442 WriteTIbyte(0xeb); // password
443 WriteTIbyte( (idlo )&0xff );
444 WriteTIbyte( (idlo>>8 )&0xff );
445 WriteTIbyte( (idlo>>16)&0xff );
446 WriteTIbyte( (idlo>>24)&0xff );
447 WriteTIbyte( (idhi )&0xff );
448 WriteTIbyte( (idhi>>8 )&0xff );
449 WriteTIbyte( (idhi>>16)&0xff );
450 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
451 WriteTIbyte( (crc )&0xff ); // crc lo
452 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
453 WriteTIbyte(0x00); // write frame lo
454 WriteTIbyte(0x03); // write frame hi
455 HIGH(GPIO_SSC_DOUT);
456 SpinDelay(50); // programming time
457
458 LED_A_OFF();
459
460 // get TI tag data into the buffer
461 AcquireTiType();
462
463 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
464 DbpString("Now use tiread to check");
15c4dc5a 465}
466
467void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
468{
ae8e8a43
MHS		 469 int i;
470 uint8_t *tab = (uint8_t *)BigBuf;
ba1a299c 471
ae8e8a43
MHS		 472 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
473 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
ba1a299c 474
ae8e8a43 475 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
ba1a299c 476
ae8e8a43
MHS		 477 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
478 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
ba1a299c 479
15c4dc5a 480#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
481#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
ba1a299c 482
ae8e8a43
MHS		 483 i = 0;
484 for(;;) {
485 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
486 if(BUTTON_PRESS()) {
487 DbpString("Stopped");
488 return;
489 }
490 WDT_HIT();
491 }
952a8bb5 492
ae8e8a43
MHS		 493 if (ledcontrol)
494 LED_D_ON();
952a8bb5 495
ae8e8a43
MHS		 496 if(tab[i])
497 OPEN_COIL();
498 else
499 SHORT_COIL();
952a8bb5 500
ae8e8a43
MHS		 501 if (ledcontrol)
502 LED_D_OFF();
952a8bb5 503
ae8e8a43
MHS		 504 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
505 if(BUTTON_PRESS()) {
506 DbpString("Stopped");
507 return;
508 }
509 WDT_HIT();
510 }
952a8bb5 511
ae8e8a43
MHS		 512 i++;
513 if(i == period) {
514 i = 0;
515 if (gap) {
516 SHORT_COIL();
517 SpinDelayUs(gap);
518 }
519 }
520 }
15c4dc5a 521}
522
15c4dc5a 523#define DEBUG_FRAME_CONTENTS 1
524void SimulateTagLowFrequencyBidir(int divisor, int t0)
525{
15c4dc5a 526}
527
528// compose fc/8 fc/10 waveform
529static void fc(int c, int *n) {
ae8e8a43
MHS		 530 uint8_t *dest = (uint8_t *)BigBuf;
531 int idx;
532
533 // for when we want an fc8 pattern every 4 logical bits
534 if(c==0) {
535 dest[((*n)++)]=1;
536 dest[((*n)++)]=1;
537 dest[((*n)++)]=0;
538 dest[((*n)++)]=0;
539 dest[((*n)++)]=0;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 }
544 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
545 if(c==8) {
546 for (idx=0; idx<6; idx++) {
547 dest[((*n)++)]=1;
548 dest[((*n)++)]=1;
549 dest[((*n)++)]=0;
550 dest[((*n)++)]=0;
551 dest[((*n)++)]=0;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 }
556 }
557
558 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
559 if(c==10) {
560 for (idx=0; idx<5; idx++) {
561 dest[((*n)++)]=1;
562 dest[((*n)++)]=1;
563 dest[((*n)++)]=1;
564 dest[((*n)++)]=0;
565 dest[((*n)++)]=0;
566 dest[((*n)++)]=0;
567 dest[((*n)++)]=0;
568 dest[((*n)++)]=0;
569 dest[((*n)++)]=0;
570 dest[((*n)++)]=0;
571 }
572 }
15c4dc5a 573}
574
575// prepare a waveform pattern in the buffer based on the ID given then
576// simulate a HID tag until the button is pressed
577void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
578{
ae8e8a43
MHS		 579 int n=0, i=0;
580 /*
581 HID tag bitstream format
582 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
583 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
584 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
585 A fc8 is inserted before every 4 bits
586 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
587 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
588 */
589
590 if (hi>0xFFF) {
591 DbpString("Tags can only have 44 bits.");
592 return;
593 }
594 fc(0,&n);
595 // special start of frame marker containing invalid bit sequences
596 fc(8, &n); fc(8, &n); // invalid
597 fc(8, &n); fc(10, &n); // logical 0
598 fc(10, &n); fc(10, &n); // invalid
599 fc(8, &n); fc(10, &n); // logical 0
600
601 WDT_HIT();
602 // manchester encode bits 43 to 32
603 for (i=11; i>=0; i--) {
604 if ((i%4)==3) fc(0,&n);
605 if ((hi>>i)&1) {
606 fc(10, &n); fc(8, &n); // low-high transition
607 } else {
608 fc(8, &n); fc(10, &n); // high-low transition
609 }
610 }
611
612 WDT_HIT();
613 // manchester encode bits 31 to 0
614 for (i=31; i>=0; i--) {
615 if ((i%4)==3) fc(0,&n);
616 if ((lo>>i)&1) {
617 fc(10, &n); fc(8, &n); // low-high transition
618 } else {
619 fc(8, &n); fc(10, &n); // high-low transition
620 }
621 }
622
623 if (ledcontrol)
624 LED_A_ON();
625 SimulateTagLowFrequency(n, 0, ledcontrol);
626
627 if (ledcontrol)
628 LED_A_OFF();
15c4dc5a 629}
eb191de6 630
b3b70669 631// loop to get raw HID waveform then FSK demodulate the TAG ID from it
69d88ec4
MHS		 632void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
633{
ae8e8a43
MHS		 634 uint8_t *dest = (uint8_t *)BigBuf;
635
a1d17964 636 size_t size=sizeof(BigBuf);
ae8e8a43 637 uint32_t hi2=0, hi=0, lo=0;
a1d17964 638 int idx=0;
ae8e8a43
MHS		 639 // Configure to go in 125Khz listen mode
640 LFSetupFPGAForADC(95, true);
641
642 while(!BUTTON_PRESS()) {
643
644 WDT_HIT();
645 if (ledcontrol) LED_A_ON();
646
647 DoAcquisition125k_internal(-1,true);
ae8e8a43 648 // FSK demodulator
ae8e8a43 649 WDT_HIT();
a1d17964 650 size = sizeof(BigBuf);
ae8e8a43 651
a1d17964 652 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
653
ec75f5c1 654 if (idx>0 && lo>0){
ae8e8a43
MHS		 655 // final loop, go over previously decoded manchester data and decode into usable tag ID
656 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
657 if (hi2 != 0){ //extra large HID tags
658 Dbprintf("TAG ID: %x%08x%08x (%d)",
659 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
660 }else { //standard HID tags <38 bits
661 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
662 uint8_t bitlen = 0;
663 uint32_t fc = 0;
664 uint32_t cardnum = 0;
ba1a299c 665 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
ae8e8a43
MHS		 666 uint32_t lo2=0;
667 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
668 uint8_t idx3 = 1;
ba1a299c 669 while(lo2 > 1){ //find last bit set to 1 (format len bit)
670 lo2=lo2 >> 1;
ae8e8a43
MHS		 671 idx3++;
672 }
ba1a299c 673 bitlen = idx3+19;
ae8e8a43
MHS		 674 fc =0;
675 cardnum=0;
ba1a299c 676 if(bitlen == 26){
ae8e8a43
MHS		 677 cardnum = (lo>>1)&0xFFFF;
678 fc = (lo>>17)&0xFF;
679 }
ba1a299c 680 if(bitlen == 37){
ae8e8a43
MHS		 681 cardnum = (lo>>1)&0x7FFFF;
682 fc = ((hi&0xF)<<12)|(lo>>20);
683 }
ba1a299c 684 if(bitlen == 34){
ae8e8a43
MHS		 685 cardnum = (lo>>1)&0xFFFF;
686 fc= ((hi&1)<<15)|(lo>>17);
687 }
ba1a299c 688 if(bitlen == 35){
ae8e8a43
MHS		 689 cardnum = (lo>>1)&0xFFFFF;
690 fc = ((hi&1)<<11)|(lo>>21);
691 }
692 }
693 else { //if bit 38 is not set then 37 bit format is used
694 bitlen= 37;
695 fc =0;
696 cardnum=0;
697 if(bitlen==37){
698 cardnum = (lo>>1)&0x7FFFF;
699 fc = ((hi&0xF)<<12)|(lo>>20);
700 }
701 }
702 //Dbprintf("TAG ID: %x%08x (%d)",
703 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
704 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
705 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
706 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
707 }
708 if (findone){
709 if (ledcontrol) LED_A_OFF();
710 return;
711 }
712 // reset
713 hi2 = hi = lo = 0;
714 }
715 WDT_HIT();
ae8e8a43
MHS		 716 }
717 DbpString("Stopped");
718 if (ledcontrol) LED_A_OFF();
eb191de6 719}
720
66707a3b 721void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
eb191de6 722{
ae8e8a43
MHS		 723 uint8_t *dest = (uint8_t *)BigBuf;
724
ec75f5c1 725 size_t size=0, idx=0;
ae8e8a43
MHS		 726 int clk=0, invert=0, errCnt=0;
727 uint64_t lo=0;
728 // Configure to go in 125Khz listen mode
729 LFSetupFPGAForADC(95, true);
730
731 while(!BUTTON_PRESS()) {
732
733 WDT_HIT();
734 if (ledcontrol) LED_A_ON();
735
736 DoAcquisition125k_internal(-1,true);
737 size = sizeof(BigBuf);
ae8e8a43 738 //Dbprintf("DEBUG: Buffer got");
d91a31f9 739 //askdemod and manchester decode
740 errCnt = askmandemod(dest, &size, &clk, &invert);
ae8e8a43
MHS		 741 //Dbprintf("DEBUG: ASK Got");
742 WDT_HIT();
743
744 if (errCnt>=0){
ec75f5c1 745 lo = Em410xDecode(dest, &size, &idx);
ae8e8a43 746 //Dbprintf("DEBUG: EM GOT");
ae8e8a43 747 if (lo>0){
d91a31f9 748 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
749 (uint32_t)(lo>>32),
750 (uint32_t)lo,
751 (uint32_t)(lo&0xFFFF),
752 (uint32_t)((lo>>16LL) & 0xFF),
753 (uint32_t)(lo & 0xFFFFFF));
ae8e8a43
MHS		 754 }
755 if (findone){
756 if (ledcontrol) LED_A_OFF();
757 return;
758 }
759 } else{
760 //Dbprintf("DEBUG: No Tag");
761 }
762 WDT_HIT();
763 lo = 0;
764 clk=0;
765 invert=0;
766 errCnt=0;
767 size=0;
ae8e8a43
MHS		 768 }
769 DbpString("Stopped");
770 if (ledcontrol) LED_A_OFF();
15c4dc5a 771}
69d88ec4 772
a1f3bb12 773void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
eb191de6 774{
ae8e8a43 775 uint8_t *dest = (uint8_t *)BigBuf;
ae8e8a43
MHS		 776 int idx=0;
777 uint32_t code=0, code2=0;
778 uint8_t version=0;
779 uint8_t facilitycode=0;
780 uint16_t number=0;
781 // Configure to go in 125Khz listen mode
782 LFSetupFPGAForADC(95, true);
783
784 while(!BUTTON_PRESS()) {
785 WDT_HIT();
786 if (ledcontrol) LED_A_ON();
787 DoAcquisition125k_internal(-1,true);
788 //fskdemod and get start index
789 WDT_HIT();
6ca4c646 790 idx = IOdemodFSK(dest,sizeof(BigBuf));
ae8e8a43
MHS		 791 if (idx>0){
792 //valid tag found
793
794 //Index map
795 //0 10 20 30 40 50 60
796 //| | | | | | |
797 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
798 //-----------------------------------------------------------------------------
799 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
800 //
801 //XSF(version)facility:codeone+codetwo
802 //Handle the data
803 if(findone){ //only print binary if we are doing one
804 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
805 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
806 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
807 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
808 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
809 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
810 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
811 }
812 code = bytebits_to_byte(dest+idx,32);
813 code2 = bytebits_to_byte(dest+idx+32,32);
814 version = bytebits_to_byte(dest+idx+27,8); //14,4
815 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
816 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
817
818 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
819 // if we're only looking for one tag
820 if (findone){
821 if (ledcontrol) LED_A_OFF();
822 //LED_A_OFF();
823 return;
824 }
825 code=code2=0;
826 version=facilitycode=0;
827 number=0;
828 idx=0;
829 }
830 WDT_HIT();
831 }
832 DbpString("Stopped");
833 if (ledcontrol) LED_A_OFF();
eb191de6 834}
a1f3bb12 835
2d4eae76 836/*------------------------------
837 * T5555/T5557/T5567 routines
838 *------------------------------
839 */
840
841/* T55x7 configuration register definitions */
842#define T55x7_POR_DELAY 0x00000001
843#define T55x7_ST_TERMINATOR 0x00000008
844#define T55x7_PWD 0x00000010
845#define T55x7_MAXBLOCK_SHIFT 5
846#define T55x7_AOR 0x00000200
847#define T55x7_PSKCF_RF_2 0
848#define T55x7_PSKCF_RF_4 0x00000400
849#define T55x7_PSKCF_RF_8 0x00000800
850#define T55x7_MODULATION_DIRECT 0
851#define T55x7_MODULATION_PSK1 0x00001000
852#define T55x7_MODULATION_PSK2 0x00002000
853#define T55x7_MODULATION_PSK3 0x00003000
854#define T55x7_MODULATION_FSK1 0x00004000
855#define T55x7_MODULATION_FSK2 0x00005000
856#define T55x7_MODULATION_FSK1a 0x00006000
857#define T55x7_MODULATION_FSK2a 0x00007000
858#define T55x7_MODULATION_MANCHESTER 0x00008000
859#define T55x7_MODULATION_BIPHASE 0x00010000
860#define T55x7_BITRATE_RF_8 0
861#define T55x7_BITRATE_RF_16 0x00040000
862#define T55x7_BITRATE_RF_32 0x00080000
863#define T55x7_BITRATE_RF_40 0x000C0000
864#define T55x7_BITRATE_RF_50 0x00100000
865#define T55x7_BITRATE_RF_64 0x00140000
866#define T55x7_BITRATE_RF_100 0x00180000
867#define T55x7_BITRATE_RF_128 0x001C0000
868
869/* T5555 (Q5) configuration register definitions */
870#define T5555_ST_TERMINATOR 0x00000001
871#define T5555_MAXBLOCK_SHIFT 0x00000001
872#define T5555_MODULATION_MANCHESTER 0
873#define T5555_MODULATION_PSK1 0x00000010
874#define T5555_MODULATION_PSK2 0x00000020
875#define T5555_MODULATION_PSK3 0x00000030
876#define T5555_MODULATION_FSK1 0x00000040
877#define T5555_MODULATION_FSK2 0x00000050
878#define T5555_MODULATION_BIPHASE 0x00000060
879#define T5555_MODULATION_DIRECT 0x00000070
880#define T5555_INVERT_OUTPUT 0x00000080
881#define T5555_PSK_RF_2 0
882#define T5555_PSK_RF_4 0x00000100
883#define T5555_PSK_RF_8 0x00000200
884#define T5555_USE_PWD 0x00000400
885#define T5555_USE_AOR 0x00000800
886#define T5555_BITRATE_SHIFT 12
887#define T5555_FAST_WRITE 0x00004000
888#define T5555_PAGE_SELECT 0x00008000
889
890/*
891 * Relevant times in microsecond
892 * To compensate antenna falling times shorten the write times
893 * and enlarge the gap ones.
894 */
895#define START_GAP 250
896#define WRITE_GAP 160
897#define WRITE_0 144 // 192
898#define WRITE_1 400 // 432 for T55x7; 448 for E5550
899
900// Write one bit to card
901void T55xxWriteBit(int bit)
ec09b62d 902{
ae8e8a43
MHS		 903 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
904 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
905 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
906 if (bit == 0)
907 SpinDelayUs(WRITE_0);
908 else
909 SpinDelayUs(WRITE_1);
910 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
911 SpinDelayUs(WRITE_GAP);
ec09b62d 912}
913
2d4eae76 914// Write one card block in page 0, no lock
54a942b0 915void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 916{
ae8e8a43
MHS		 917 //unsigned int i; //enio adjustment 12/10/14
918 uint32_t i;
919
920 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
921 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
922 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
923
924 // Give it a bit of time for the resonant antenna to settle.
925 // And for the tag to fully power up
926 SpinDelay(150);
927
928 // Now start writting
929 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
930 SpinDelayUs(START_GAP);
931
932 // Opcode
933 T55xxWriteBit(1);
934 T55xxWriteBit(0); //Page 0
935 if (PwdMode == 1){
936 // Pwd
937 for (i = 0x80000000; i != 0; i >>= 1)
938 T55xxWriteBit(Pwd & i);
939 }
940 // Lock bit
941 T55xxWriteBit(0);
942
943 // Data
54a942b0 944 for (i = 0x80000000; i != 0; i >>= 1)
ae8e8a43
MHS		 945 T55xxWriteBit(Data & i);
946
947 // Block
948 for (i = 0x04; i != 0; i >>= 1)
949 T55xxWriteBit(Block & i);
950
951 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
952 // so wait a little more)
953 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
954 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
955 SpinDelay(20);
956 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
ec09b62d 957}
958
54a942b0 959// Read one card block in page 0
960void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
ec09b62d 961{
ae8e8a43
MHS		 962 uint8_t *dest = (uint8_t *)BigBuf;
963 //int m=0, i=0; //enio adjustment 12/10/14
964 uint32_t m=0, i=0;
965 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
966 m = sizeof(BigBuf);
967 // Clear destination buffer before sending the command
968 memset(dest, 128, m);
969 // Connect the A/D to the peak-detected low-frequency path.
970 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
971 // Now set up the SSC to get the ADC samples that are now streaming at us.
972 FpgaSetupSsc();
973
974 LED_D_ON();
975 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
976 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
977
978 // Give it a bit of time for the resonant antenna to settle.
979 // And for the tag to fully power up
980 SpinDelay(150);
981
982 // Now start writting
983 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
984 SpinDelayUs(START_GAP);
985
986 // Opcode
987 T55xxWriteBit(1);
988 T55xxWriteBit(0); //Page 0
989 if (PwdMode == 1){
990 // Pwd
991 for (i = 0x80000000; i != 0; i >>= 1)
992 T55xxWriteBit(Pwd & i);
993 }
994 // Lock bit
995 T55xxWriteBit(0);
996 // Block
997 for (i = 0x04; i != 0; i >>= 1)
998 T55xxWriteBit(Block & i);
999
1000 // Turn field on to read the response
1001 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1002 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1003
1004 // Now do the acquisition
1005 i = 0;
1006 for(;;) {
1007 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1008 AT91C_BASE_SSC->SSC_THR = 0x43;
1009 }
1010 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1011 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1012 // we don't care about actual value, only if it's more or less than a
1013 // threshold essentially we capture zero crossings for later analysis
1014 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1015 i++;
1016 if (i >= m) break;
1017 }
1018 }
1019
1020 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1021 LED_D_OFF();
1022 DbpString("DONE!");
54a942b0 1023}
2d4eae76 1024
54a942b0 1025// Read card traceability data (page 1)
1026void T55xxReadTrace(void){
ae8e8a43
MHS		 1027 uint8_t *dest = (uint8_t *)BigBuf;
1028 int m=0, i=0;
1029
1030 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1031 m = sizeof(BigBuf);
1032 // Clear destination buffer before sending the command
1033 memset(dest, 128, m);
1034 // Connect the A/D to the peak-detected low-frequency path.
1035 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1036 // Now set up the SSC to get the ADC samples that are now streaming at us.
1037 FpgaSetupSsc();
1038
1039 LED_D_ON();
1040 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1041 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1042
1043 // Give it a bit of time for the resonant antenna to settle.
1044 // And for the tag to fully power up
1045 SpinDelay(150);
1046
1047 // Now start writting
1048 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1049 SpinDelayUs(START_GAP);
1050
1051 // Opcode
1052 T55xxWriteBit(1);
1053 T55xxWriteBit(1); //Page 1
1054
1055 // Turn field on to read the response
1056 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1057 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1058
1059 // Now do the acquisition
1060 i = 0;
1061 for(;;) {
1062 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1063 AT91C_BASE_SSC->SSC_THR = 0x43;
1064 }
1065 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1066 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1067 i++;
1068 if (i >= m) break;
1069 }
1070 }
1071
1072 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1073 LED_D_OFF();
1074 DbpString("DONE!");
54a942b0 1075}
ec09b62d 1076
54a942b0 1077/*-------------- Cloning routines -----------*/
1078// Copy HID id to card and setup block 0 config
1079void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1080{
ae8e8a43
MHS		 1081 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1082 int last_block = 0;
1083
1084 if (longFMT){
1085 // Ensure no more than 84 bits supplied
1086 if (hi2>0xFFFFF) {
1087 DbpString("Tags can only have 84 bits.");
1088 return;
1089 }
1090 // Build the 6 data blocks for supplied 84bit ID
1091 last_block = 6;
1092 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1093 for (int i=0;i<4;i++) {
1094 if (hi2 & (1<<(19-i)))
1095 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1096 else
1097 data1 |= (1<<((3-i)*2)); // 0 -> 01
1098 }
1099
1100 data2 = 0;
1101 for (int i=0;i<16;i++) {
1102 if (hi2 & (1<<(15-i)))
1103 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1104 else
1105 data2 |= (1<<((15-i)*2)); // 0 -> 01
1106 }
1107
1108 data3 = 0;
1109 for (int i=0;i<16;i++) {
1110 if (hi & (1<<(31-i)))
1111 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1112 else
1113 data3 |= (1<<((15-i)*2)); // 0 -> 01
1114 }
1115
1116 data4 = 0;
1117 for (int i=0;i<16;i++) {
1118 if (hi & (1<<(15-i)))
1119 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1120 else
1121 data4 |= (1<<((15-i)*2)); // 0 -> 01
1122 }
1123
1124 data5 = 0;
1125 for (int i=0;i<16;i++) {
1126 if (lo & (1<<(31-i)))
1127 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1128 else
1129 data5 |= (1<<((15-i)*2)); // 0 -> 01
1130 }
1131
1132 data6 = 0;
1133 for (int i=0;i<16;i++) {
1134 if (lo & (1<<(15-i)))
1135 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1136 else
1137 data6 |= (1<<((15-i)*2)); // 0 -> 01
1138 }
54a942b0 1139 }
ae8e8a43
MHS		 1140 else {
1141 // Ensure no more than 44 bits supplied
1142 if (hi>0xFFF) {
1143 DbpString("Tags can only have 44 bits.");
1144 return;
1145 }
1146
1147 // Build the 3 data blocks for supplied 44bit ID
1148 last_block = 3;
1149
1150 data1 = 0x1D000000; // load preamble
1151
1152 for (int i=0;i<12;i++) {
1153 if (hi & (1<<(11-i)))
1154 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1155 else
1156 data1 |= (1<<((11-i)*2)); // 0 -> 01
1157 }
1158
1159 data2 = 0;
1160 for (int i=0;i<16;i++) {
1161 if (lo & (1<<(31-i)))
1162 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1163 else
1164 data2 |= (1<<((15-i)*2)); // 0 -> 01
1165 }
1166
1167 data3 = 0;
1168 for (int i=0;i<16;i++) {
1169 if (lo & (1<<(15-i)))
1170 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1171 else
1172 data3 |= (1<<((15-i)*2)); // 0 -> 01
1173 }
54a942b0 1174 }
ae8e8a43
MHS		 1175
1176 LED_D_ON();
1177 // Program the data blocks for supplied ID
1178 // and the block 0 for HID format
1179 T55xxWriteBlock(data1,1,0,0);
1180 T55xxWriteBlock(data2,2,0,0);
1181 T55xxWriteBlock(data3,3,0,0);
1182
1183 if (longFMT) { // if long format there are 6 blocks
1184 T55xxWriteBlock(data4,4,0,0);
1185 T55xxWriteBlock(data5,5,0,0);
1186 T55xxWriteBlock(data6,6,0,0);
54a942b0 1187 }
ae8e8a43
MHS		 1188
1189 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1190 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1191 T55x7_MODULATION_FSK2a |
1192 last_block << T55x7_MAXBLOCK_SHIFT,
1193 0,0,0);
1194
1195 LED_D_OFF();
1196
1197 DbpString("DONE!");
2d4eae76 1198}
ec09b62d 1199
a1f3bb12 1200void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1201{
ae8e8a43
MHS		 1202 int data1=0, data2=0; //up to six blocks for long format
1203
a1f3bb12 1204 data1 = hi; // load preamble
1205 data2 = lo;
ba1a299c 1206
a1f3bb12 1207 LED_D_ON();
1208 // Program the data blocks for supplied ID
1209 // and the block 0 for HID format
1210 T55xxWriteBlock(data1,1,0,0);
1211 T55xxWriteBlock(data2,2,0,0);
ae8e8a43 1212
a1f3bb12 1213 //Config Block
1214 T55xxWriteBlock(0x00147040,0,0,0);
1215 LED_D_OFF();
ae8e8a43 1216
a1f3bb12 1217 DbpString("DONE!");
1218}
1219
2d4eae76 1220// Define 9bit header for EM410x tags
1221#define EM410X_HEADER 0x1FF
1222#define EM410X_ID_LENGTH 40
ec09b62d 1223
2d4eae76 1224void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1225{
ae8e8a43
MHS		 1226 int i, id_bit;
1227 uint64_t id = EM410X_HEADER;
1228 uint64_t rev_id = 0; // reversed ID
1229 int c_parity[4]; // column parity
1230 int r_parity = 0; // row parity
1231 uint32_t clock = 0;
1232
1233 // Reverse ID bits given as parameter (for simpler operations)
1234 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1235 if (i < 32) {
1236 rev_id = (rev_id << 1) | (id_lo & 1);
1237 id_lo >>= 1;
1238 } else {
1239 rev_id = (rev_id << 1) | (id_hi & 1);
1240 id_hi >>= 1;
1241 }
1242 }
1243
1244 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1245 id_bit = rev_id & 1;
1246
1247 if (i % 4 == 0) {
1248 // Don't write row parity bit at start of parsing
1249 if (i)
1250 id = (id << 1) | r_parity;
1251 // Start counting parity for new row
1252 r_parity = id_bit;
1253 } else {
1254 // Count row parity
1255 r_parity ^= id_bit;
1256 }
1257
1258 // First elements in column?
1259 if (i < 4)
1260 // Fill out first elements
1261 c_parity[i] = id_bit;
1262 else
1263 // Count column parity
1264 c_parity[i % 4] ^= id_bit;
1265
1266 // Insert ID bit
1267 id = (id << 1) | id_bit;
1268 rev_id >>= 1;
1269 }
1270
1271 // Insert parity bit of last row
1272 id = (id << 1) | r_parity;
1273
1274 // Fill out column parity at the end of tag
1275 for (i = 0; i < 4; ++i)
1276 id = (id << 1) | c_parity[i];
1277
1278 // Add stop bit
1279 id <<= 1;
1280
1281 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1282 LED_D_ON();
1283
1284 // Write EM410x ID
1285 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1286 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1287
1288 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1289 if (card) {
1290 // Clock rate is stored in bits 8-15 of the card value
1291 clock = (card & 0xFF00) >> 8;
1292 Dbprintf("Clock rate: %d", clock);
1293 switch (clock)
1294 {
1295 case 32:
1296 clock = T55x7_BITRATE_RF_32;
1297 break;
1298 case 16:
1299 clock = T55x7_BITRATE_RF_16;
1300 break;
1301 case 0:
1302 // A value of 0 is assumed to be 64 for backwards-compatibility
1303 // Fall through...
1304 case 64:
1305 clock = T55x7_BITRATE_RF_64;
1306 break;
1307 default:
1308 Dbprintf("Invalid clock rate: %d", clock);
1309 return;
1310 }
1311
1312 // Writing configuration for T55x7 tag
1313 T55xxWriteBlock(clock |
1314 T55x7_MODULATION_MANCHESTER |
1315 2 << T55x7_MAXBLOCK_SHIFT,
1316 0, 0, 0);
1317 }
1318 else
1319 // Writing configuration for T5555(Q5) tag
1320 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1321 T5555_MODULATION_MANCHESTER |
1322 2 << T5555_MAXBLOCK_SHIFT,
1323 0, 0, 0);
1324
1325 LED_D_OFF();
1326 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1327 (uint32_t)(id >> 32), (uint32_t)id);
2d4eae76 1328}
2414f978 1329
1330// Clone Indala 64-bit tag by UID to T55x7
1331void CopyIndala64toT55x7(int hi, int lo)
1332{
2414f978 1333
ae8e8a43
MHS		 1334 //Program the 2 data blocks for supplied 64bit UID
1335 // and the block 0 for Indala64 format
1336 T55xxWriteBlock(hi,1,0,0);
1337 T55xxWriteBlock(lo,2,0,0);
1338 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1339 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1340 T55x7_MODULATION_PSK1 |
1341 2 << T55x7_MAXBLOCK_SHIFT,
1342 0, 0, 0);
1343 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1344 // T5567WriteBlock(0x603E1042,0);
2414f978 1345
ae8e8a43 1346 DbpString("DONE!");
4118b74d 1347
ba1a299c 1348}
2414f978 1349
1350void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1351{
ae8e8a43 1352
ae8e8a43
MHS		 1353 //Program the 7 data blocks for supplied 224bit UID
1354 // and the block 0 for Indala224 format
1355 T55xxWriteBlock(uid1,1,0,0);
1356 T55xxWriteBlock(uid2,2,0,0);
1357 T55xxWriteBlock(uid3,3,0,0);
1358 T55xxWriteBlock(uid4,4,0,0);
1359 T55xxWriteBlock(uid5,5,0,0);
1360 T55xxWriteBlock(uid6,6,0,0);
1361 T55xxWriteBlock(uid7,7,0,0);
1362 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1363 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1364 T55x7_MODULATION_PSK1 |
1365 7 << T55x7_MAXBLOCK_SHIFT,
1366 0,0,0);
1367 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1368 // T5567WriteBlock(0x603E10E2,0);
1369
1370 DbpString("DONE!");
4118b74d 1371
2414f978 1372}
54a942b0 1373
1374
1375#define abs(x) ( ((x)<0) ? -(x) : (x) )
1376#define max(x,y) ( x<y ? y:x)
1377
1378int DemodPCF7931(uint8_t **outBlocks) {
ae8e8a43
MHS		 1379 uint8_t BitStream[256];
1380 uint8_t Blocks[8][16];
1381 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1382 int GraphTraceLen = sizeof(BigBuf);
1383 int i, j, lastval, bitidx, half_switch;
1384 int clock = 64;
1385 int tolerance = clock / 8;
1386 int pmc, block_done;
1387 int lc, warnings = 0;
1388 int num_blocks = 0;
1389 int lmin=128, lmax=128;
1390 uint8_t dir;
1391
1392 AcquireRawAdcSamples125k(0);
1393
1394 lmin = 64;
1395 lmax = 192;
1396
1397 i = 2;
1398
1399 /* Find first local max/min */
1400 if(GraphBuffer[1] > GraphBuffer[0]) {
1401 while(i < GraphTraceLen) {
1402 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1403 break;
1404 i++;
1405 }
1406 dir = 0;
54a942b0 1407 }
ae8e8a43
MHS		 1408 else {
1409 while(i < GraphTraceLen) {
1410 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1411 break;
1412 i++;
1413 }
1414 dir = 1;
54a942b0 1415 }
ae8e8a43
MHS		 1416
1417 lastval = i++;
1418 half_switch = 0;
1419 pmc = 0;
1420 block_done = 0;
1421
1422 for (bitidx = 0; i < GraphTraceLen; i++)
1423 {
1424 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1425 {
1426 lc = i - lastval;
1427 lastval = i;
1428
1429 // Switch depending on lc length:
1430 // Tolerance is 1/8 of clock rate (arbitrary)
1431 if (abs(lc-clock/4) < tolerance) {
1432 // 16T0
1433 if((i - pmc) == lc) { /* 16T0 was previous one */
1434 /* It's a PMC ! */
1435 i += (128+127+16+32+33+16)-1;
1436 lastval = i;
1437 pmc = 0;
1438 block_done = 1;
1439 }
1440 else {
1441 pmc = i;
1442 }
1443 } else if (abs(lc-clock/2) < tolerance) {
1444 // 32TO
1445 if((i - pmc) == lc) { /* 16T0 was previous one */
1446 /* It's a PMC ! */
1447 i += (128+127+16+32+33)-1;
1448 lastval = i;
1449 pmc = 0;
1450 block_done = 1;
1451 }
1452 else if(half_switch == 1) {
1453 BitStream[bitidx++] = 0;
1454 half_switch = 0;
1455 }
1456 else
1457 half_switch++;
1458 } else if (abs(lc-clock) < tolerance) {
1459 // 64TO
1460 BitStream[bitidx++] = 1;
1461 } else {
1462 // Error
1463 warnings++;
1464 if (warnings > 10)
1465 {
1466 Dbprintf("Error: too many detection errors, aborting.");
1467 return 0;
1468 }
1469 }
1470
1471 if(block_done == 1) {
1472 if(bitidx == 128) {
1473 for(j=0; j<16; j++) {
1474 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1475 64*BitStream[j*8+6]+
1476 32*BitStream[j*8+5]+
1477 16*BitStream[j*8+4]+
1478 8*BitStream[j*8+3]+
1479 4*BitStream[j*8+2]+
1480 2*BitStream[j*8+1]+
1481 BitStream[j*8];
1482 }
1483 num_blocks++;
1484 }
1485 bitidx = 0;
1486 block_done = 0;
1487 half_switch = 0;
1488 }
1489 if(i < GraphTraceLen)
1490 {
1491 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1492 else dir = 1;
1493 }
1494 }
1495 if(bitidx==255)
1496 bitidx=0;
1497 warnings = 0;
1498 if(num_blocks == 4) break;
1499 }
1500 memcpy(outBlocks, Blocks, 16*num_blocks);
1501 return num_blocks;
54a942b0 1502}
1503
1504int IsBlock0PCF7931(uint8_t *Block) {
ae8e8a43
MHS		 1505 // Assume RFU means 0 :)
1506 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1507 return 1;
1508 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1509 return 1;
1510 return 0;
54a942b0 1511}
1512
1513int IsBlock1PCF7931(uint8_t *Block) {
ae8e8a43
MHS		 1514 // Assume RFU means 0 :)
1515 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1516 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1517 return 1;
1518
1519 return 0;
54a942b0 1520}
d91a31f9 1521
54a942b0 1522#define ALLOC 16
1523
1524void ReadPCF7931() {
ae8e8a43
MHS		 1525 uint8_t Blocks[8][17];
1526 uint8_t tmpBlocks[4][16];
1527 int i, j, ind, ind2, n;
1528 int num_blocks = 0;
1529 int max_blocks = 8;
1530 int ident = 0;
1531 int error = 0;
1532 int tries = 0;
1533
1534 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1535
1536 do {
1537 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1538 n = DemodPCF7931((uint8_t**)tmpBlocks);
1539 if(!n)
1540 error++;
1541 if(error==10 && num_blocks == 0) {
1542 Dbprintf("Error, no tag or bad tag");
1543 return;
54a942b0 1544 }
ae8e8a43
MHS		 1545 else if (tries==20 || error==10) {
1546 Dbprintf("Error reading the tag");
1547 Dbprintf("Here is the partial content");
1548 goto end;
1549 }
1550
1551 for(i=0; i<n; i++)
1552 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1553 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1554 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1555 if(!ident) {
1556 for(i=0; i<n; i++) {
1557 if(IsBlock0PCF7931(tmpBlocks[i])) {
1558 // Found block 0 ?
1559 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1560 // Found block 1!
1561 // \o/
1562 ident = 1;
1563 memcpy(Blocks[0], tmpBlocks[i], 16);
1564 Blocks[0][ALLOC] = 1;
1565 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1566 Blocks[1][ALLOC] = 1;
1567 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1568 // Debug print
1569 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1570 num_blocks = 2;
1571 // Handle following blocks
1572 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1573 if(j==n) j=0;
1574 if(j==i) break;
1575 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1576 Blocks[ind2][ALLOC] = 1;
1577 }
1578 break;
1579 }
54a942b0 1580 }
ae8e8a43
MHS		 1581 }
1582 }
1583 else {
1584 for(i=0; i<n; i++) { // Look for identical block in known blocks
1585 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1586 for(j=0; j<max_blocks; j++) {
1587 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1588 // Found an identical block
1589 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1590 if(ind2 < 0)
1591 ind2 = max_blocks;
1592 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1593 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1594 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1595 Blocks[ind2][ALLOC] = 1;
1596 num_blocks++;
1597 if(num_blocks == max_blocks) goto end;
1598 }
1599 }
1600 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1601 if(ind2 > max_blocks)
1602 ind2 = 0;
1603 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1604 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1605 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1606 Blocks[ind2][ALLOC] = 1;
1607 num_blocks++;
1608 if(num_blocks == max_blocks) goto end;
1609 }
1610 }
1611 }
1612 }
54a942b0 1613 }
54a942b0 1614 }
54a942b0 1615 }
ae8e8a43
MHS		 1616 tries++;
1617 if (BUTTON_PRESS()) return;
1618 } while (num_blocks != max_blocks);
54a942b0 1619end:
ae8e8a43
MHS		 1620 Dbprintf("-----------------------------------------");
1621 Dbprintf("Memory content:");
1622 Dbprintf("-----------------------------------------");
1623 for(i=0; i<max_blocks; i++) {
1624 if(Blocks[i][ALLOC]==1)
1625 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1626 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1627 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1628 else
1629 Dbprintf("<missing block %d>", i);
1630 }
1631 Dbprintf("-----------------------------------------");
1632
1633 return ;
54a942b0 1634}
1635
1636
1637//-----------------------------------
1638// EM4469 / EM4305 routines
1639//-----------------------------------
1640#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1641#define FWD_CMD_WRITE 0xA
1642#define FWD_CMD_READ 0x9
1643#define FWD_CMD_DISABLE 0x5
1644
1645
1646uint8_t forwardLink_data[64]; //array of forwarded bits
1647uint8_t * forward_ptr; //ptr for forward message preparation
1648uint8_t fwd_bit_sz; //forwardlink bit counter
1649uint8_t * fwd_write_ptr; //forwardlink bit pointer
1650
1651//====================================================================
1652// prepares command bits
1653// see EM4469 spec
1654//====================================================================
1655//--------------------------------------------------------------------
1656uint8_t Prepare_Cmd( uint8_t cmd ) {
ae8e8a43
MHS		 1657 //--------------------------------------------------------------------
1658
1659 *forward_ptr++ = 0; //start bit
1660 *forward_ptr++ = 0; //second pause for 4050 code
1661
1662 *forward_ptr++ = cmd;
1663 cmd >>= 1;
1664 *forward_ptr++ = cmd;
1665 cmd >>= 1;
1666 *forward_ptr++ = cmd;
1667 cmd >>= 1;
1668 *forward_ptr++ = cmd;
1669
1670 return 6; //return number of emited bits
54a942b0 1671}
1672
1673//====================================================================
1674// prepares address bits
1675// see EM4469 spec
1676//====================================================================
1677
1678//--------------------------------------------------------------------
1679uint8_t Prepare_Addr( uint8_t addr ) {
ae8e8a43
MHS		 1680 //--------------------------------------------------------------------
1681
1682 register uint8_t line_parity;
1683
1684 uint8_t i;
1685 line_parity = 0;
1686 for(i=0;i<6;i++) {
1687 *forward_ptr++ = addr;
1688 line_parity ^= addr;
1689 addr >>= 1;
1690 }
1691
1692 *forward_ptr++ = (line_parity & 1);
1693
1694 return 7; //return number of emited bits
54a942b0 1695}
1696
1697//====================================================================
1698// prepares data bits intreleaved with parity bits
1699// see EM4469 spec
1700//====================================================================
1701
1702//--------------------------------------------------------------------
1703uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
ae8e8a43
MHS		 1704 //--------------------------------------------------------------------
1705
1706 register uint8_t line_parity;
1707 register uint8_t column_parity;
1708 register uint8_t i, j;
1709 register uint16_t data;
1710
1711 data = data_low;
1712 column_parity = 0;
1713
1714 for(i=0; i<4; i++) {
1715 line_parity = 0;
1716 for(j=0; j<8; j++) {
1717 line_parity ^= data;
1718 column_parity ^= (data & 1) << j;
1719 *forward_ptr++ = data;
1720 data >>= 1;
1721 }
1722 *forward_ptr++ = line_parity;
1723 if(i == 1)
1724 data = data_hi;
1725 }
1726
54a942b0 1727 for(j=0; j<8; j++) {
ae8e8a43
MHS		 1728 *forward_ptr++ = column_parity;
1729 column_parity >>= 1;
54a942b0 1730 }
ae8e8a43
MHS		 1731 *forward_ptr = 0;
1732
1733 return 45; //return number of emited bits
54a942b0 1734}
1735
1736//====================================================================
1737// Forward Link send function
1738// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1739// fwd_bit_count set with number of bits to be sent
1740//====================================================================
1741void SendForward(uint8_t fwd_bit_count) {
ae8e8a43
MHS		 1742
1743 fwd_write_ptr = forwardLink_data;
1744 fwd_bit_sz = fwd_bit_count;
1745
1746 LED_D_ON();
1747
1748 //Field on
1749 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1750 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1751 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1752
1753 // Give it a bit of time for the resonant antenna to settle.
1754 // And for the tag to fully power up
1755 SpinDelay(150);
1756
1757 // force 1st mod pulse (start gap must be longer for 4305)
1758 fwd_bit_sz--; //prepare next bit modulation
1759 fwd_write_ptr++;
1760 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1761 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1762 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1763 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1764 SpinDelayUs(16*8); //16 cycles on (8us each)
1765
1766 // now start writting
1767 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1768 if(((*fwd_write_ptr++) & 1) == 1)
1769 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1770 else {
1771 //These timings work for 4469/4269/4305 (with the 55*8 above)
1772 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1773 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1774 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1775 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1776 SpinDelayUs(9*8); //16 cycles on (8us each)
1777 }
54a942b0 1778 }
54a942b0 1779}
1780
1781void EM4xLogin(uint32_t Password) {
ae8e8a43
MHS		 1782
1783 uint8_t fwd_bit_count;
1784
1785 forward_ptr = forwardLink_data;
1786 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1787 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1788
1789 SendForward(fwd_bit_count);
1790
1791 //Wait for command to complete
1792 SpinDelay(20);
1793
54a942b0 1794}
1795
1796void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
ae8e8a43
MHS		 1797
1798 uint8_t fwd_bit_count;
1799 uint8_t *dest = (uint8_t *)BigBuf;
1800 int m=0, i=0;
1801
1802 //If password mode do login
1803 if (PwdMode == 1) EM4xLogin(Pwd);
1804
1805 forward_ptr = forwardLink_data;
1806 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1807 fwd_bit_count += Prepare_Addr( Address );
1808
1809 m = sizeof(BigBuf);
1810 // Clear destination buffer before sending the command
1811 memset(dest, 128, m);
1812 // Connect the A/D to the peak-detected low-frequency path.
1813 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1814 // Now set up the SSC to get the ADC samples that are now streaming at us.
1815 FpgaSetupSsc();
1816
1817 SendForward(fwd_bit_count);
1818
1819 // Now do the acquisition
1820 i = 0;
1821 for(;;) {
1822 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1823 AT91C_BASE_SSC->SSC_THR = 0x43;
1824 }
1825 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1826 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1827 i++;
1828 if (i >= m) break;
1829 }
54a942b0 1830 }
ae8e8a43
MHS		 1831 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1832 LED_D_OFF();
54a942b0 1833}
1834
1835void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
ae8e8a43
MHS		 1836
1837 uint8_t fwd_bit_count;
1838
1839 //If password mode do login
1840 if (PwdMode == 1) EM4xLogin(Pwd);
1841
1842 forward_ptr = forwardLink_data;
1843 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1844 fwd_bit_count += Prepare_Addr( Address );
1845 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1846
1847 SendForward(fwd_bit_count);
1848
1849 //Wait for write to complete
1850 SpinDelay(20);
1851 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1852 LED_D_OFF();
54a942b0 1853}
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