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Fix some printf/scanf format strings
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ba06a4b6 1//-----------------------------------------------------------------------------
2//
3// Jonathan Westhues, April 2006
4//-----------------------------------------------------------------------------
5
5ea2a248 6module hi_reader(
7 ck_1356meg,
ba06a4b6 8 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
9 adc_d, adc_clk,
10 ssp_frame, ssp_din, ssp_dout, ssp_clk,
ba06a4b6 11 dbg,
5ea2a248 12 subcarrier_frequency, minor_mode
ba06a4b6 13);
5ea2a248 14 input ck_1356meg;
ba06a4b6 15 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
16 input [7:0] adc_d;
17 output adc_clk;
18 input ssp_dout;
19 output ssp_frame, ssp_din, ssp_clk;
ba06a4b6 20 output dbg;
5ea2a248 21 input [1:0] subcarrier_frequency;
cd028159 22 input [3:0] minor_mode;
ba06a4b6 23
5ea2a248 24assign adc_clk = ck_1356meg; // sample frequency is 13,56 MHz
ba06a4b6 25
ba06a4b6 26// When we're a reader, we just need to do the BPSK demod; but when we're an
27// eavesdropper, we also need to pick out the commands sent by the reader,
28// using AM. Do this the same way that we do it for the simulated tag.
51d4f6f1 29reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
ba06a4b6 30reg [11:0] has_been_low_for;
31always @(negedge adc_clk)
32begin
7a537397 33 if (& adc_d[7:0]) after_hysteresis <= 1'b1;
34 else if (~(| adc_d[7:0])) after_hysteresis <= 1'b0;
ba06a4b6 35
7a537397 36 if (after_hysteresis)
ba06a4b6 37 begin
7a537397 38 has_been_low_for <= 12'd0;
ba06a4b6 39 end
40 else
41 begin
7a537397 42 if (has_been_low_for == 12'd4095)
ba06a4b6 43 begin
44 has_been_low_for <= 12'd0;
45 after_hysteresis <= 1'b1;
46 end
47 else
48 has_been_low_for <= has_been_low_for + 1;
49 end
50end
51
315e18e6 52
53// Let us report a correlation every 64 samples. I.e.
54// one Q/I pair after 4 subcarrier cycles for the 848kHz subcarrier,
55// one Q/I pair after 2 subcarrier cycles for the 424kHz subcarriers,
56// one Q/I pair for each subcarrier cyle for the 212kHz subcarrier.
57// We need a 6-bit counter for the timing.
ba06a4b6 58reg [5:0] corr_i_cnt;
315e18e6 59always @(negedge adc_clk)
60begin
61 corr_i_cnt <= corr_i_cnt + 1;
62end
63
5ea2a248 64
65// A couple of registers in which to accumulate the correlations. From the 64 samples
315e18e6 66// we would add at most 32 times the difference between unmodulated and modulated signal. It should
d372569b 67// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
68// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
315e18e6 69// Temporary we might need more bits. For the 212kHz subcarrier we could possible add 32 times the
70// maximum signal value before a first subtraction would occur. 32 * 255 = 8160 can be held in 13 bits.
71// Add one bit for sign -> need 14 bit registers but final result will fit into 12 bits.
72reg signed [13:0] corr_i_accum;
73reg signed [13:0] corr_q_accum;
d372569b 74// we will report maximum 8 significant bits
ba06a4b6 75reg signed [7:0] corr_i_out;
76reg signed [7:0] corr_q_out;
d9de20fa 77
d9de20fa 78
79// the amplitude of the subcarrier is sqrt(ci^2 + cq^2).
80// approximate by amplitude = max(|ci|,|cq|) + 1/2*min(|ci|,|cq|)
5ea2a248 81reg [13:0] corr_amplitude, abs_ci, abs_cq, max_ci_cq;
82reg [12:0] min_ci_cq_2; // min_ci_cq / 2
d9de20fa 83
5ea2a248 84always @(*)
d9de20fa 85begin
86 if (corr_i_accum[13] == 1'b0)
87 abs_ci <= corr_i_accum;
88 else
89 abs_ci <= -corr_i_accum;
90
91 if (corr_q_accum[13] == 1'b0)
92 abs_cq <= corr_q_accum;
93 else
94 abs_cq <= -corr_q_accum;
95
96 if (abs_ci > abs_cq)
97 begin
98 max_ci_cq <= abs_ci;
5ea2a248 99 min_ci_cq_2 <= abs_cq / 2;
d9de20fa 100 end
101 else
102 begin
103 max_ci_cq <= abs_cq;
5ea2a248 104 min_ci_cq_2 <= abs_ci / 2;
d9de20fa 105 end
106
5ea2a248 107 corr_amplitude <= max_ci_cq + min_ci_cq_2;
d9de20fa 108
109end
110
111
315e18e6 112// The subcarrier reference signals
113reg subcarrier_I;
114reg subcarrier_Q;
ba06a4b6 115
5ea2a248 116always @(*)
315e18e6 117begin
5ea2a248 118 if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
315e18e6 119 begin
120 subcarrier_I = ~corr_i_cnt[3];
121 subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
122 end
5ea2a248 123 else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
315e18e6 124 begin
125 subcarrier_I = ~corr_i_cnt[5];
126 subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
127 end
128 else
129 begin // 424 kHz
130 subcarrier_I = ~corr_i_cnt[4];
131 subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
132 end
133end
d9de20fa 134
135
ba06a4b6 136// ADC data appears on the rising edge, so sample it on the falling edge
137always @(negedge adc_clk)
138begin
139 // These are the correlators: we correlate against in-phase and quadrature
d9de20fa 140 // versions of our reference signal, and keep the (signed) results or the
141 // resulting amplitude to send out later over the SSP.
be09ea86 142 if (corr_i_cnt == 6'd0)
ba06a4b6 143 begin
5ea2a248 144 if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE)
ba06a4b6 145 begin
5ea2a248 146 // send amplitude plus 2 bits reader signal
147 corr_i_out <= corr_amplitude[13:6];
148 corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
149 end
150 else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
151 begin
152 // Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
153 if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
154 corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
155 else // truncate to maximum value
156 if (corr_i_accum[13] == 1'b0)
157 corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
158 else
159 corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
160 // Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
161 if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
162 corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
163 else // truncate to maximum value
164 if (corr_q_accum[13] == 1'b0)
165 corr_q_out <= {7'b0111111, after_hysteresis_prev};
166 else
167 corr_q_out <= {7'b1000000, after_hysteresis_prev};
168 end
169 else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE)
ba06a4b6 170 begin
5ea2a248 171 // send amplitude
172 corr_i_out <= {2'b00, corr_amplitude[13:8]};
173 corr_q_out <= corr_amplitude[7:0];
174 end
175 else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
176 begin
177 // Send 8 bits of in phase tag signal
178 if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
179 corr_i_out <= corr_i_accum[11:4];
180 else // truncate to maximum value
181 if (corr_i_accum[13] == 1'b0)
182 corr_i_out <= 8'b01111111;
183 else
184 corr_i_out <= 8'b10000000;
185 // Send 8 bits of quadrature phase tag signal
186 if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
187 corr_q_out <= corr_q_accum[11:4];
188 else // truncate to maximum value
189 if (corr_q_accum[13] == 1'b0)
190 corr_q_out <= 8'b01111111;
191 else
192 corr_q_out <= 8'b10000000;
193 end
d9de20fa 194
195 // for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
196 after_hysteresis_prev_prev <= after_hysteresis;
315e18e6 197 // Initialize next correlation.
198 // Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate.
199 corr_i_accum <= $signed({1'b0,adc_d});
200 corr_q_accum <= $signed({1'b0,adc_d});
ba06a4b6 201 end
202 else
203 begin
315e18e6 204 if (subcarrier_I)
205 corr_i_accum <= corr_i_accum + $signed({1'b0,adc_d});
ba06a4b6 206 else
315e18e6 207 corr_i_accum <= corr_i_accum - $signed({1'b0,adc_d});
ba06a4b6 208
315e18e6 209 if (subcarrier_Q)
210 corr_q_accum <= corr_q_accum + $signed({1'b0,adc_d});
51d4f6f1 211 else
315e18e6 212 corr_q_accum <= corr_q_accum - $signed({1'b0,adc_d});
ba06a4b6 213 end
214
d9de20fa 215 // for each Q/I pair report two reader signal samples when sniffing. Store the 2nd.
be09ea86 216 if (corr_i_cnt == 6'd32)
ba06a4b6 217 after_hysteresis_prev <= after_hysteresis;
218
219 // Then the result from last time is serialized and send out to the ARM.
220 // We get one report each cycle, and each report is 16 bits, so the
d9de20fa 221 // ssp_clk should be the adc_clk divided by 64/16 = 4.
222 // ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
ba06a4b6 223
be09ea86 224 if (corr_i_cnt[1:0] == 2'b00)
ba06a4b6 225 begin
ba06a4b6 226 // Don't shift if we just loaded new data, obviously.
be09ea86 227 if (corr_i_cnt != 6'd0)
ba06a4b6 228 begin
229 corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
230 corr_q_out[7:1] <= corr_q_out[6:0];
231 end
232 end
233
5ea2a248 234end
235
236
237// ssp clock and frame signal for communication to and from ARM
7a537397 238// _____ _____ _____ _
239// ssp_clk | |_____| |_____| |_____|
240// _____
241// ssp_frame ___| |____________________________
242// ___________ ___________ ___________ _
243// ssp_d_in X___________X___________X___________X_
244//
245// corr_i_cnt 0 1 2 3 4 5 6 7 8 9 10 11 12 ...
246//
247
5ea2a248 248reg ssp_clk;
249reg ssp_frame;
ba06a4b6 250
5ea2a248 251always @(negedge adc_clk)
252begin
253 if (corr_i_cnt[1:0] == 2'b00)
254 ssp_clk <= 1'b1;
255 if (corr_i_cnt[1:0] == 2'b10)
256 ssp_clk <= 1'b0;
257
258 // set ssp_frame signal for corr_i_cnt = 1..3
259 // (send one frame with 16 Bits)
c41dd5f9 260 if (corr_i_cnt == 6'd1)
5ea2a248 261 ssp_frame <= 1'b1;
7a537397 262 if (corr_i_cnt == 6'd3)
5ea2a248 263 ssp_frame <= 1'b0;
ba06a4b6 264end
265
5ea2a248 266
ba06a4b6 267assign ssp_din = corr_i_out[7];
268
5ea2a248 269
cd028159 270// a jamming signal
271reg jam_signal;
272reg [3:0] jam_counter;
273
274always @(negedge adc_clk)
275begin
276 if (corr_i_cnt == 6'd0)
277 begin
278 jam_counter <= jam_counter + 1;
279 jam_signal <= jam_counter[1] ^ jam_counter[3];
280 end
281end
282
5ea2a248 283// Antenna drivers
284reg pwr_hi, pwr_oe4;
285
286always @(*)
287begin
288 if (minor_mode == `FPGA_HF_READER_MODE_SEND_SHALLOW_MOD)
289 begin
290 pwr_hi = ck_1356meg;
291 pwr_oe4 = ssp_dout;
292 end
293 else if (minor_mode == `FPGA_HF_READER_MODE_SEND_FULL_MOD)
294 begin
295 pwr_hi = ck_1356meg & ~ssp_dout;
296 pwr_oe4 = 1'b0;
297 end
cd028159 298 else if (minor_mode == `FPGA_HF_READER_MODE_SEND_JAM)
299 begin
300 pwr_hi = ck_1356meg & jam_signal;
301 pwr_oe4 = 1'b0;
302 end
5ea2a248 303 else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ
304 || minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE
305 || minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE)
cd028159 306 begin // all off
5ea2a248 307 pwr_hi = 1'b0;
308 pwr_oe4 = 1'b0;
309 end
310 else // receiving from tag
311 begin
312 pwr_hi = ck_1356meg;
313 pwr_oe4 = 1'b0;
314 end
cd028159 315end
5ea2a248 316
317// always on
318assign pwr_oe1 = 1'b0;
319assign pwr_oe3 = 1'b0;
320
321// Unused.
322assign pwr_lo = 1'b0;
323assign pwr_oe2 = 1'b0;
324
325// Debug Output
ba06a4b6 326assign dbg = corr_i_cnt[3];
327
ba06a4b6 328endmodule
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