[proxmark3-svn] / armsrc / util.c

//-----------------------------------------------------------------------------
// Jonathan Westhues, Sept 2005
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Utility functions used in many places, not specific to any piece of code.
//-----------------------------------------------------------------------------

#include "util.h"

void print_result(char *name, uint8_t *buf, size_t len) {
	uint8_t *p = buf;

	if ( len % 16 == 0 ) {
		for(; p-buf < len; p += 16)
			Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
				name,
				p-buf,
				len,
				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
			);
	}
	else {
		for(; p-buf < len; p += 8)
			Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x",
				name,
				p-buf,
				len,
				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
	}
}

size_t nbytes(size_t nbits) {
	return (nbits >> 3)+((nbits % 8) > 0);
}

uint32_t SwapBits(uint32_t value, int nrbits) {
	uint32_t newvalue = 0;
	for(int i = 0; i < nrbits; i++) {
		newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
	}
	return newvalue;
}

/*
 ref  http://www.csm.ornl.gov/~dunigan/crc.html
 Returns the value v with the bottom b [0,32] bits reflected. 
 Example: reflect(0x3e23L,3) == 0x3e26
*/
uint32_t reflect(uint32_t v, int b) {
	uint32_t t = v;
	for ( int i = 0; i < b; ++i) {
		if (t & 1)
			v |=  BITMASK((b-1)-i);
		else
			v &= ~BITMASK((b-1)-i);
		t>>=1;
	}
	return v;
}

void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) {
	while (len--) {
		dest[len] = (uint8_t) n;
		n >>= 8;
	}
}

uint64_t bytes_to_num(uint8_t* src, size_t len) {
	uint64_t num = 0;
	while (len--) {
		num = (num << 8) | (*src);
		src++;
	}
	return num;
}

// RotateLeft - Ultralight, Desfire
void rol(uint8_t *data, const size_t len) {
    uint8_t first = data[0];
    for (size_t i = 0; i < len-1; i++) {
        data[i] = data[i+1];
    }
    data[len-1] = first;
}

void lsl (uint8_t *data, size_t len) {
    for (size_t n = 0; n < len - 1; n++) {
        data[n] = (data[n] << 1) | (data[n+1] >> 7);
    }
    data[len - 1] <<= 1;
}

int32_t le24toh (uint8_t data[3]) {
    return (data[2] << 16) | (data[1] << 8) | data[0];
}

void LEDsoff() {
	LED_A_OFF();
	LED_B_OFF();
	LED_C_OFF();
	LED_D_OFF();
}

// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
void LED(int led, int ms) {
	if (led & LED_RED)
		LED_C_ON();
	if (led & LED_ORANGE)
		LED_A_ON();
	if (led & LED_GREEN)
		LED_B_ON();
	if (led & LED_RED2)
		LED_D_ON();

	if (!ms)
		return;

	SpinDelay(ms);

	if (led & LED_RED)
		LED_C_OFF();
	if (led & LED_ORANGE)
		LED_A_OFF();
	if (led & LED_GREEN)
		LED_B_OFF();
	if (led & LED_RED2)
		LED_D_OFF();
}

// Determine if a button is double clicked, single clicked,
// not clicked, or held down (for ms || 1sec)
// In general, don't use this function unless you expect a
// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
int BUTTON_CLICKED(int ms) {
	// Up to 500ms in between clicks to mean a double click
	int ticks = (48000 * (ms ? ms : 1000)) >> 10;

	// If we're not even pressed, forget about it!
	if (!BUTTON_PRESS())
		return BUTTON_NO_CLICK;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	int letoff = 0;
	for(;;)
	{
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

		// We haven't let off the button yet
		if (!letoff)
		{
			// We just let it off!
			if (!BUTTON_PRESS())
			{
				letoff = 1;

				// reset our timer for 500ms
				start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
				ticks = (48000 * (500)) >> 10;
			}

			// Still haven't let it off
			else
				// Have we held down a full second?
				if (now == (uint16_t)(start + ticks))
					return BUTTON_HOLD;
		}

		// We already let off, did we click again?
		else
			// Sweet, double click!
			if (BUTTON_PRESS())
				return BUTTON_DOUBLE_CLICK;

			// Have we ran out of time to double click?
			else
				if (now == (uint16_t)(start + ticks))
					// At least we did a single click
					return BUTTON_SINGLE_CLICK;

		WDT_HIT();
	}

	// We should never get here
	return BUTTON_ERROR;
}

// Determine if a button is held down
int BUTTON_HELD(int ms) {
	// If button is held for one second
	int ticks = (48000 * (ms ? ms : 1000)) >> 10;

	// If we're not even pressed, forget about it!
	if (!BUTTON_PRESS())
		return BUTTON_NO_CLICK;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	for(;;)
	{
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

		// As soon as our button let go, we didn't hold long enough
		if (!BUTTON_PRESS())
			return BUTTON_SINGLE_CLICK;

		// Have we waited the full second?
		else
			if (now == (uint16_t)(start + ticks))
				return BUTTON_HOLD;

		WDT_HIT();
	}

	// We should never get here
	return BUTTON_ERROR;
}

// attempt at high resolution microsecond timer
// beware: timer counts in 21.3uS increments (1024/48Mhz)
void SpinDelayUs(int us) {
	int ticks = (48*us) >> 10;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	for(;;) {
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
		if (now == (uint16_t)(start + ticks))
			return;

		WDT_HIT();
	}
}

void SpinDelay(int ms) {
  // convert to uS and call microsecond delay function
	SpinDelayUs(ms*1000);
}

/* Similar to FpgaGatherVersion this formats stored version information
 * into a string representation. It takes a pointer to the struct version_information,
 * verifies the magic properties, then stores a formatted string, prefixed by
 * prefix in dst.
 */
void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information) {
	struct version_information *v = (struct version_information*)version_information;
	dst[0] = 0;
	strncat(dst, prefix, len-1);
	if(v->magic != VERSION_INFORMATION_MAGIC) {
		strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);
		return;
	}
	if(v->versionversion != 1) {
		strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);
		return;
	}
	if(!v->present) {
		strncat(dst, "Version information not available\n", len - strlen(dst) - 1);
		return;
	}

	strncat(dst, v->gitversion, len - strlen(dst) - 1);
	if(v->clean == 0) {
		strncat(dst, "-unclean", len - strlen(dst) - 1);
	} else if(v->clean == 2) {
		strncat(dst, "-suspect", len - strlen(dst) - 1);
	}

	strncat(dst, " ", len - strlen(dst) - 1);
	strncat(dst, v->buildtime, len - strlen(dst) - 1);
	strncat(dst, "\n", len - strlen(dst) - 1);
}

//  -------------------------------------------------------------------------
//  timer lib
//  -------------------------------------------------------------------------
//  test procedure:
//
//	ti = GetTickCount();
//	SpinDelay(1000);
//	ti = GetTickCount() - ti;
//	Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());

void StartTickCount() {
	// This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
	// We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
    uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;		// = 16 * main clock frequency (16MHz) / slow clock frequency
	// set RealTimeCounter divider to count at 1kHz:
	AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
	// note: worst case precision is approx 2.5%
}

/*
* Get the current count.
*/
uint32_t RAMFUNC GetTickCount(){
	return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
}

//  -------------------------------------------------------------------------
//  microseconds timer 
//  -------------------------------------------------------------------------
void StartCountUS() {
	AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
//	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;

	// fast clock
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
								AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
								AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
	AT91C_BASE_TC0->TC_RA = 1;
	AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
	
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
	
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
	AT91C_BASE_TCB->TCB_BCR = 1;
	}

uint32_t RAMFUNC GetCountUS(){
	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
	//  By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
}

// static uint32_t GlobalUsCounter = 0;

// uint32_t RAMFUNC GetDeltaCountUS(){
	// uint32_t g_cnt = GetCountUS();
	// uint32_t g_res = g_cnt - GlobalUsCounter;
	// GlobalUsCounter = g_cnt;
	// return g_res;
// }


//  -------------------------------------------------------------------------
//  Timer for iso14443 commands. Uses ssp_clk from FPGA 
//  -------------------------------------------------------------------------
void StartCountSspClk() {
	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 		// XC0 Clock = TIOA1
							| AT91C_TCB_TC1XC1S_NONE 		// XC1 Clock = none
							| AT91C_TCB_TC2XC2S_TIOA0;		// XC2 Clock = TIOA0

	// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; 				// disable TC1
	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
							| AT91C_TC_CPCSTOP				// Stop clock on RC compare
							| AT91C_TC_EEVTEDG_RISING		// Trigger on rising edge of Event
							| AT91C_TC_EEVT_TIOB			// Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
							| AT91C_TC_ENETRG				// Enable external trigger event
							| AT91C_TC_WAVESEL_UP	 		// Upmode without automatic trigger on RC compare
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_AEEVT_SET 			// Set TIOA1 on external event
							| AT91C_TC_ACPC_CLEAR; 			// Clear TIOA1 on RC Compare
	AT91C_BASE_TC1->TC_RC = 0x04; 							// RC Compare value = 0x04

	// use TC0 to count TIOA1 pulses
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;				// disable TC0
	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0	 			// TC0 clock = XC0 clock = TIOA1
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_WAVESEL_UP	 		// just count
							| AT91C_TC_ACPA_CLEAR 			// Clear TIOA0 on RA Compare
							| AT91C_TC_ACPC_SET; 			// Set TIOA0 on RC Compare
	AT91C_BASE_TC0->TC_RA = 1;								// RA Compare value = 1; pulse width to TC2
	AT91C_BASE_TC0->TC_RC = 0; 								// RC Compare value = 0; increment TC2 on overflow

	// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; 				// disable TC2  
	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2	 			// TC2 clock = XC2 clock = TIOA0
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_WAVESEL_UP;	 		// just count

	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;				// enable TC0
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;				// enable TC1
	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;				// enable TC2

	// synchronize the counter with the ssp_frame signal. 
	// Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present 
	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); 	// wait for ssp_frame to go high (start of frame)
	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); 		// wait for ssp_frame to be low
	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); 	// wait for ssp_clk to go high

	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
	AT91C_BASE_TCB->TCB_BCR = 1;							// assert Sync (set all timers to 0 on next active clock edge)
	// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
	// (just started with the transfer of the 4th Bit).

	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. 
	// Therefore need to wait quite some time before we can use the counter.
	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
}

uint32_t RAMFUNC GetCountSspClk(){
	uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
	if ((tmp_count & 0x0000ffff) == 0)  //small chance that we may have missed an increment in TC2
		return (AT91C_BASE_TC2->TC_CV << 16);
	return tmp_count;
}
Commit	Line	Data
e30c654b	1	//-----------------------------------------------------------------------------
e30c654b	2	// Jonathan Westhues, Sept 2005
bd20f8f4	3	//
	4	// This code is licensed to you under the terms of the GNU GPL, version 2 or,
	5	// at your option, any later version. See the LICENSE.txt file for the text of
	6	// the license.
	7	//-----------------------------------------------------------------------------
	8	// Utility functions used in many places, not specific to any piece of code.
e30c654b	9	//-----------------------------------------------------------------------------
bd20f8f4	10
f7e3ed82	11	#include "util.h"
e30c654b	12
f38a1528	13	void print_result(char name, uint8_t buf, size_t len) {
41863885	14	uint8_t *p = buf;
f38a1528	15
41863885	16	if ( len % 16 == 0 ) {
	17	for(; p-buf < len; p += 16)
	18	Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
f38a1528	19	name,
	20	p-buf,
	21	len,
	22	p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
41863885	23	);
	24	}
	25	else {
	26	for(; p-buf < len; p += 8)
	27	Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x",
	28	name,
	29	p-buf,
	30	len,
	31	p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
	32	}
f38a1528	33	}
f38a1528	34
195af472	35	size_t nbytes(size_t nbits) {
665775c8	36	return (nbits >> 3)+((nbits % 8) > 0);
195af472	37	}
195af472	38
81cd0474	39	uint32_t SwapBits(uint32_t value, int nrbits) {
81cd0474	40	uint32_t newvalue = 0;
5192a0a6	41	for(int i = 0; i < nrbits; i++) {
81cd0474	42	newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
	43	}
	44	return newvalue;
	45	}
	46
ab3af4fe	47	/*
	48	ref http://www.csm.ornl.gov/~dunigan/crc.html
	49	Returns the value v with the bottom b [0,32] bits reflected.
	50	Example: reflect(0x3e23L,3) == 0x3e26
	51	*/
	52	uint32_t reflect(uint32_t v, int b) {
	53	uint32_t t = v;
	54	for ( int i = 0; i < b; ++i) {
	55	if (t & 1)
	56	v \|= BITMASK((b-1)-i);
	57	else
	58	v &= ~BITMASK((b-1)-i);
	59	t>>=1;
	60	}
	61	return v;
	62	}
	63
41863885	64	void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) {
e30c654b	65	while (len--) {
f7e3ed82	66	dest[len] = (uint8_t) n;
e30c654b	67	n >>= 8;
	68	}
	69	}
	70
41863885	71	uint64_t bytes_to_num(uint8_t* src, size_t len) {
e30c654b	72	uint64_t num = 0;
2abdfa49	73	while (len--) {
e30c654b	74	num = (num << 8) \| (*src);
	75	src++;
	76	}
	77	return num;
	78	}
	79
f38a1528	80	// RotateLeft - Ultralight, Desfire
41863885	81	void rol(uint8_t *data, const size_t len) {
f38a1528	82	uint8_t first = data[0];
	83	for (size_t i = 0; i < len-1; i++) {
	84	data[i] = data[i+1];
	85	}
	86	data[len-1] = first;
	87	}
dd79e03a	88
f38a1528	89	void lsl (uint8_t *data, size_t len) {
	90	for (size_t n = 0; n < len - 1; n++) {
	91	data[n] = (data[n] << 1) \| (data[n+1] >> 7);
	92	}
	93	data[len - 1] <<= 1;
	94	}
	95
ab3af4fe	96	int32_t le24toh (uint8_t data[3]) {
f38a1528	97	return (data[2] << 16) \| (data[1] << 8) \| data[0];
	98	}
	99
ab3af4fe	100	void LEDsoff() {
e30c654b	101	LED_A_OFF();
	102	LED_B_OFF();
	103	LED_C_OFF();
	104	LED_D_OFF();
	105	}
	106
	107	// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
ab3af4fe	108	void LED(int led, int ms) {
e30c654b	109	if (led & LED_RED)
	110	LED_C_ON();
	111	if (led & LED_ORANGE)
	112	LED_A_ON();
	113	if (led & LED_GREEN)
	114	LED_B_ON();
	115	if (led & LED_RED2)
	116	LED_D_ON();
	117
	118	if (!ms)
	119	return;
	120
	121	SpinDelay(ms);
	122
	123	if (led & LED_RED)
	124	LED_C_OFF();
	125	if (led & LED_ORANGE)
	126	LED_A_OFF();
	127	if (led & LED_GREEN)
	128	LED_B_OFF();
	129	if (led & LED_RED2)
	130	LED_D_OFF();
	131	}
	132
e30c654b	133	// Determine if a button is double clicked, single clicked,
	134	// not clicked, or held down (for ms \|\| 1sec)
	135	// In general, don't use this function unless you expect a
	136	// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
ab3af4fe	137	int BUTTON_CLICKED(int ms) {
e30c654b	138	// Up to 500ms in between clicks to mean a double click
	139	int ticks = (48000 * (ms ? ms : 1000)) >> 10;
	140
	141	// If we're not even pressed, forget about it!
	142	if (!BUTTON_PRESS())
	143	return BUTTON_NO_CLICK;
	144
	145	// Borrow a PWM unit for my real-time clock
	146	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	147	// 48 MHz / 1024 gives 46.875 kHz
	148	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	149	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	150	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
	151
f7e3ed82	152	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	153
	154	int letoff = 0;
	155	for(;;)
	156	{
f7e3ed82	157	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	158
	159	// We haven't let off the button yet
	160	if (!letoff)
	161	{
	162	// We just let it off!
	163	if (!BUTTON_PRESS())
	164	{
	165	letoff = 1;
	166
	167	// reset our timer for 500ms
	168	start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
	169	ticks = (48000 * (500)) >> 10;
	170	}
	171
	172	// Still haven't let it off
	173	else
	174	// Have we held down a full second?
f7e3ed82	175	if (now == (uint16_t)(start + ticks))
e30c654b	176	return BUTTON_HOLD;
	177	}
	178
	179	// We already let off, did we click again?
	180	else
	181	// Sweet, double click!
	182	if (BUTTON_PRESS())
	183	return BUTTON_DOUBLE_CLICK;
	184
	185	// Have we ran out of time to double click?
	186	else
f7e3ed82	187	if (now == (uint16_t)(start + ticks))
e30c654b	188	// At least we did a single click
	189	return BUTTON_SINGLE_CLICK;
	190
	191	WDT_HIT();
	192	}
	193
	194	// We should never get here
	195	return BUTTON_ERROR;
	196	}
	197
	198	// Determine if a button is held down
ab3af4fe	199	int BUTTON_HELD(int ms) {
e30c654b	200	// If button is held for one second
	201	int ticks = (48000 * (ms ? ms : 1000)) >> 10;
	202
	203	// If we're not even pressed, forget about it!
	204	if (!BUTTON_PRESS())
	205	return BUTTON_NO_CLICK;
	206
	207	// Borrow a PWM unit for my real-time clock
	208	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	209	// 48 MHz / 1024 gives 46.875 kHz
	210	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	211	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	212	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
	213
f7e3ed82	214	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	215
	216	for(;;)
	217	{
f7e3ed82	218	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	219
	220	// As soon as our button let go, we didn't hold long enough
	221	if (!BUTTON_PRESS())
	222	return BUTTON_SINGLE_CLICK;
	223
	224	// Have we waited the full second?
	225	else
f7e3ed82	226	if (now == (uint16_t)(start + ticks))
e30c654b	227	return BUTTON_HOLD;
	228
	229	WDT_HIT();
	230	}
	231
	232	// We should never get here
	233	return BUTTON_ERROR;
	234	}
	235
	236	// attempt at high resolution microsecond timer
	237	// beware: timer counts in 21.3uS increments (1024/48Mhz)
ab3af4fe	238	void SpinDelayUs(int us) {
e30c654b	239	int ticks = (48*us) >> 10;
	240
	241	// Borrow a PWM unit for my real-time clock
	242	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	243	// 48 MHz / 1024 gives 46.875 kHz
	244	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	245	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	246	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
	247
f7e3ed82	248	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	249
e30c654b	250	for(;;) {
f7e3ed82	251	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
f7e3ed82	252	if (now == (uint16_t)(start + ticks))
e30c654b	253	return;
	254
	255	WDT_HIT();
	256	}
	257	}
	258
ab3af4fe	259	void SpinDelay(int ms) {
e30c654b	260	// convert to uS and call microsecond delay function
	261	SpinDelayUs(ms*1000);
	262	}
	263
	264	/* Similar to FpgaGatherVersion this formats stored version information
	265	* into a string representation. It takes a pointer to the struct version_information,
	266	* verifies the magic properties, then stores a formatted string, prefixed by
	267	* prefix in dst.
	268	*/
ab3af4fe	269	void FormatVersionInformation(char dst, int len, const char prefix, void *version_information) {
e30c654b	270	struct version_information v = (struct version_information)version_information;
e30c654b	271	dst[0] = 0;
a61b4976	272	strncat(dst, prefix, len-1);
e30c654b	273	if(v->magic != VERSION_INFORMATION_MAGIC) {
9783989b	274	strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);
e30c654b	275	return;
	276	}
	277	if(v->versionversion != 1) {
9783989b	278	strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);
e30c654b	279	return;
	280	}
	281	if(!v->present) {
9783989b	282	strncat(dst, "Version information not available\n", len - strlen(dst) - 1);
e30c654b	283	return;
	284	}
	285
cba867f2	286	strncat(dst, v->gitversion, len - strlen(dst) - 1);
e30c654b	287	if(v->clean == 0) {
cba867f2	288	strncat(dst, "-unclean", len - strlen(dst) - 1);
e30c654b	289	} else if(v->clean == 2) {
cba867f2	290	strncat(dst, "-suspect", len - strlen(dst) - 1);
e30c654b	291	}
e30c654b	292
cba867f2 MHS	293	strncat(dst, " ", len - strlen(dst) - 1);
cba867f2 MHS	294	strncat(dst, v->buildtime, len - strlen(dst) - 1);
9783989b	295	strncat(dst, "\n", len - strlen(dst) - 1);
e30c654b	296	}
9ca155ba M	297
	298	// -------------------------------------------------------------------------
	299	// timer lib
	300	// -------------------------------------------------------------------------
	301	// test procedure:
	302	//
	303	// ti = GetTickCount();
	304	// SpinDelay(1000);
	305	// ti = GetTickCount() - ti;
	306	// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
	307
ab3af4fe	308	void StartTickCount() {
f62b5e12	309	// This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
	310	// We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
	311	uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency
	312	// set RealTimeCounter divider to count at 1kHz:
	313	AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST \| ((256000 + (mainf/2)) / mainf);
	314	// note: worst case precision is approx 2.5%
9ca155ba M	315	}
	316
	317	/*
	318	* Get the current count.
	319	*/
	320	uint32_t RAMFUNC GetTickCount(){
8f51ddb0	321	return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
9ca155ba M	322	}
9ca155ba M	323
8f51ddb0 M	324	// -------------------------------------------------------------------------
	325	// microseconds timer
	326	// -------------------------------------------------------------------------
ab3af4fe	327	void StartCountUS() {
8f51ddb0 M	328	AT91C_BASE_PMC->PMC_PCER \|= (0x1 << 12) \| (0x1 << 13) \| (0x1 << 14);
	329	// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
	330	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE \| AT91C_TCB_TC1XC1S_TIOA0 \| AT91C_TCB_TC2XC2S_NONE;
	331
	332	// fast clock
	333	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	334	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK \| // MCK(48MHz)/32 -- tick=1.5mks
aaa1a9a2	335	AT91C_TC_WAVE \| AT91C_TC_WAVESEL_UP_AUTO \| AT91C_TC_ACPA_CLEAR \|
aaa1a9a2	336	AT91C_TC_ACPC_SET \| AT91C_TC_ASWTRG_SET;
8f51ddb0 M	337	AT91C_BASE_TC0->TC_RA = 1;
	338	AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
	339
	340	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	341	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
1c611bbd	342
8f51ddb0 M	343	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
	344	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
	345	AT91C_BASE_TCB->TCB_BCR = 1;
1c611bbd	346	}
8f51ddb0 M	347
8f51ddb0 M	348	uint32_t RAMFUNC GetCountUS(){
0de8e387	349	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
0de8e387	350	// By suggestion from PwPiwi, http://www.proxmark.org/forum/viewtopic.php?pid=17548#p17548
41863885	351	//return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3);
41863885	352	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3);
8f51ddb0 M	353	}
8f51ddb0 M	354
41863885	355	// static uint32_t GlobalUsCounter = 0;
8f51ddb0	356
41863885	357	// uint32_t RAMFUNC GetDeltaCountUS(){
	358	// uint32_t g_cnt = GetCountUS();
	359	// uint32_t g_res = g_cnt - GlobalUsCounter;
	360	// GlobalUsCounter = g_cnt;
	361	// return g_res;
	362	// }
8f51ddb0 M	363
8f51ddb0 M	364
1c611bbd	365	// -------------------------------------------------------------------------
7bc95e2e	366	// Timer for iso14443 commands. Uses ssp_clk from FPGA
1c611bbd	367	// -------------------------------------------------------------------------
ab3af4fe	368	void StartCountSspClk() {
1c611bbd	369	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) \| (1 << AT91C_ID_TC1) \| (1 << AT91C_ID_TC2); // Enable Clock to all timers
	370	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
	371	\| AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
	372	\| AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
	373
	374	// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
	375	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
	376	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
	377	\| AT91C_TC_CPCSTOP // Stop clock on RC compare
	378	\| AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
7bc95e2e	379	\| AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
1c611bbd	380	\| AT91C_TC_ENETRG // Enable external trigger event
	381	\| AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
	382	\| AT91C_TC_WAVE // Waveform Mode
	383	\| AT91C_TC_AEEVT_SET // Set TIOA1 on external event
	384	\| AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
	385	AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
	386
	387	// use TC0 to count TIOA1 pulses
7bc95e2e	388	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
1c611bbd	389	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
	390	\| AT91C_TC_WAVE // Waveform Mode
	391	\| AT91C_TC_WAVESEL_UP // just count
	392	\| AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
	393	\| AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
	394	AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
	395	AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
	396
	397	// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
	398	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
	399	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
	400	\| AT91C_TC_WAVE // Waveform Mode
	401	\| AT91C_TC_WAVESEL_UP; // just count
88e20c9f	402
1c611bbd	403	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
	404	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
	405	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
9492e0b0	406
88e20c9f	407	// synchronize the counter with the ssp_frame signal.
88e20c9f	408	// Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present
7bc95e2e	409	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
9492e0b0	410	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
7bc95e2e	411	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
88e20c9f	412
7bc95e2e	413	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
7bc95e2e	414	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
1c611bbd	415	AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
7bc95e2e	416	// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
	417	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
	418	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
	419	// (just started with the transfer of the 4th Bit).
88e20c9f	420
	421	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows.
	422	// Therefore need to wait quite some time before we can use the counter.
7bc95e2e	423	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
1c611bbd	424	}
1c611bbd	425
7bc95e2e	426	uint32_t RAMFUNC GetCountSspClk(){
5192a0a6	427	uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) \| AT91C_BASE_TC0->TC_CV;
5192a0a6	428	if ((tmp_count & 0x0000ffff) == 0) //small chance that we may have missed an increment in TC2
1c611bbd	429	return (AT91C_BASE_TC2->TC_CV << 16);
5192a0a6	430	return tmp_count;
1c611bbd	431	}
7bc95e2e	432