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CHG: some magic generation1 tags is not following protocol and answers to the "halt...
[proxmark3-svn] / fpga / hi_sniffer.v
CommitLineData
1d0ccbe0 1
2module hi_sniffer(
3 pck0, ck_1356meg, ck_1356megb,
4 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
5 adc_d, adc_clk,
6 ssp_frame, ssp_din, ssp_dout, ssp_clk,
7 cross_hi, cross_lo,
8 dbg,
9 xcorr_is_848, snoop, xcorr_quarter_freq // not used.
10);
11 input pck0, ck_1356meg, ck_1356megb;
12 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
13 input [7:0] adc_d;
14 output adc_clk;
15 input ssp_dout;
16 output ssp_frame, ssp_din, ssp_clk;
17 input cross_hi, cross_lo;
18 output dbg;
19 input xcorr_is_848, snoop, xcorr_quarter_freq; // not used.
20
21// We are only snooping, all off.
22assign pwr_hi = 1'b0;// ck_1356megb & (~snoop);
23assign pwr_oe1 = 1'b0;
24assign pwr_oe2 = 1'b0;
25assign pwr_oe3 = 1'b0;
26assign pwr_oe4 = 1'b0;
27
28reg ssp_clk = 1'b0;
29reg ssp_frame;
30reg adc_clk;
31reg [7:0] adc_d_out = 8'd0;
32reg [7:0] ssp_cnt = 8'd0;
33reg [7:0] pck_divider = 8'd0;
34reg ant_lo = 1'b0;
35reg bit_to_send = 1'b0;
36
37always @(ck_1356meg, pck0) // should synthetisize to a mux..
38 begin
39 adc_clk = ck_1356meg;
40 ssp_clk = ~ck_1356meg;
41 end
42
43reg [7:0] cnt_test = 8'd0; // test
44
45always @(posedge pck0)
46begin
47 ant_lo <= 1'b0;
48end
49
50always @(posedge ssp_clk) // ~1356 (hf)
51begin
52 if(ssp_cnt[7:0] == 8'd255) // SSP counter for divides.
53 ssp_cnt[7:0] <= 8'd0;
54 else
55 ssp_cnt <= ssp_cnt + 1;
56
57 if((ssp_cnt[2:0] == 3'b000) && !ant_lo) // To set frame length
58 begin
59 adc_d_out[7:0] = adc_d; // disable for test
60 bit_to_send = adc_d_out[0];
61 ssp_frame <= 1'b1;
62 end
63 else
64 begin
65 adc_d_out[6:0] = adc_d_out[7:1];
66 adc_d_out[7] = 1'b0; // according to old lf_read.v comment prevents gliches if not set.
67 bit_to_send = adc_d_out[0];
68 ssp_frame <= 1'b0;
69 end
70end
71
72assign ssp_din = bit_to_send && !ant_lo;//bit_to_send && !ant_lo; // && .. not needed i guess?
73
74assign pwr_lo = ant_lo;
75
76
77endmodule
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