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ADD: a new pwdgen algo Nicknamed C, (Huge props to @Bettse for everything) also...
[proxmark3-svn] / armsrc / iclass.c
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cee5a30d 1//-----------------------------------------------------------------------------
2// Gerhard de Koning Gans - May 2008
3// Hagen Fritsch - June 2010
4// Gerhard de Koning Gans - May 2011
1e262141 5// Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation
cee5a30d 6//
7// This code is licensed to you under the terms of the GNU GPL, version 2 or,
8// at your option, any later version. See the LICENSE.txt file for the text of
9// the license.
10//-----------------------------------------------------------------------------
11// Routines to support iClass.
12//-----------------------------------------------------------------------------
13// Based on ISO14443a implementation. Still in experimental phase.
14// Contribution made during a security research at Radboud University Nijmegen
15//
16// Please feel free to contribute and extend iClass support!!
17//-----------------------------------------------------------------------------
18//
cee5a30d 19// FIX:
20// ====
21// We still have sometimes a demodulation error when snooping iClass communication.
22// The resulting trace of a read-block-03 command may look something like this:
23//
24// + 22279: : 0c 03 e8 01
25//
26// ...with an incorrect answer...
27//
28// + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
29//
30// We still left the error signalling bytes in the traces like 0xbb
31//
32// A correct trace should look like this:
33//
34// + 21112: : 0c 03 e8 01
35// + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
36//
37//-----------------------------------------------------------------------------
38
99cf19d9 39#include "proxmark3.h"
cee5a30d 40#include "apps.h"
41#include "util.h"
42#include "string.h"
7e67e42f 43#include "common.h"
f38a1528 44#include "cmd.h"
1e262141 45// Needed for CRC in emulation mode;
46// same construction as in ISO 14443;
47// different initial value (CRC_ICLASS)
99cf19d9 48#include "iso14443crc.h"
49#include "iso15693tools.h"
b67f7ec3 50#include "protocols.h"
10a8875c 51#include "optimized_cipher.h"
cee5a30d 52
1e262141 53static int timeout = 4096;
cee5a30d 54
cee5a30d 55
1e262141 56static int SendIClassAnswer(uint8_t *resp, int respLen, int delay);
cee5a30d 57
58//-----------------------------------------------------------------------------
59// The software UART that receives commands from the reader, and its state
60// variables.
61//-----------------------------------------------------------------------------
62static struct {
63 enum {
64 STATE_UNSYNCD,
65 STATE_START_OF_COMMUNICATION,
66 STATE_RECEIVING
67 } state;
68 uint16_t shiftReg;
69 int bitCnt;
70 int byteCnt;
71 int byteCntMax;
72 int posCnt;
73 int nOutOfCnt;
74 int OutOfCnt;
75 int syncBit;
1e262141 76 int samples;
cee5a30d 77 int highCnt;
78 int swapper;
79 int counter;
80 int bitBuffer;
81 int dropPosition;
a501c82b 82 uint8_t *output;
cee5a30d 83} Uart;
84
1e262141 85static RAMFUNC int OutOfNDecoding(int bit)
cee5a30d 86{
9f693930 87 //int error = 0;
cee5a30d 88 int bitright;
89
90 if(!Uart.bitBuffer) {
91 Uart.bitBuffer = bit ^ 0xFF0;
92 return FALSE;
93 }
94 else {
95 Uart.bitBuffer <<= 4;
96 Uart.bitBuffer ^= bit;
97 }
98
99 /*if(Uart.swapper) {
100 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
101 Uart.byteCnt++;
102 Uart.swapper = 0;
103 if(Uart.byteCnt > 15) { return TRUE; }
104 }
105 else {
106 Uart.swapper = 1;
107 }*/
108
109 if(Uart.state != STATE_UNSYNCD) {
110 Uart.posCnt++;
111
112 if((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {
113 bit = 0x00;
114 }
115 else {
116 bit = 0x01;
117 }
118 if(((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {
119 bitright = 0x00;
120 }
121 else {
122 bitright = 0x01;
123 }
124 if(bit != bitright) { bit = bitright; }
125
126
127 // So, now we only have to deal with *bit*, lets see...
128 if(Uart.posCnt == 1) {
129 // measurement first half bitperiod
130 if(!bit) {
131 // Drop in first half means that we are either seeing
132 // an SOF or an EOF.
133
134 if(Uart.nOutOfCnt == 1) {
135 // End of Communication
136 Uart.state = STATE_UNSYNCD;
137 Uart.highCnt = 0;
138 if(Uart.byteCnt == 0) {
139 // Its not straightforward to show single EOFs
140 // So just leave it and do not return TRUE
a501c82b 141 Uart.output[0] = 0xf0;
cee5a30d 142 Uart.byteCnt++;
cee5a30d 143 }
144 else {
145 return TRUE;
146 }
147 }
148 else if(Uart.state != STATE_START_OF_COMMUNICATION) {
149 // When not part of SOF or EOF, it is an error
150 Uart.state = STATE_UNSYNCD;
151 Uart.highCnt = 0;
9f693930 152 //error = 4;
cee5a30d 153 }
154 }
155 }
156 else {
157 // measurement second half bitperiod
158 // Count the bitslot we are in... (ISO 15693)
159 Uart.nOutOfCnt++;
160
161 if(!bit) {
162 if(Uart.dropPosition) {
163 if(Uart.state == STATE_START_OF_COMMUNICATION) {
9f693930 164 //error = 1;
cee5a30d 165 }
166 else {
9f693930 167 //error = 7;
cee5a30d 168 }
169 // It is an error if we already have seen a drop in current frame
170 Uart.state = STATE_UNSYNCD;
171 Uart.highCnt = 0;
172 }
173 else {
174 Uart.dropPosition = Uart.nOutOfCnt;
175 }
176 }
177
178 Uart.posCnt = 0;
179
180
181 if(Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) {
182 Uart.nOutOfCnt = 0;
183
184 if(Uart.state == STATE_START_OF_COMMUNICATION) {
185 if(Uart.dropPosition == 4) {
186 Uart.state = STATE_RECEIVING;
187 Uart.OutOfCnt = 256;
188 }
189 else if(Uart.dropPosition == 3) {
190 Uart.state = STATE_RECEIVING;
191 Uart.OutOfCnt = 4;
192 //Uart.output[Uart.byteCnt] = 0xdd;
193 //Uart.byteCnt++;
194 }
195 else {
196 Uart.state = STATE_UNSYNCD;
197 Uart.highCnt = 0;
198 }
199 Uart.dropPosition = 0;
200 }
201 else {
202 // RECEIVING DATA
203 // 1 out of 4
204 if(!Uart.dropPosition) {
205 Uart.state = STATE_UNSYNCD;
206 Uart.highCnt = 0;
9f693930 207 //error = 9;
cee5a30d 208 }
209 else {
210 Uart.shiftReg >>= 2;
211
212 // Swap bit order
213 Uart.dropPosition--;
214 //if(Uart.dropPosition == 1) { Uart.dropPosition = 2; }
215 //else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; }
216
217 Uart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6);
218 Uart.bitCnt += 2;
219 Uart.dropPosition = 0;
220
221 if(Uart.bitCnt == 8) {
222 Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);
223 Uart.byteCnt++;
cee5a30d 224 Uart.bitCnt = 0;
225 Uart.shiftReg = 0;
226 }
227 }
228 }
229 }
230 else if(Uart.nOutOfCnt == Uart.OutOfCnt) {
231 // RECEIVING DATA
232 // 1 out of 256
233 if(!Uart.dropPosition) {
234 Uart.state = STATE_UNSYNCD;
235 Uart.highCnt = 0;
9f693930 236 //error = 3;
cee5a30d 237 }
238 else {
239 Uart.dropPosition--;
240 Uart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff);
241 Uart.byteCnt++;
cee5a30d 242 Uart.bitCnt = 0;
243 Uart.shiftReg = 0;
244 Uart.nOutOfCnt = 0;
245 Uart.dropPosition = 0;
246 }
247 }
248
249 /*if(error) {
250 Uart.output[Uart.byteCnt] = 0xAA;
251 Uart.byteCnt++;
252 Uart.output[Uart.byteCnt] = error & 0xFF;
253 Uart.byteCnt++;
254 Uart.output[Uart.byteCnt] = 0xAA;
255 Uart.byteCnt++;
256 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
257 Uart.byteCnt++;
258 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
259 Uart.byteCnt++;
260 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
261 Uart.byteCnt++;
262 Uart.output[Uart.byteCnt] = 0xAA;
263 Uart.byteCnt++;
264 return TRUE;
265 }*/
266 }
267
268 }
269 else {
270 bit = Uart.bitBuffer & 0xf0;
271 bit >>= 4;
272 bit ^= 0x0F; // drops become 1s ;-)
273 if(bit) {
274 // should have been high or at least (4 * 128) / fc
275 // according to ISO this should be at least (9 * 128 + 20) / fc
276 if(Uart.highCnt == 8) {
277 // we went low, so this could be start of communication
278 // it turns out to be safer to choose a less significant
279 // syncbit... so we check whether the neighbour also represents the drop
280 Uart.posCnt = 1; // apparently we are busy with our first half bit period
281 Uart.syncBit = bit & 8;
282 Uart.samples = 3;
283 if(!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; }
284 else if(bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }
285 if(!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; }
286 else if(bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }
287 if(!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0;
288 if(Uart.syncBit && (Uart.bitBuffer & 8)) {
289 Uart.syncBit = 8;
290
291 // the first half bit period is expected in next sample
292 Uart.posCnt = 0;
293 Uart.samples = 3;
294 }
295 }
296 else if(bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; }
297
298 Uart.syncBit <<= 4;
299 Uart.state = STATE_START_OF_COMMUNICATION;
300 Uart.bitCnt = 0;
301 Uart.byteCnt = 0;
cee5a30d 302 Uart.nOutOfCnt = 0;
303 Uart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256
304 Uart.dropPosition = 0;
305 Uart.shiftReg = 0;
9f693930 306 //error = 0;
cee5a30d 307 }
308 else {
309 Uart.highCnt = 0;
310 }
311 }
312 else {
313 if(Uart.highCnt < 8) {
314 Uart.highCnt++;
315 }
316 }
317 }
318
319 return FALSE;
320}
321
322//=============================================================================
1e262141 323// Manchester
cee5a30d 324//=============================================================================
325
326static struct {
327 enum {
328 DEMOD_UNSYNCD,
329 DEMOD_START_OF_COMMUNICATION,
330 DEMOD_START_OF_COMMUNICATION2,
331 DEMOD_START_OF_COMMUNICATION3,
332 DEMOD_SOF_COMPLETE,
333 DEMOD_MANCHESTER_D,
334 DEMOD_MANCHESTER_E,
335 DEMOD_END_OF_COMMUNICATION,
336 DEMOD_END_OF_COMMUNICATION2,
337 DEMOD_MANCHESTER_F,
338 DEMOD_ERROR_WAIT
339 } state;
340 int bitCount;
341 int posCount;
342 int syncBit;
cee5a30d 343 uint16_t shiftReg;
344 int buffer;
345 int buffer2;
346 int buffer3;
347 int buff;
348 int samples;
349 int len;
350 enum {
351 SUB_NONE,
352 SUB_FIRST_HALF,
353 SUB_SECOND_HALF,
354 SUB_BOTH
355 } sub;
356 uint8_t *output;
357} Demod;
358
359static RAMFUNC int ManchesterDecoding(int v)
360{
361 int bit;
362 int modulation;
363 int error = 0;
364
365 bit = Demod.buffer;
366 Demod.buffer = Demod.buffer2;
367 Demod.buffer2 = Demod.buffer3;
368 Demod.buffer3 = v;
369
370 if(Demod.buff < 3) {
371 Demod.buff++;
372 return FALSE;
373 }
374
375 if(Demod.state==DEMOD_UNSYNCD) {
376 Demod.output[Demod.len] = 0xfa;
377 Demod.syncBit = 0;
378 //Demod.samples = 0;
379 Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part
cee5a30d 380
381 if(bit & 0x08) {
382 Demod.syncBit = 0x08;
383 }
384
385 if(bit & 0x04) {
386 if(Demod.syncBit) {
387 bit <<= 4;
388 }
389 Demod.syncBit = 0x04;
390 }
391
392 if(bit & 0x02) {
393 if(Demod.syncBit) {
394 bit <<= 2;
395 }
396 Demod.syncBit = 0x02;
397 }
398
399 if(bit & 0x01 && Demod.syncBit) {
400 Demod.syncBit = 0x01;
401 }
402
403 if(Demod.syncBit) {
404 Demod.len = 0;
405 Demod.state = DEMOD_START_OF_COMMUNICATION;
406 Demod.sub = SUB_FIRST_HALF;
407 Demod.bitCount = 0;
408 Demod.shiftReg = 0;
cee5a30d 409 Demod.samples = 0;
410 if(Demod.posCount) {
411 //if(trigger) LED_A_OFF(); // Not useful in this case...
412 switch(Demod.syncBit) {
413 case 0x08: Demod.samples = 3; break;
414 case 0x04: Demod.samples = 2; break;
415 case 0x02: Demod.samples = 1; break;
416 case 0x01: Demod.samples = 0; break;
417 }
418 // SOF must be long burst... otherwise stay unsynced!!!
419 if(!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) {
420 Demod.state = DEMOD_UNSYNCD;
421 }
422 }
423 else {
424 // SOF must be long burst... otherwise stay unsynced!!!
425 if(!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) {
426 Demod.state = DEMOD_UNSYNCD;
427 error = 0x88;
428 }
429
430 }
431 error = 0;
432
433 }
434 }
435 else {
436 modulation = bit & Demod.syncBit;
437 modulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
cee5a30d 438
439 Demod.samples += 4;
440
441 if(Demod.posCount==0) {
442 Demod.posCount = 1;
443 if(modulation) {
444 Demod.sub = SUB_FIRST_HALF;
445 }
446 else {
447 Demod.sub = SUB_NONE;
448 }
449 }
450 else {
451 Demod.posCount = 0;
452 /*(modulation && (Demod.sub == SUB_FIRST_HALF)) {
453 if(Demod.state!=DEMOD_ERROR_WAIT) {
454 Demod.state = DEMOD_ERROR_WAIT;
455 Demod.output[Demod.len] = 0xaa;
456 error = 0x01;
457 }
458 }*/
459 //else if(modulation) {
460 if(modulation) {
461 if(Demod.sub == SUB_FIRST_HALF) {
462 Demod.sub = SUB_BOTH;
463 }
464 else {
465 Demod.sub = SUB_SECOND_HALF;
466 }
467 }
468 else if(Demod.sub == SUB_NONE) {
469 if(Demod.state == DEMOD_SOF_COMPLETE) {
470 Demod.output[Demod.len] = 0x0f;
471 Demod.len++;
cee5a30d 472 Demod.state = DEMOD_UNSYNCD;
473// error = 0x0f;
474 return TRUE;
475 }
476 else {
477 Demod.state = DEMOD_ERROR_WAIT;
478 error = 0x33;
479 }
480 /*if(Demod.state!=DEMOD_ERROR_WAIT) {
481 Demod.state = DEMOD_ERROR_WAIT;
482 Demod.output[Demod.len] = 0xaa;
483 error = 0x01;
484 }*/
485 }
486
487 switch(Demod.state) {
488 case DEMOD_START_OF_COMMUNICATION:
489 if(Demod.sub == SUB_BOTH) {
490 //Demod.state = DEMOD_MANCHESTER_D;
491 Demod.state = DEMOD_START_OF_COMMUNICATION2;
492 Demod.posCount = 1;
493 Demod.sub = SUB_NONE;
494 }
495 else {
496 Demod.output[Demod.len] = 0xab;
497 Demod.state = DEMOD_ERROR_WAIT;
498 error = 0xd2;
499 }
500 break;
501 case DEMOD_START_OF_COMMUNICATION2:
502 if(Demod.sub == SUB_SECOND_HALF) {
503 Demod.state = DEMOD_START_OF_COMMUNICATION3;
504 }
505 else {
506 Demod.output[Demod.len] = 0xab;
507 Demod.state = DEMOD_ERROR_WAIT;
508 error = 0xd3;
509 }
510 break;
511 case DEMOD_START_OF_COMMUNICATION3:
512 if(Demod.sub == SUB_SECOND_HALF) {
513// Demod.state = DEMOD_MANCHESTER_D;
514 Demod.state = DEMOD_SOF_COMPLETE;
515 //Demod.output[Demod.len] = Demod.syncBit & 0xFF;
516 //Demod.len++;
517 }
518 else {
519 Demod.output[Demod.len] = 0xab;
520 Demod.state = DEMOD_ERROR_WAIT;
521 error = 0xd4;
522 }
523 break;
524 case DEMOD_SOF_COMPLETE:
525 case DEMOD_MANCHESTER_D:
526 case DEMOD_MANCHESTER_E:
527 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
528 // 00001111 = 1 (0 in 14443)
529 if(Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF
530 Demod.bitCount++;
531 Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;
532 Demod.state = DEMOD_MANCHESTER_D;
533 }
534 else if(Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF
535 Demod.bitCount++;
536 Demod.shiftReg >>= 1;
537 Demod.state = DEMOD_MANCHESTER_E;
538 }
539 else if(Demod.sub == SUB_BOTH) {
540 Demod.state = DEMOD_MANCHESTER_F;
541 }
542 else {
543 Demod.state = DEMOD_ERROR_WAIT;
544 error = 0x55;
545 }
546 break;
547
548 case DEMOD_MANCHESTER_F:
549 // Tag response does not need to be a complete byte!
550 if(Demod.len > 0 || Demod.bitCount > 0) {
551 if(Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF
f5ed4d12 552 Demod.shiftReg >>= (9 - Demod.bitCount); // right align data
cee5a30d 553 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
554 Demod.len++;
cee5a30d 555 }
556
557 Demod.state = DEMOD_UNSYNCD;
558 return TRUE;
559 }
560 else {
561 Demod.output[Demod.len] = 0xad;
562 Demod.state = DEMOD_ERROR_WAIT;
563 error = 0x03;
564 }
565 break;
566
567 case DEMOD_ERROR_WAIT:
568 Demod.state = DEMOD_UNSYNCD;
569 break;
570
571 default:
572 Demod.output[Demod.len] = 0xdd;
573 Demod.state = DEMOD_UNSYNCD;
574 break;
575 }
576
577 /*if(Demod.bitCount>=9) {
578 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
579 Demod.len++;
580
581 Demod.parityBits <<= 1;
582 Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);
583
584 Demod.bitCount = 0;
585 Demod.shiftReg = 0;
586 }*/
587 if(Demod.bitCount>=8) {
588 Demod.shiftReg >>= 1;
589 Demod.output[Demod.len] = (Demod.shiftReg & 0xff);
590 Demod.len++;
cee5a30d 591 Demod.bitCount = 0;
592 Demod.shiftReg = 0;
593 }
594
595 if(error) {
596 Demod.output[Demod.len] = 0xBB;
597 Demod.len++;
598 Demod.output[Demod.len] = error & 0xFF;
599 Demod.len++;
600 Demod.output[Demod.len] = 0xBB;
601 Demod.len++;
602 Demod.output[Demod.len] = bit & 0xFF;
603 Demod.len++;
604 Demod.output[Demod.len] = Demod.buffer & 0xFF;
605 Demod.len++;
606 // Look harder ;-)
607 Demod.output[Demod.len] = Demod.buffer2 & 0xFF;
608 Demod.len++;
609 Demod.output[Demod.len] = Demod.syncBit & 0xFF;
610 Demod.len++;
611 Demod.output[Demod.len] = 0xBB;
612 Demod.len++;
613 return TRUE;
614 }
615
616 }
617
618 } // end (state != UNSYNCED)
619
620 return FALSE;
621}
622
623//=============================================================================
1e262141 624// Finally, a `sniffer' for iClass communication
cee5a30d 625// Both sides of communication!
626//=============================================================================
627
628//-----------------------------------------------------------------------------
629// Record the sequence of commands sent by the reader to the tag, with
630// triggering so that we start recording at the point that the tag is moved
631// near the reader.
632//-----------------------------------------------------------------------------
633void RAMFUNC SnoopIClass(void)
634{
99cf19d9 635
636
cee5a30d 637 // We won't start recording the frames that we acquire until we trigger;
638 // a good trigger condition to get started is probably when we see a
639 // response from the tag.
9f693930 640 //int triggered = FALSE; // FALSE to wait first for card
cee5a30d 641
642 // The command (reader -> tag) that we're receiving.
643 // The length of a received command will in most cases be no more than 18 bytes.
644 // So 32 should be enough!
f71f4deb 645 #define ICLASS_BUFFER_SIZE 32
646 uint8_t readerToTagCmd[ICLASS_BUFFER_SIZE];
cee5a30d 647 // The response (tag -> reader) that we're receiving.
f71f4deb 648 uint8_t tagToReaderResponse[ICLASS_BUFFER_SIZE];
6a1f2d82 649
7cc204bf 650 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
651
f71f4deb 652 // free all BigBuf memory
653 BigBuf_free();
654 // The DMA buffer, used to stream samples from the FPGA
655 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
656
3000dc4e
MHS		 657 set_tracing(TRUE);
658 clear_trace();
1e262141 659 iso14a_set_trigger(FALSE);
cee5a30d 660
cee5a30d 661 int lastRxCounter;
117d9ec2 662 uint8_t *upTo;
cee5a30d 663 int smpl;
664 int maxBehindBy = 0;
665
666 // Count of samples received so far, so that we can include timing
667 // information in the trace buffer.
668 int samples = 0;
669 rsamples = 0;
670
cee5a30d 671 // Set up the demodulator for tag -> reader responses.
17cba269 672 Demod.output = tagToReaderResponse;
cee5a30d 673 Demod.len = 0;
674 Demod.state = DEMOD_UNSYNCD;
675
676 // Setup for the DMA.
677 FpgaSetupSsc();
678 upTo = dmaBuf;
679 lastRxCounter = DMA_BUFFER_SIZE;
680 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
681
682 // And the reader -> tag commands
683 memset(&Uart, 0, sizeof(Uart));
17cba269 684 Uart.output = readerToTagCmd;
cee5a30d 685 Uart.byteCntMax = 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
686 Uart.state = STATE_UNSYNCD;
687
688 // And put the FPGA in the appropriate mode
689 // Signal field is off with the appropriate LED
690 LED_D_OFF();
691 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);
692 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
693
81012e67 694 uint32_t time_0 = GetCountSspClk();
55eaed8f
MHS		 695 uint32_t time_start = 0;
696 uint32_t time_stop = 0;
81012e67 697
cee5a30d 698 int div = 0;
699 //int div2 = 0;
700 int decbyte = 0;
701 int decbyter = 0;
702
703 // And now we loop, receiving samples.
704 for(;;) {
705 LED_A_ON();
706 WDT_HIT();
707 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
708 (DMA_BUFFER_SIZE-1);
709 if(behindBy > maxBehindBy) {
710 maxBehindBy = behindBy;
f71f4deb 711 if(behindBy > (9 * DMA_BUFFER_SIZE / 10)) {
cee5a30d 712 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy);
713 goto done;
714 }
715 }
716 if(behindBy < 1) continue;
717
718 LED_A_OFF();
719 smpl = upTo[0];
720 upTo++;
721 lastRxCounter -= 1;
722 if(upTo - dmaBuf > DMA_BUFFER_SIZE) {
723 upTo -= DMA_BUFFER_SIZE;
724 lastRxCounter += DMA_BUFFER_SIZE;
725 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
726 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
727 }
728
729 //samples += 4;
730 samples += 1;
cee5a30d 731
cee5a30d 732 if(smpl & 0xF) {
733 decbyte ^= (1 << (3 - div));
734 }
cee5a30d 735
736 // FOR READER SIDE COMMUMICATION...
17cba269 737
cee5a30d 738 decbyter <<= 2;
739 decbyter ^= (smpl & 0x30);
740
741 div++;
742
743 if((div + 1) % 2 == 0) {
744 smpl = decbyter;
1e262141 745 if(OutOfNDecoding((smpl & 0xF0) >> 4)) {
cee5a30d 746 rsamples = samples - Uart.samples;
55eaed8f 747 time_stop = (GetCountSspClk()-time_0) << 4;
cee5a30d 748 LED_C_ON();
17cba269 749
81012e67 750 //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,TRUE)) break;
17cba269 751 //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
6a1f2d82 752 if(tracing) {
a501c82b 753 uint8_t parity[MAX_PARITY_SIZE];
754 GetParity(Uart.output, Uart.byteCnt, parity);
55eaed8f 755 LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, TRUE);
81012e67
MHS		 756 }
757
17cba269
MHS		 758
759 /* And ready to receive another command. */
cee5a30d 760 Uart.state = STATE_UNSYNCD;
761 /* And also reset the demod code, which might have been */
762 /* false-triggered by the commands from the reader. */
763 Demod.state = DEMOD_UNSYNCD;
764 LED_B_OFF();
765 Uart.byteCnt = 0;
55eaed8f
MHS		 766 }else{
767 time_start = (GetCountSspClk()-time_0) << 4;
cee5a30d 768 }
769 decbyter = 0;
770 }
771
772 if(div > 3) {
773 smpl = decbyte;
774 if(ManchesterDecoding(smpl & 0x0F)) {
55eaed8f
MHS		 775 time_stop = (GetCountSspClk()-time_0) << 4;
776
cee5a30d 777 rsamples = samples - Demod.samples;
778 LED_B_ON();
779
6a1f2d82 780 if(tracing) {
a501c82b 781 uint8_t parity[MAX_PARITY_SIZE];
782 GetParity(Demod.output, Demod.len, parity);
55eaed8f 783 LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, FALSE);
81012e67 784 }
17cba269 785
cee5a30d 786 // And ready to receive another response.
787 memset(&Demod, 0, sizeof(Demod));
17cba269 788 Demod.output = tagToReaderResponse;
cee5a30d 789 Demod.state = DEMOD_UNSYNCD;
790 LED_C_OFF();
55eaed8f
MHS		 791 }else{
792 time_start = (GetCountSspClk()-time_0) << 4;
cee5a30d 793 }
794
795 div = 0;
796 decbyte = 0x00;
797 }
798 //}
799
800 if(BUTTON_PRESS()) {
801 DbpString("cancelled_a");
802 goto done;
803 }
804 }
805
806 DbpString("COMMAND FINISHED");
807
808 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
3000dc4e 809 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
cee5a30d 810
811done:
812 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
813 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
3000dc4e 814 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
cee5a30d 815 LED_A_OFF();
816 LED_B_OFF();
1e262141 817 LED_C_OFF();
818 LED_D_OFF();
5ee53a0e 819 set_tracing(FALSE);
1e262141 820}
821
912a3e94 822void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
823 int i;
824 for(i = 0; i < 8; i++) {
825 rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);
1e262141 826 }
827}
828
829//-----------------------------------------------------------------------------
830// Wait for commands from reader
831// Stop when button is pressed
832// Or return TRUE when command is captured
833//-----------------------------------------------------------------------------
834static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
835{
912a3e94 836 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1e262141 837 // only, since we are receiving, not transmitting).
838 // Signal field is off with the appropriate LED
839 LED_D_OFF();
840 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
841
842 // Now run a `software UART' on the stream of incoming samples.
843 Uart.output = received;
844 Uart.byteCntMax = maxLen;
845 Uart.state = STATE_UNSYNCD;
846
847 for(;;) {
848 WDT_HIT();
849
850 if(BUTTON_PRESS()) return FALSE;
851
852 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
853 AT91C_BASE_SSC->SSC_THR = 0x00;
854 }
855 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
856 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
95e63594 857
1e262141 858 if(OutOfNDecoding(b & 0x0f)) {
859 *len = Uart.byteCnt;
860 return TRUE;
861 }
862 }
863 }
864}
865
645c960f
MHS		 866static uint8_t encode4Bits(const uint8_t b)
867{
868 uint8_t c = b & 0xF;
869 // OTA, the least significant bits first
870 // The columns are
871 // 1 - Bit value to send
872 // 2 - Reversed (big-endian)
873 // 3 - Encoded
874 // 4 - Hex values
875
876 switch(c){
877 // 1 2 3 4
878 case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
879 case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
880 case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
881 case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
882 case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
883 case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
884 case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
885 case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
886 case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
887 case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
888 case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
889 case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
890 case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
891 case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
892 case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
893 default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
894
895 }
896}
1e262141 897
898//-----------------------------------------------------------------------------
899// Prepare tag messages
900//-----------------------------------------------------------------------------
901static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
902{
645c960f
MHS		 903
904 /*
905 * SOF comprises 3 parts;
906 * * An unmodulated time of 56.64 us
907 * * 24 pulses of 423.75 KHz (fc/32)
908 * * A logic 1, which starts with an unmodulated time of 18.88us
909 * followed by 8 pulses of 423.75kHz (fc/32)
910 *
911 *
912 * EOF comprises 3 parts:
913 * - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
914 * time of 18.88us.
915 * - 24 pulses of fc/32
916 * - An unmodulated time of 56.64 us
917 *
918 *
919 * A logic 0 starts with 8 pulses of fc/32
920 * followed by an unmodulated time of 256/fc (~18,88us).
921 *
922 * A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
923 * 8 pulses of fc/32 (also 18.88us)
924 *
925 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
926 * works like this.
927 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
928 * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
929 *
6b038d19 930 * In this mode the SOF can be written as 00011101 = 0x1D
645c960f
MHS		 931 * The EOF can be written as 10111000 = 0xb8
932 * A logic 1 is 01
933 * A logic 0 is 10
934 *
935 * */
936
1e262141 937 int i;
938
939 ToSendReset();
940
941 // Send SOF
645c960f 942 ToSend[++ToSendMax] = 0x1D;
1e262141 943
944 for(i = 0; i < len; i++) {
1e262141 945 uint8_t b = cmd[i];
645c960f
MHS		 946 ToSend[++ToSendMax] = encode4Bits(b & 0xF); //Least significant half
947 ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF);//Most significant half
1e262141 948 }
1e262141 949
950 // Send EOF
645c960f 951 ToSend[++ToSendMax] = 0xB8;
81012e67 952 //lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
1e262141 953 // Convert from last byte pos to length
954 ToSendMax++;
955}
956
957// Only SOF
958static void CodeIClassTagSOF()
959{
81012e67
MHS		 960 //So far a dummy implementation, not used
961 //int lastProxToAirDuration =0;
1e262141 962
81012e67 963 ToSendReset();
1e262141 964 // Send SOF
645c960f 965 ToSend[++ToSendMax] = 0x1D;
81012e67
MHS		 966// lastProxToAirDuration = 8*ToSendMax - 3*8;//Not counting zeroes in the beginning
967
1e262141 968 // Convert from last byte pos to length
969 ToSendMax++;
970}
b67f7ec3
MHS		 971#define MODE_SIM_CSN 0
972#define MODE_EXIT_AFTER_MAC 1
973#define MODE_FULLSIM 2
55eaed8f 974
b67f7ec3 975int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf);
ff7bb4ef
MHS		 976/**
977 * @brief SimulateIClass simulates an iClass card.
978 * @param arg0 type of simulation
979 * - 0 uses the first 8 bytes in usb data as CSN
980 * - 2 "dismantling iclass"-attack. This mode iterates through all CSN's specified
981 * in the usb data. This mode collects MAC from the reader, in order to do an offline
982 * attack on the keys. For more info, see "dismantling iclass" and proxclone.com.
983 * - Other : Uses the default CSN (031fec8af7ff12e0)
984 * @param arg1 - number of CSN's contained in datain (applicable for mode 2 only)
985 * @param arg2
986 * @param datain
987 */
988void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain)
1e262141 989{
ff7bb4ef
MHS		 990 uint32_t simType = arg0;
991 uint32_t numberOfCSNS = arg1;
7cc204bf 992 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1e262141 993
ff7bb4ef 994 // Enable and clear the trace
3000dc4e
MHS		 995 set_tracing(TRUE);
996 clear_trace();
b67f7ec3
MHS		 997 //Use the emulator memory for SIM
998 uint8_t *emulator = BigBuf_get_EM_addr();
81cd0474 999
ff7bb4ef
MHS		 1000 if(simType == 0) {
1001 // Use the CSN from commandline
b67f7ec3
MHS		 1002 memcpy(emulator, datain, 8);
1003 doIClassSimulation(MODE_SIM_CSN,NULL);
ff7bb4ef
MHS		 1004 }else if(simType == 1)
1005 {
b67f7ec3
MHS		 1006 //Default CSN
1007 uint8_t csn_crc[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };
1008 // Use the CSN from commandline
1009 memcpy(emulator, csn_crc, 8);
1010 doIClassSimulation(MODE_SIM_CSN,NULL);
ff7bb4ef
MHS		 1011 }
1012 else if(simType == 2)
1013 {
9f6e9d15 1014
7b941c8d 1015 uint8_t mac_responses[USB_CMD_DATA_SIZE] = { 0 };
a501c82b 1016 Dbprintf("Going into attack mode, %d CSNS sent", numberOfCSNS);
ff7bb4ef
MHS		 1017 // In this mode, a number of csns are within datain. We'll simulate each one, one at a time
1018 // in order to collect MAC's from the reader. This can later be used in an offlne-attack
1019 // in order to obtain the keys, as in the "dismantling iclass"-paper.
9f6e9d15
MHS		 1020 int i = 0;
1021 for( ; i < numberOfCSNS && i*8+8 < USB_CMD_DATA_SIZE; i++)
ff7bb4ef
MHS		 1022 {
1023 // The usb data is 512 bytes, fitting 65 8-byte CSNs in there.
1024
b67f7ec3
MHS		 1025 memcpy(emulator, datain+(i*8), 8);
1026 if(doIClassSimulation(MODE_EXIT_AFTER_MAC,mac_responses+i*8))
f83cc126 1027 {
645c960f 1028 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
f83cc126
MHS		 1029 return; // Button pressed
1030 }
ff7bb4ef 1031 }
9f6e9d15
MHS		 1032 cmd_send(CMD_ACK,CMD_SIMULATE_TAG_ICLASS,i,0,mac_responses,i*8);
1033
b67f7ec3
MHS		 1034 }else if(simType == 3){
1035 //This is 'full sim' mode, where we use the emulator storage for data.
1036 doIClassSimulation(MODE_FULLSIM, NULL);
81012e67
MHS		 1037 }
1038 else{
ff7bb4ef
MHS		 1039 // We may want a mode here where we hardcode the csns to use (from proxclone).
1040 // That will speed things up a little, but not required just yet.
1041 Dbprintf("The mode is not implemented, reserved for future use");
1042 }
9f6e9d15 1043 Dbprintf("Done...");
5ee53a0e 1044 set_tracing(FALSE);
ff7bb4ef 1045}
c8387e85
MHS		 1046void AppendCrc(uint8_t* data, int len)
1047{
1048 ComputeCrc14443(CRC_ICLASS,data,len,data+len,data+len+1);
1049}
b67f7ec3 1050
ff7bb4ef
MHS		 1051/**
1052 * @brief Does the actual simulation
1053 * @param csn - csn to use
1054 * @param breakAfterMacReceived if true, returns after reader MAC has been received.
1055 */
b67f7ec3 1056int doIClassSimulation( int simulationMode, uint8_t *reader_mac_buf)
ff7bb4ef 1057{
b67f7ec3
MHS		 1058 // free eventually allocated BigBuf memory
1059 BigBuf_free_keep_EM();
55eaed8f 1060
61fe9073
MHS		 1061 State cipher_state;
1062// State cipher_state_reserve;
b67f7ec3
MHS		 1063 uint8_t *csn = BigBuf_get_EM_addr();
1064 uint8_t *emulator = csn;
1065 uint8_t sof_data[] = { 0x0F} ;
1e262141 1066 // CSN followed by two CRC bytes
b67f7ec3
MHS		 1067 uint8_t anticoll_data[10] = { 0 };
1068 uint8_t csn_data[10] = { 0 };
1069 memcpy(csn_data,csn,sizeof(csn_data));
f83cc126 1070 Dbprintf("Simulating CSN %02x%02x%02x%02x%02x%02x%02x%02x",csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
1e262141 1071
1e262141 1072 // Construct anticollision-CSN
b67f7ec3 1073 rotateCSN(csn_data,anticoll_data);
1e262141 1074
1075 // Compute CRC on both CSNs
b67f7ec3
MHS		 1076 ComputeCrc14443(CRC_ICLASS, anticoll_data, 8, &anticoll_data[8], &anticoll_data[9]);
1077 ComputeCrc14443(CRC_ICLASS, csn_data, 8, &csn_data[8], &csn_data[9]);
1078
61fe9073 1079 uint8_t diversified_key[8] = { 0 };
b67f7ec3
MHS		 1080 // e-Purse
1081 uint8_t card_challenge_data[8] = { 0x00 };
1082 if(simulationMode == MODE_FULLSIM)
1083 {
e5cd4ee4
MHS		 1084 //The diversified key should be stored on block 3
1085 //Get the diversified key from emulator memory
1086 memcpy(diversified_key, emulator+(8*3),8);
1087
b67f7ec3
MHS		 1088 //Card challenge, a.k.a e-purse is on block 2
1089 memcpy(card_challenge_data,emulator + (8 * 2) , 8);
61fe9073 1090 //Precalculate the cipher state, feeding it the CC
e5cd4ee4
MHS		 1091 cipher_state = opt_doTagMAC_1(card_challenge_data,diversified_key);
1092
b67f7ec3 1093 }
1e262141 1094
ff7bb4ef 1095 int exitLoop = 0;
1e262141 1096 // Reader 0a
1097 // Tag 0f
1098 // Reader 0c
1099 // Tag anticoll. CSN
1100 // Reader 81 anticoll. CSN
1101 // Tag CSN
1102
55eaed8f 1103 uint8_t *modulated_response;
b19caaef 1104 int modulated_response_size = 0;
55eaed8f
MHS		 1105 uint8_t* trace_data = NULL;
1106 int trace_data_size = 0;
1e262141 1107
b67f7ec3 1108
645c960f 1109 // Respond SOF -- takes 1 bytes
b67f7ec3
MHS		 1110 uint8_t *resp_sof = BigBuf_malloc(2);
1111 int resp_sof_Len;
1e262141 1112
1113 // Anticollision CSN (rotated CSN)
645c960f 1114 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
b67f7ec3
MHS		 1115 uint8_t *resp_anticoll = BigBuf_malloc(28);
1116 int resp_anticoll_len;
1e262141 1117
1118 // CSN
645c960f 1119 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
b67f7ec3
MHS		 1120 uint8_t *resp_csn = BigBuf_malloc(30);
1121 int resp_csn_len;
1e262141 1122
1123 // e-Purse
b3cc5f29 1124 // 18: Takes 2 bytes for SOF/EOF and 8 * 2 = 16 bytes (2 bytes/bit)
b67f7ec3
MHS		 1125 uint8_t *resp_cc = BigBuf_malloc(20);
1126 int resp_cc_len;
1e262141 1127
f71f4deb 1128 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1e262141 1129 int len;
1130
1e262141 1131 // Prepare card messages
1132 ToSendMax = 0;
1133
1134 // First card answer: SOF
1135 CodeIClassTagSOF();
b67f7ec3 1136 memcpy(resp_sof, ToSend, ToSendMax); resp_sof_Len = ToSendMax;
1e262141 1137
1138 // Anticollision CSN
b67f7ec3
MHS		 1139 CodeIClassTagAnswer(anticoll_data, sizeof(anticoll_data));
1140 memcpy(resp_anticoll, ToSend, ToSendMax); resp_anticoll_len = ToSendMax;
1e262141 1141
1142 // CSN
b67f7ec3
MHS		 1143 CodeIClassTagAnswer(csn_data, sizeof(csn_data));
1144 memcpy(resp_csn, ToSend, ToSendMax); resp_csn_len = ToSendMax;
1e262141 1145
1146 // e-Purse
b67f7ec3
MHS		 1147 CodeIClassTagAnswer(card_challenge_data, sizeof(card_challenge_data));
1148 memcpy(resp_cc, ToSend, ToSendMax); resp_cc_len = ToSendMax;
1e262141 1149
b19caaef 1150 //This is used for responding to READ-block commands or other data which is dynamically generated
c8387e85
MHS		 1151 //First the 'trace'-data, not encoded for FPGA
1152 uint8_t *data_generic_trace = BigBuf_malloc(8 + 2);//8 bytes data + 2byte CRC is max tag answer
1153 //Then storage for the modulated data
1154 //Each bit is doubled when modulated for FPGA, and we also have SOF and EOF (2 bytes)
1155 uint8_t *data_response = BigBuf_malloc( (8+2) * 2 + 2);
e3dc1e4c
MHS		 1156
1157 // Start from off (no field generated)
fa541aca
MHS		 1158 //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1159 //SpinDelay(200);
1160 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1161 SpinDelay(100);
1162 StartCountSspClk();
1e262141 1163 // We need to listen to the high-frequency, peak-detected path.
1164 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1165 FpgaSetupSsc();
1166
1167 // To control where we are in the protocol
1e262141 1168 int cmdsRecvd = 0;
81012e67
MHS		 1169 uint32_t time_0 = GetCountSspClk();
1170 uint32_t t2r_time =0;
1171 uint32_t r2t_time =0;
912a3e94 1172
1e262141 1173 LED_A_ON();
f83cc126 1174 bool buttonPressed = false;
e5cd4ee4 1175 uint8_t response_delay = 1;
ff7bb4ef 1176 while(!exitLoop) {
e5cd4ee4 1177 response_delay = 1;
1e262141 1178 LED_B_OFF();
e3dc1e4c
MHS		 1179 //Signal tracer
1180 // Can be used to get a trigger for an oscilloscope..
1181 LED_C_OFF();
1182
1e262141 1183 if(!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
f83cc126 1184 buttonPressed = true;
1e262141 1185 break;
81cd0474 1186 }
81012e67 1187 r2t_time = GetCountSspClk();
e3dc1e4c
MHS		 1188 //Signal tracer
1189 LED_C_ON();
1e262141 1190
81cd0474 1191 // Okay, look at the command now.
b67f7ec3 1192 if(receivedCmd[0] == ICLASS_CMD_ACTALL ) {
1e262141 1193 // Reader in anticollission phase
b67f7ec3
MHS		 1194 modulated_response = resp_sof; modulated_response_size = resp_sof_Len; //order = 1;
1195 trace_data = sof_data;
1196 trace_data_size = sizeof(sof_data);
1197 } else if(receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 1) {
1e262141 1198 // Reader asks for anticollission CSN
b67f7ec3
MHS		 1199 modulated_response = resp_anticoll; modulated_response_size = resp_anticoll_len; //order = 2;
1200 trace_data = anticoll_data;
1201 trace_data_size = sizeof(anticoll_data);
1e262141 1202 //DbpString("Reader requests anticollission CSN:");
b67f7ec3 1203 } else if(receivedCmd[0] == ICLASS_CMD_SELECT) {
1e262141 1204 // Reader selects anticollission CSN.
1205 // Tag sends the corresponding real CSN
b67f7ec3
MHS		 1206 modulated_response = resp_csn; modulated_response_size = resp_csn_len; //order = 3;
1207 trace_data = csn_data;
1208 trace_data_size = sizeof(csn_data);
1e262141 1209 //DbpString("Reader selects anticollission CSN:");
b67f7ec3 1210 } else if(receivedCmd[0] == ICLASS_CMD_READCHECK_KD) {
1e262141 1211 // Read e-purse (88 02)
b67f7ec3
MHS		 1212 modulated_response = resp_cc; modulated_response_size = resp_cc_len; //order = 4;
1213 trace_data = card_challenge_data;
1214 trace_data_size = sizeof(card_challenge_data);
1e262141 1215 LED_B_ON();
b67f7ec3 1216 } else if(receivedCmd[0] == ICLASS_CMD_CHECK) {
1e262141 1217 // Reader random and reader MAC!!!
b67f7ec3 1218 if(simulationMode == MODE_FULLSIM)
61fe9073
MHS		 1219 {
1220 //NR, from reader, is in receivedCmd +1
1221 opt_doTagMAC_2(cipher_state,receivedCmd+1,data_generic_trace,diversified_key);
1222
b19caaef 1223 trace_data = data_generic_trace;
b67f7ec3
MHS		 1224 trace_data_size = 4;
1225 CodeIClassTagAnswer(trace_data , trace_data_size);
1226 memcpy(data_response, ToSend, ToSendMax);
1227 modulated_response = data_response;
1228 modulated_response_size = ToSendMax;
e5cd4ee4 1229 response_delay = 0;//We need to hurry here...
10a8875c 1230 //exitLoop = true;
b67f7ec3
MHS		 1231 }else
1232 { //Not fullsim, we don't respond
f38a1528 1233 // We do not know what to answer, so lets keep quiet
b67f7ec3 1234 modulated_response = resp_sof; modulated_response_size = 0;
55eaed8f
MHS		 1235 trace_data = NULL;
1236 trace_data_size = 0;
b67f7ec3 1237 if (simulationMode == MODE_EXIT_AFTER_MAC){
ff7bb4ef 1238 // dbprintf:ing ...
f5ed4d12 1239 Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x"
1240 ,csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
ff7bb4ef 1241 Dbprintf("RDR: (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x",len,
a501c82b 1242 receivedCmd[0], receivedCmd[1], receivedCmd[2],
ff7bb4ef
MHS		 1243 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1244 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
9f6e9d15
MHS		 1245 if (reader_mac_buf != NULL)
1246 {
1247 memcpy(reader_mac_buf,receivedCmd+1,8);
1248 }
ff7bb4ef
MHS		 1249 exitLoop = true;
1250 }
ff7bb4ef 1251 }
b67f7ec3
MHS		 1252
1253 } else if(receivedCmd[0] == ICLASS_CMD_HALT && len == 1) {
1e262141 1254 // Reader ends the session
b67f7ec3 1255 modulated_response = resp_sof; modulated_response_size = 0; //order = 0;
55eaed8f
MHS		 1256 trace_data = NULL;
1257 trace_data_size = 0;
b67f7ec3
MHS		 1258 } else if(simulationMode == MODE_FULLSIM && receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 4){
1259 //Read block
1260 uint16_t blk = receivedCmd[1];
c8387e85
MHS		 1261 //Take the data...
1262 memcpy(data_generic_trace, emulator+(blk << 3),8);
1263 //Add crc
1264 AppendCrc(data_generic_trace, 8);
1265 trace_data = data_generic_trace;
1266 trace_data_size = 10;
1267 CodeIClassTagAnswer(trace_data , trace_data_size);
1268 memcpy(data_response, ToSend, ToSendMax);
1269 modulated_response = data_response;
1270 modulated_response_size = ToSendMax;
1271 }else if(receivedCmd[0] == ICLASS_CMD_UPDATE && simulationMode == MODE_FULLSIM)
1272 {//Probably the reader wants to update the nonce. Let's just ignore that for now.
1273 // OBS! If this is implemented, don't forget to regenerate the cipher_state
1274 //We're expected to respond with the data+crc, exactly what's already in the receivedcmd
1275 //receivedcmd is now UPDATE 1b | ADDRESS 1b| DATA 8b| Signature 4b or CRC 2b|
1276
1277 //Take the data...
1278 memcpy(data_generic_trace, receivedCmd+2,8);
1279 //Add crc
1280 AppendCrc(data_generic_trace, 8);
1281 trace_data = data_generic_trace;
1282 trace_data_size = 10;
b67f7ec3
MHS		 1283 CodeIClassTagAnswer(trace_data , trace_data_size);
1284 memcpy(data_response, ToSend, ToSendMax);
1285 modulated_response = data_response;
1286 modulated_response_size = ToSendMax;
1287 }
b19caaef
MHS		 1288 else if(receivedCmd[0] == ICLASS_CMD_PAGESEL)
1289 {//Pagesel
1290 //Pagesel enables to select a page in the selected chip memory and return its configuration block
1291 //Chips with a single page will not answer to this command
1292 // It appears we're fine ignoring this.
1293 //Otherwise, we should answer 8bytes (block) + 2bytes CRC
1294 }
b67f7ec3 1295 else {
17cba269 1296 //#db# Unknown command received from reader (len=5): 26 1 0 f6 a 44 44 44 44
1e262141 1297 // Never seen this command before
1298 Dbprintf("Unknown command received from reader (len=%d): %x %x %x %x %x %x %x %x %x",
1299 len,
1300 receivedCmd[0], receivedCmd[1], receivedCmd[2],
1301 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1302 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
1303 // Do not respond
b67f7ec3 1304 modulated_response = resp_sof; modulated_response_size = 0; //order = 0;
55eaed8f
MHS		 1305 trace_data = NULL;
1306 trace_data_size = 0;
1e262141 1307 }
1308
81012e67
MHS		 1309 if(cmdsRecvd > 100) {
1310 //DbpString("100 commands later...");
9f6e9d15 1311 //break;
1e262141 1312 }
1313 else {
1314 cmdsRecvd++;
1315 }
55eaed8f 1316 /**
6b038d19 1317 A legit tag has about 380us delay between reader EOT and tag SOF.
55eaed8f
MHS		 1318 **/
1319 if(modulated_response_size > 0) {
e5cd4ee4 1320 SendIClassAnswer(modulated_response, modulated_response_size, response_delay);
81012e67 1321 t2r_time = GetCountSspClk();
81cd0474 1322 }
f83cc126 1323
81cd0474 1324 if (tracing) {
a501c82b 1325 uint8_t parity[MAX_PARITY_SIZE];
1326 GetParity(receivedCmd, len, parity);
1327 LogTrace(receivedCmd,len, (r2t_time-time_0)<< 4, (r2t_time-time_0) << 4, parity, TRUE);
17cba269 1328
55eaed8f
MHS		 1329 if (trace_data != NULL) {
1330 GetParity(trace_data, trace_data_size, parity);
1331 LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
17cba269 1332 }
81012e67
MHS		 1333 if(!tracing) {
1334 DbpString("Trace full");
1335 //break;
1336 }
1337
81cd0474 1338 }
81cd0474 1339 }
1e262141 1340
9f6e9d15 1341 //Dbprintf("%x", cmdsRecvd);
1e262141 1342 LED_A_OFF();
1343 LED_B_OFF();
7b941c8d
MHS		 1344 LED_C_OFF();
1345
f83cc126
MHS		 1346 if(buttonPressed)
1347 {
1348 DbpString("Button pressed");
1349 }
f83cc126 1350 return buttonPressed;
1e262141 1351}
1352
1353static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
1354{
e3dc1e4c 1355 int i = 0, d=0;//, u = 0, d = 0;
1e262141 1356 uint8_t b = 0;
e3dc1e4c 1357
645c960f
MHS		 1358 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
1359 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
e3dc1e4c 1360
1e262141 1361 AT91C_BASE_SSC->SSC_THR = 0x00;
1362 FpgaSetupSsc();
e3dc1e4c
MHS		 1363 while(!BUTTON_PRESS()) {
1364 if((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
1365 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1e262141 1366 }
e3dc1e4c
MHS		 1367 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
1368 b = 0x00;
1e262141 1369 if(d < delay) {
1e262141 1370 d++;
1371 }
e3dc1e4c
MHS		 1372 else {
1373 if( i < respLen){
1374 b = resp[i];
1375 //Hack
1376 //b = 0xAC;
1377 }
1378 i++;
1e262141 1379 }
1380 AT91C_BASE_SSC->SSC_THR = b;
1e262141 1381 }
e3dc1e4c 1382
645c960f
MHS		 1383// if (i > respLen +4) break;
1384 if (i > respLen +1) break;
1e262141 1385 }
1386
1387 return 0;
1388}
1389
1390/// THE READER CODE
1391
1392//-----------------------------------------------------------------------------
1393// Transmit the command (to the tag) that was placed in ToSend[].
1394//-----------------------------------------------------------------------------
1395static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
1396{
1397 int c;
1e262141 1398 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1399 AT91C_BASE_SSC->SSC_THR = 0x00;
1400 FpgaSetupSsc();
1401
1402 if (wait)
f5ed4d12 1403 {
1404 if(*wait < 10) *wait = 10;
2ed270a8 1405
1e262141 1406 for(c = 0; c < *wait;) {
1407 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1408 AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
1409 c++;
1410 }
1411 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1412 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1413 (void)r;
1414 }
1415 WDT_HIT();
1416 }
1417
f5ed4d12 1418 }
1419
1420
1e262141 1421 uint8_t sendbyte;
1422 bool firstpart = TRUE;
1423 c = 0;
1424 for(;;) {
1425 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1426
1427 // DOUBLE THE SAMPLES!
1428 if(firstpart) {
1429 sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
1430 }
1431 else {
1432 sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
1433 c++;
1434 }
1435 if(sendbyte == 0xff) {
1436 sendbyte = 0xfe;
1437 }
1438 AT91C_BASE_SSC->SSC_THR = sendbyte;
1439 firstpart = !firstpart;
1440
1441 if(c >= len) {
1442 break;
1443 }
1444 }
1445 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1446 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1447 (void)r;
1448 }
1449 WDT_HIT();
1450 }
1451 if (samples) *samples = (c + *wait) << 3;
1452}
1453
1454
1455//-----------------------------------------------------------------------------
1456// Prepare iClass reader command to send to FPGA
1457//-----------------------------------------------------------------------------
1458void CodeIClassCommand(const uint8_t * cmd, int len)
1459{
1460 int i, j, k;
1461 uint8_t b;
1462
1463 ToSendReset();
1464
1465 // Start of Communication: 1 out of 4
1466 ToSend[++ToSendMax] = 0xf0;
1467 ToSend[++ToSendMax] = 0x00;
1468 ToSend[++ToSendMax] = 0x0f;
1469 ToSend[++ToSendMax] = 0x00;
1470
1471 // Modulate the bytes
1472 for (i = 0; i < len; i++) {
1473 b = cmd[i];
1474 for(j = 0; j < 4; j++) {
1475 for(k = 0; k < 4; k++) {
e3dc1e4c
MHS		 1476 if(k == (b & 3)) {
1477 ToSend[++ToSendMax] = 0x0f;
1478 }
1479 else {
1480 ToSend[++ToSendMax] = 0x00;
1481 }
1e262141 1482 }
1483 b >>= 2;
1484 }
1485 }
1486
1487 // End of Communication
1488 ToSend[++ToSendMax] = 0x00;
1489 ToSend[++ToSendMax] = 0x00;
1490 ToSend[++ToSendMax] = 0xf0;
1491 ToSend[++ToSendMax] = 0x00;
1492
1493 // Convert from last character reference to length
1494 ToSendMax++;
1495}
1496
1497void ReaderTransmitIClass(uint8_t* frame, int len)
1498{
1499 int wait = 0;
1500 int samples = 0;
1e262141 1501
1502 // This is tied to other size changes
1e262141 1503 CodeIClassCommand(frame,len);
1504
1505 // Select the card
1506 TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait);
1507 if(trigger)
1508 LED_A_ON();
1509
1510 // Store reader command in buffer
6a1f2d82 1511 if (tracing) {
a501c82b 1512 uint8_t par[MAX_PARITY_SIZE];
1513 GetParity(frame, len, par);
1514 LogTrace(frame, len, rsamples, rsamples, par, TRUE);
1515 }
1e262141 1516}
1517
1518//-----------------------------------------------------------------------------
1519// Wait a certain time for tag response
1520// If a response is captured return TRUE
1521// If it takes too long return FALSE
1522//-----------------------------------------------------------------------------
1523static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer
1524{
1525 // buffer needs to be 512 bytes
1526 int c;
1527
1528 // Set FPGA mode to "reader listen mode", no modulation (listen
1529 // only, since we are receiving, not transmitting).
1530 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1531
1532 // Now get the answer from the card
1533 Demod.output = receivedResponse;
1534 Demod.len = 0;
1535 Demod.state = DEMOD_UNSYNCD;
1536
1537 uint8_t b;
1538 if (elapsed) *elapsed = 0;
1539
1540 bool skip = FALSE;
1541
1542 c = 0;
1543 for(;;) {
1544 WDT_HIT();
1545
95e63594 1546 if(BUTTON_PRESS()) return FALSE;
1e262141 1547
1548 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1549 AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!
1550 if (elapsed) (*elapsed)++;
1551 }
1552 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1553 if(c < timeout) { c++; } else { return FALSE; }
1554 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1555 skip = !skip;
1556 if(skip) continue;
95e63594 1557
1e262141 1558 if(ManchesterDecoding(b & 0x0f)) {
1559 *samples = c << 3;
1560 return TRUE;
1561 }
1562 }
1563 }
1564}
1565
1566int ReaderReceiveIClass(uint8_t* receivedAnswer)
1567{
1568 int samples = 0;
1569 if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return FALSE;
7bc95e2e 1570 rsamples += samples;
6a1f2d82 1571 if (tracing) {
1572 uint8_t parity[MAX_PARITY_SIZE];
1573 GetParity(receivedAnswer, Demod.len, parity);
1574 LogTrace(receivedAnswer,Demod.len,rsamples,rsamples,parity,FALSE);
a501c82b 1575 }
1e262141 1576 if(samples == 0) return FALSE;
1577 return Demod.len;
1578}
1579
f38a1528 1580void setupIclassReader()
1581{
1582 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1583 // Reset trace buffer
3000dc4e
MHS		 1584 set_tracing(TRUE);
1585 clear_trace();
f38a1528 1586
1587 // Setup SSC
1588 FpgaSetupSsc();
1589 // Start from off (no field generated)
1590 // Signal field is off with the appropriate LED
1591 LED_D_OFF();
1592 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1593 SpinDelay(200);
1594
1595 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1596
1597 // Now give it time to spin up.
1598 // Signal field is on with the appropriate LED
1599 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1600 SpinDelay(200);
1601 LED_A_ON();
1602
1603}
1604
e98572a1 1605bool sendCmdGetResponseWithRetries(uint8_t* command, size_t cmdsize, uint8_t* resp, uint8_t expected_size, uint8_t retries)
d3a22c7d 1606{
1607 while(retries-- > 0)
1608 {
1609 ReaderTransmitIClass(command, cmdsize);
1610 if(expected_size == ReaderReceiveIClass(resp)){
e98572a1 1611 return true;
d3a22c7d 1612 }
1613 }
e98572a1 1614 return false;//Error
d3a22c7d 1615}
1616
1617/**
1618 * @brief Talks to an iclass tag, sends the commands to get CSN and CC.
1619 * @param card_data where the CSN and CC are stored for return
1620 * @return 0 = fail
1621 * 1 = Got CSN
1622 * 2 = Got CSN and CC
1623 */
e98572a1 1624uint8_t handshakeIclassTag_ext(uint8_t *card_data, bool use_credit_key)
d3a22c7d 1625{
1626 static uint8_t act_all[] = { 0x0a };
e98572a1 1627 //static uint8_t identify[] = { 0x0c };
1628 static uint8_t identify[] = { 0x0c, 0x00, 0x73, 0x33 };
d3a22c7d 1629 static uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
e98572a1 1630 static uint8_t readcheck_cc[]= { 0x88, 0x02 };
1631 if (use_credit_key)
1632 readcheck_cc[0] = 0x18;
1633 else
1634 readcheck_cc[0] = 0x88;
caaf9618 1635
f71f4deb 1636 uint8_t resp[ICLASS_BUFFER_SIZE];
d3a22c7d 1637
1638 uint8_t read_status = 0;
1639
1640 // Send act_all
1641 ReaderTransmitIClass(act_all, 1);
1642 // Card present?
1643 if(!ReaderReceiveIClass(resp)) return read_status;//Fail
1644 //Send Identify
1645 ReaderTransmitIClass(identify, 1);
1646 //We expect a 10-byte response here, 8 byte anticollision-CSN and 2 byte CRC
1647 uint8_t len = ReaderReceiveIClass(resp);
1648 if(len != 10) return read_status;//Fail
1649
1650 //Copy the Anti-collision CSN to our select-packet
1651 memcpy(&select[1],resp,8);
1652 //Select the card
1653 ReaderTransmitIClass(select, sizeof(select));
1654 //We expect a 10-byte response here, 8 byte CSN and 2 byte CRC
1655 len = ReaderReceiveIClass(resp);
1656 if(len != 10) return read_status;//Fail
1657
1658 //Success - level 1, we got CSN
1659 //Save CSN in response data
1660 memcpy(card_data,resp,8);
1661
1662 //Flag that we got to at least stage 1, read CSN
1663 read_status = 1;
1664
1665 // Card selected, now read e-purse (cc)
1666 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1667 if(ReaderReceiveIClass(resp) == 8) {
1668 //Save CC (e-purse) in response data
1669 memcpy(card_data+8,resp,8);
caaf9618 1670 read_status++;
d3a22c7d 1671 }
1672
1673 return read_status;
1674}
e98572a1 1675uint8_t handshakeIclassTag(uint8_t *card_data){
1676 return handshakeIclassTag_ext(card_data, false);
1677}
d3a22c7d 1678
caaf9618 1679
1e262141 1680// Reader iClass Anticollission
1681void ReaderIClass(uint8_t arg0) {
f38a1528 1682
83602aff
MHS		 1683 uint8_t card_data[6 * 8]={0};
1684 memset(card_data, 0xFF, sizeof(card_data));
f38a1528 1685 uint8_t last_csn[8]={0};
6a1f2d82 1686
caaf9618
MHS		 1687 //Read conf block CRC(0x01) => 0xfa 0x22
1688 uint8_t readConf[] = { ICLASS_CMD_READ_OR_IDENTIFY,0x01, 0xfa, 0x22};
1689 //Read conf block CRC(0x05) => 0xde 0x64
1690 uint8_t readAA[] = { ICLASS_CMD_READ_OR_IDENTIFY,0x05, 0xde, 0x64};
1691
1692
f38a1528 1693 int read_status= 0;
caaf9618 1694 uint8_t result_status = 0;
f38a1528 1695 bool abort_after_read = arg0 & FLAG_ICLASS_READER_ONLY_ONCE;
8949bb5d 1696 bool try_once = arg0 & FLAG_ICLASS_READER_ONE_TRY;
e98572a1 1697 bool use_credit_key = false;
1698 if (arg0 & FLAG_ICLASS_READER_CEDITKEY)
1699 use_credit_key = true;
3000dc4e 1700 set_tracing(TRUE);
f38a1528 1701 setupIclassReader();
1702
8949bb5d 1703 uint16_t tryCnt=0;
f38a1528 1704 while(!BUTTON_PRESS())
1705 {
8949bb5d 1706 if (try_once && tryCnt > 5) break;
1707 tryCnt++;
3000dc4e 1708 if(!tracing) {
d3a22c7d 1709 DbpString("Trace full");
1710 break;
1711 }
c8dd9b09 1712 WDT_HIT();
f38a1528 1713
e98572a1 1714 read_status = handshakeIclassTag_ext(card_data, use_credit_key);
d3a22c7d 1715
1716 if(read_status == 0) continue;
caaf9618
MHS		 1717 if(read_status == 1) result_status = FLAG_ICLASS_READER_CSN;
1718 if(read_status == 2) result_status = FLAG_ICLASS_READER_CSN|FLAG_ICLASS_READER_CC;
1719
1720 // handshakeIclass returns CSN|CC, but the actual block
1721 // layout is CSN|CONFIG|CC, so here we reorder the data,
1722 // moving CC forward 8 bytes
1723 memcpy(card_data+16,card_data+8, 8);
1724 //Read block 1, config
1725 if(arg0 & FLAG_ICLASS_READER_CONF)
1726 {
1727 if(sendCmdGetResponseWithRetries(readConf, sizeof(readConf),card_data+8, 10, 10))
caaf9618
MHS		 1728 {
1729 result_status |= FLAG_ICLASS_READER_CONF;
e98572a1 1730 } else {
1731 Dbprintf("Failed to dump config block");
caaf9618
MHS		 1732 }
1733 }
f38a1528 1734
caaf9618
MHS		 1735 //Read block 5, AA
1736 if(arg0 & FLAG_ICLASS_READER_AA){
1737 if(sendCmdGetResponseWithRetries(readAA, sizeof(readAA),card_data+(8*4), 10, 10))
1738 {
caaf9618 1739 result_status |= FLAG_ICLASS_READER_AA;
e98572a1 1740 } else {
1741 //Dbprintf("Failed to dump AA block");
caaf9618
MHS		 1742 }
1743 }
1744
1745 // 0 : CSN
b67f7ec3 1746 // 1 : Configuration
caaf9618
MHS		 1747 // 2 : e-purse
1748 // (3,4 write-only, kc and kd)
b67f7ec3
MHS		 1749 // 5 Application issuer area
1750 //
1751 //Then we can 'ship' back the 8 * 5 bytes of data,
1752 // with 0xFF:s in block 3 and 4.
1753
f38a1528 1754 LED_B_ON();
1755 //Send back to client, but don't bother if we already sent this
1756 if(memcmp(last_csn, card_data, 8) != 0)
d3a22c7d 1757 {
caaf9618
MHS		 1758 // If caller requires that we get CC, continue until we got it
1759 if( (arg0 & read_status & FLAG_ICLASS_READER_CC) || !(arg0 & FLAG_ICLASS_READER_CC))
d3a22c7d 1760 {
caaf9618 1761 cmd_send(CMD_ACK,result_status,0,0,card_data,sizeof(card_data));
d3a22c7d 1762 if(abort_after_read) {
1763 LED_A_OFF();
5ee53a0e 1764 set_tracing(FALSE);
d3a22c7d 1765 return;
1766 }
5ee53a0e 1767 //Save that we already sent this....
1768 memcpy(last_csn, card_data, 8);
d3a22c7d 1769 }
d3a22c7d 1770 }
c8dd9b09 1771 LED_B_OFF();
f38a1528 1772 }
d3a22c7d 1773 cmd_send(CMD_ACK,0,0,0,card_data, 0);
aa41c605 1774 LED_A_OFF();
5ee53a0e 1775 set_tracing(FALSE);
f38a1528 1776}
1777
1778void ReaderIClass_Replay(uint8_t arg0, uint8_t *MAC) {
d3a22c7d 1779
14edfd09 1780 uint8_t card_data[USB_CMD_DATA_SIZE]={0};
d3a22c7d 1781 uint16_t block_crc_LUT[255] = {0};
1782
1783 {//Generate a lookup table for block crc
1784 for(int block = 0; block < 255; block++){
1785 char bl = block;
1786 block_crc_LUT[block] = iclass_crc16(&bl ,1);
1787 }
1788 }
1789 //Dbprintf("Lookup table: %02x %02x %02x" ,block_crc_LUT[0],block_crc_LUT[1],block_crc_LUT[2]);
1790
f38a1528 1791 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1792 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1793
fecd8202 1794 uint16_t crc = 0;
f38a1528 1795 uint8_t cardsize=0;
f38a1528 1796 uint8_t mem=0;
1797
1798 static struct memory_t{
1799 int k16;
1800 int book;
1801 int k2;
1802 int lockauth;
1803 int keyaccess;
1804 } memory;
1805
f71f4deb 1806 uint8_t resp[ICLASS_BUFFER_SIZE];
6a1f2d82 1807
f38a1528 1808 setupIclassReader();
3000dc4e 1809 set_tracing(TRUE);
f38a1528 1810
d3a22c7d 1811 while(!BUTTON_PRESS()) {
1812
1813 WDT_HIT();
39d3ce5d 1814
3000dc4e 1815 if(!tracing) {
f38a1528 1816 DbpString("Trace full");
1817 break;
1818 }
1819
d3a22c7d 1820 uint8_t read_status = handshakeIclassTag(card_data);
1821 if(read_status < 2) continue;
1822
5ee53a0e 1823 //for now replay captured auth (as cc not updated)
1824 memcpy(check+5,MAC,4);
d3a22c7d 1825
e98572a1 1826 if(!sendCmdGetResponseWithRetries(check, sizeof(check),resp, 4, 5))
d3a22c7d 1827 {
5ee53a0e 1828 Dbprintf("Error: Authentication Fail!");
d3a22c7d 1829 continue;
5ee53a0e 1830 }
d3a22c7d 1831
1832 //first get configuration block (block 1)
1833 crc = block_crc_LUT[1];
5ee53a0e 1834 read[1]=1;
1835 read[2] = crc >> 8;
1836 read[3] = crc & 0xff;
d3a22c7d 1837
e98572a1 1838 if(!sendCmdGetResponseWithRetries(read, sizeof(read),resp, 10, 10))
d3a22c7d 1839 {
1840 Dbprintf("Dump config (block 1) failed");
1841 continue;
1842 }
1843
5ee53a0e 1844 mem=resp[5];
1845 memory.k16= (mem & 0x80);
1846 memory.book= (mem & 0x20);
1847 memory.k2= (mem & 0x8);
1848 memory.lockauth= (mem & 0x2);
1849 memory.keyaccess= (mem & 0x1);
f38a1528 1850
d3a22c7d 1851 cardsize = memory.k16 ? 255 : 32;
1852 WDT_HIT();
14edfd09 1853 //Set card_data to all zeroes, we'll fill it with data
1854 memset(card_data,0x0,USB_CMD_DATA_SIZE);
1855 uint8_t failedRead =0;
428d6221 1856 uint32_t stored_data_length =0;
f38a1528 1857 //then loop around remaining blocks
d3a22c7d 1858 for(int block=0; block < cardsize; block++){
1859
1860 read[1]= block;
1861 crc = block_crc_LUT[block];
5ee53a0e 1862 read[2] = crc >> 8;
1863 read[3] = crc & 0xff;
d3a22c7d 1864
e98572a1 1865 if(sendCmdGetResponseWithRetries(read, sizeof(read), resp, 10, 10))
d3a22c7d 1866 {
5ee53a0e 1867 Dbprintf(" %02x: %02x %02x %02x %02x %02x %02x %02x %02x",
1868 block, resp[0], resp[1], resp[2],
1869 resp[3], resp[4], resp[5],
1870 resp[6], resp[7]);
d3a22c7d 1871
14edfd09 1872 //Fill up the buffer
1873 memcpy(card_data+stored_data_length,resp,8);
1874 stored_data_length += 8;
14edfd09 1875 if(stored_data_length +8 > USB_CMD_DATA_SIZE)
1876 {//Time to send this off and start afresh
1877 cmd_send(CMD_ACK,
1878 stored_data_length,//data length
1879 failedRead,//Failed blocks?
1880 0,//Not used ATM
1881 card_data, stored_data_length);
1882 //reset
1883 stored_data_length = 0;
1884 failedRead = 0;
1885 }
5ee53a0e 1886 } else {
14edfd09 1887 failedRead = 1;
1888 stored_data_length +=8;//Otherwise, data becomes misaligned
d3a22c7d 1889 Dbprintf("Failed to dump block %d", block);
f38a1528 1890 }
1891 }
428d6221 1892
14edfd09 1893 //Send off any remaining data
1894 if(stored_data_length > 0)
1895 {
1896 cmd_send(CMD_ACK,
1897 stored_data_length,//data length
1898 failedRead,//Failed blocks?
1899 0,//Not used ATM
1900 card_data, stored_data_length);
1901 }
d3a22c7d 1902 //If we got here, let's break
1903 break;
f38a1528 1904 }
14edfd09 1905 //Signal end of transmission
1906 cmd_send(CMD_ACK,
1907 0,//data length
1908 0,//Failed blocks?
1909 0,//Not used ATM
1910 card_data, 0);
1911
f38a1528 1912 LED_A_OFF();
5ee53a0e 1913 set_tracing(FALSE);
f38a1528 1914}
1915
e98572a1 1916void iClass_ReadCheck(uint8_t blockNo, uint8_t keyType) {
1917 uint8_t readcheck[] = { keyType, blockNo };
1918 uint8_t resp[] = {0,0,0,0,0,0,0,0};
1919 size_t isOK = 0;
1920 isOK = sendCmdGetResponseWithRetries(readcheck, sizeof(readcheck), resp, sizeof(resp), 6);
1921 cmd_send(CMD_ACK,isOK,0,0,0,0);
1922}
1e262141 1923
e98572a1 1924void iClass_Authentication(uint8_t *MAC) {
1925 uint8_t check[] = { ICLASS_CMD_CHECK, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1926 uint8_t resp[ICLASS_BUFFER_SIZE];
1927 memcpy(check+5,MAC,4);
1928 bool isOK;
1929 isOK = sendCmdGetResponseWithRetries(check, sizeof(check), resp, 4, 6);
1930 cmd_send(CMD_ACK,isOK,0,0,0,0);
1931}
1932bool iClass_ReadBlock(uint8_t blockNo, uint8_t *readdata) {
1933 uint8_t readcmd[] = {ICLASS_CMD_READ_OR_IDENTIFY, blockNo, 0x00, 0x00}; //0x88, 0x00 // can i use 0C?
1934 char bl = blockNo;
1935 uint16_t rdCrc = iclass_crc16(&bl, 1);
1936 readcmd[2] = rdCrc >> 8;
1937 readcmd[3] = rdCrc & 0xff;
1938 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1939 bool isOK = false;
1940
1941 //readcmd[1] = blockNo;
1942 isOK = sendCmdGetResponseWithRetries(readcmd, sizeof(readcmd), resp, 10, 10);
1943 memcpy(readdata, resp, sizeof(resp));
1944
1945 return isOK;
1946}
1e262141 1947
e98572a1 1948void iClass_ReadBlk(uint8_t blockno) {
1949 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1950 bool isOK = false;
1951 isOK = iClass_ReadBlock(blockno, readblockdata);
1952 cmd_send(CMD_ACK, isOK, 0, 0, readblockdata, 8);
1953}
1e262141 1954
e98572a1 1955void iClass_Dump(uint8_t blockno, uint8_t numblks) {
1956 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1957 bool isOK = false;
1958 uint8_t blkCnt = 0;
1e262141 1959
e98572a1 1960 BigBuf_free();
1961 uint8_t *dataout = BigBuf_malloc(255*8);
1962 if (dataout == NULL){
1963 Dbprintf("out of memory");
1964 OnError(1);
1965 return;
1966 }
1967 memset(dataout,0xFF,255*8);
1968
1969 for (;blkCnt < numblks; blkCnt++) {
1970 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1971 if (!isOK || (readblockdata[0] == 0xBB || readblockdata[7] == 0xBB || readblockdata[2] == 0xBB)) { //try again
1972 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1973 if (!isOK) {
1974 Dbprintf("Block %02X failed to read", blkCnt+blockno);
4ab4336a 1975 break;
1976 }
e98572a1 1977 }
1978 memcpy(dataout+(blkCnt*8),readblockdata,8);
1979 }
1980 //return pointer to dump memory in arg3
1981 cmd_send(CMD_ACK,isOK,blkCnt,BigBuf_max_traceLen(),0,0);
1982 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1983 LEDsoff();
1984 BigBuf_free();
1985}
1986
1987bool iClass_WriteBlock_ext(uint8_t blockNo, uint8_t *data) {
1988 uint8_t write[] = { ICLASS_CMD_UPDATE, blockNo, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1989 //uint8_t readblockdata[10];
1990 //write[1] = blockNo;
1991 memcpy(write+2, data, 12); // data + mac
1992 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1993 bool isOK;
1994 isOK = sendCmdGetResponseWithRetries(write,sizeof(write),resp,sizeof(resp),10);
1995 if (isOK) {
1996 //Dbprintf("WriteResp: %02X%02X%02X%02X%02X%02X%02X%02X%02X%02X",resp[0],resp[1],resp[2],resp[3],resp[4],resp[5],resp[6],resp[7],resp[8],resp[9]);
1997 if (memcmp(write+2,resp,8)) {
1998 //error try again
1999 isOK = sendCmdGetResponseWithRetries(write,sizeof(write),resp,sizeof(resp),10);
2000 }
2001 }
2002 return isOK;
2003}
2004
2005void iClass_WriteBlock(uint8_t blockNo, uint8_t *data) {
2006 bool isOK = iClass_WriteBlock_ext(blockNo, data);
2007 if (isOK){
2008 Dbprintf("Write block [%02x] successful",blockNo);
f38a1528 2009 }else {
e98572a1 2010 Dbprintf("Write block [%02x] failed",blockNo);
2011 }
2012 cmd_send(CMD_ACK,isOK,0,0,0,0);
2013}
f38a1528 2014
e98572a1 2015void iClass_Clone(uint8_t startblock, uint8_t endblock, uint8_t *data) {
2016 int i;
2017 int written = 0;
2018 int total_block = (endblock - startblock) + 1;
2019 for (i = 0; i < total_block;i++){
2020 // block number
2021 if (iClass_WriteBlock_ext(i+startblock, data+(i*12))){
2022 Dbprintf("Write block [%02x] successful",i + startblock);
2023 written++;
2024 } else {
2025 if (iClass_WriteBlock_ext(i+startblock, data+(i*12))){
2026 Dbprintf("Write block [%02x] successful",i + startblock);
2027 written++;
2028 } else {
2029 Dbprintf("Write block [%02x] failed",i + startblock);
2030 }
1e262141 2031 }
1e262141 2032 }
e98572a1 2033 if (written == total_block)
2034 Dbprintf("Clone complete");
2035 else
2036 Dbprintf("Clone incomplete");
2037
2038 cmd_send(CMD_ACK,1,0,0,0,0);
2039 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2040 LEDsoff();
2041}
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