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FIX: lf hitag : Mea culpa, simulation should not have reader_field on. thanks to...
[proxmark3-svn] / bootrom / bootrom.c
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bd20f8f4 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Main code for the bootloader
7//-----------------------------------------------------------------------------
8
15c4dc5a 9#include <proxmark3.h>
28fdb04f 10#include "usb_cdc.h"
11#include "cmd.h"
28fdb04f 12
13void DbpString(char *str) {
cf69eca0 14 byte_t len = 0;
15 while (str[len] != 0x00)
16 ++len;
17
18 cmd_send(CMD_DEBUG_PRINT_STRING,len,0,0,(byte_t*)str,len);
28fdb04f 19}
15c4dc5a 20
21struct common_area common_area __attribute__((section(".commonarea")));
22unsigned int start_addr, end_addr, bootrom_unlocked;
23extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
24
25static void ConfigClocks(void)
26{
27 // we are using a 16 MHz crystal as the basis for everything
28 // slow clock runs at 32Khz typical regardless of crystal
29
30 // enable system clock and USB clock
31 AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;
32
33 // enable the clock to the following peripherals
34 AT91C_BASE_PMC->PMC_PCER =
35 (1<<AT91C_ID_PIOA) |
36 (1<<AT91C_ID_ADC) |
37 (1<<AT91C_ID_SPI) |
38 (1<<AT91C_ID_SSC) |
39 (1<<AT91C_ID_PWMC) |
40 (1<<AT91C_ID_UDP);
41
0aa4cfc2 42 // worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
43 // if SLCK slow clock runs at its worst case (max) frequency of 42khz
44 // max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
15c4dc5a 45
46 // enable main oscillator and set startup delay
47 AT91C_BASE_PMC->PMC_MOR =
0aa4cfc2 48 AT91C_CKGR_MOSCEN |
49 PMC_MAIN_OSC_STARTUP_DELAY(8);
15c4dc5a 50
51 // wait for main oscillator to stabilize
3c654208 52 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) ) {};
15c4dc5a 53
0aa4cfc2 54 // PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
55 // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
56 // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
15c4dc5a 57 AT91C_BASE_PMC->PMC_PLLR =
58 PMC_PLL_DIVISOR(2) |
59 PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
60 PMC_PLL_FREQUENCY_RANGE(0) |
61 PMC_PLL_MULTIPLIER(12) |
62 PMC_PLL_USB_DIVISOR(1);
63
64 // wait for PLL to lock
3c654208 65 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ) {};
15c4dc5a 66
67 // we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
0aa4cfc2 68 // datasheet recommends that this register is programmed in two operations
15c4dc5a 69 // when changing to PLL, program the prescaler first then the source
0aa4cfc2 70 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
15c4dc5a 71
72 // wait for main clock ready signal
3c654208 73 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
15c4dc5a 74
75 // set the source to PLL
0aa4cfc2 76 AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
15c4dc5a 77
78 // wait for main clock ready signal
3c654208 79 while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ) {};
15c4dc5a 80}
81
cf69eca0 82static void Fatal(void) {
28fdb04f 83 for(;;);
15c4dc5a 84}
85
28fdb04f 86void UsbPacketReceived(uint8_t *packet, int len) {
cf69eca0 87 int i, dont_ack=0;
88 UsbCommand* c = (UsbCommand *)packet;
89 volatile uint32_t *p;
90
91 if(len != sizeof(UsbCommand)) Fatal();
28fdb04f 92
cf69eca0 93 uint32_t arg0 = (uint32_t)c->arg[0];
28fdb04f 94
cf69eca0 95 switch(c->cmd) {
96 case CMD_DEVICE_INFO: {
97 dont_ack = 1;
98 arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
99 DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
100 if(common_area.flags.osimage_present)
101 arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
102
103 cmd_send(CMD_DEVICE_INFO,arg0,1,2,0,0);
104 } break;
28fdb04f 105
cf69eca0 106 case CMD_SETUP_WRITE: {
107 /* The temporary write buffer of the embedded flash controller is mapped to the
108 * whole memory region, only the last 8 bits are decoded.
109 */
110 p = (volatile uint32_t *)&_flash_start;
111 for(i = 0; i < 12; i++)
112 p[i+arg0] = c->d.asDwords[i];
113 } break;
28fdb04f 114
cf69eca0 115 case CMD_FINISH_WRITE: {
116 uint32_t* flash_mem = (uint32_t*)(&_flash_start);
117 for ( int j=0; j<2; j++) {
118 for(i = 0+(64*j); i < 64+(64*j); i++) {
119 flash_mem[i] = c->d.asDwords[i];
120 }
28fdb04f 121
cf69eca0 122 uint32_t flash_address = arg0 + (0x100*j);
28fdb04f 123
cf69eca0 124 /* Check that the address that we are supposed to write to is within our allowed region */
125 if( ((flash_address+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (flash_address < start_addr) ) {
126 /* Disallow write */
127 dont_ack = 1;
128 cmd_send(CMD_NACK,0,0,0,0,0);
129 } else {
130 uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
131 /* Translate address to flash page and do flash, update here for the 512k part */
132 AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
133 MC_FLASH_COMMAND_PAGEN(page_n) |
134 AT91C_MC_FCMD_START_PROG;
135 }
28fdb04f 136
cf69eca0 137 // Wait until flashing of page finishes
138 uint32_t sr;
139 while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
1cb9b2a3
RW
140 if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
141 dont_ack = 1;
142 cmd_send(CMD_NACK,sr,0,0,0,0);
143 }
cf69eca0 144 }
145 } break;
28fdb04f 146
cf69eca0 147 case CMD_HARDWARE_RESET: {
148 usb_disable();
149 AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
150 } break;
28fdb04f 151
cf69eca0 152 case CMD_START_FLASH: {
153 if(c->arg[2] == START_FLASH_MAGIC)
154 bootrom_unlocked = 1;
155 else
156 bootrom_unlocked = 0;
157
158 int prot_start = (int)&_bootrom_start;
159 int prot_end = (int)&_bootrom_end;
160 int allow_start = (int)&_flash_start;
161 int allow_end = (int)&_flash_end;
162 int cmd_start = c->arg[0];
163 int cmd_end = c->arg[1];
164
165 /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
166 * bootrom area. In any case they must be within the flash area.
167 */
168 if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start))) &&
169 (cmd_start >= allow_start) &&
170 (cmd_end <= allow_end) ) {
171 start_addr = cmd_start;
172 end_addr = cmd_end;
173 } else {
174 start_addr = end_addr = 0;
175 dont_ack = 1;
176 cmd_send(CMD_NACK,0,0,0,0,0);
177 }
178 } break;
28fdb04f 179
cf69eca0 180 default: {
181 Fatal();
182 } break;
183 }
28fdb04f 184
cf69eca0 185 if(!dont_ack)
186 cmd_send(CMD_ACK,arg0,0,0,0,0);
15c4dc5a 187}
188
189static void flash_mode(int externally_entered)
190{
191 start_addr = 0;
192 end_addr = 0;
193 bootrom_unlocked = 0;
cf69eca0 194 byte_t rx[sizeof(UsbCommand)];
28fdb04f 195 size_t rx_len;
196
cf69eca0 197 usb_enable();
3c654208 198 for (volatile size_t i=0; i<0x100000; i++) {};
15c4dc5a 199
15c4dc5a 200 for(;;) {
201 WDT_HIT();
202
cf69eca0 203 if (usb_poll()) {
204 rx_len = usb_read(rx,sizeof(UsbCommand));
205 if (rx_len)
206 UsbPacketReceived(rx,rx_len);
207 }
28fdb04f 208
15c4dc5a 209 if(!externally_entered && !BUTTON_PRESS()) {
210 /* Perform a reset to leave flash mode */
cf69eca0 211 usb_disable();
15c4dc5a 212 LED_B_ON();
213 AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
cf69eca0 214 for(;;)
215 ;
15c4dc5a 216 }
217 if(externally_entered && BUTTON_PRESS()) {
218 /* Let the user's button press override the automatic leave */
219 externally_entered = 0;
220 }
221 }
222}
223
28fdb04f 224extern uint32_t _osimage_entry;
15c4dc5a 225void BootROM(void)
226{
227 //------------
228 // First set up all the I/O pins; GPIOs configured directly, other ones
229 // just need to be assigned to the appropriate peripheral.
230
231 // Kill all the pullups, especially the one on USB D+; leave them for
232 // the unused pins, though.
233 AT91C_BASE_PIOA->PIO_PPUDR =
234 GPIO_USB_PU |
235 GPIO_LED_A |
236 GPIO_LED_B |
237 GPIO_LED_C |
238 GPIO_LED_D |
239 GPIO_FPGA_DIN |
240 GPIO_FPGA_DOUT |
241 GPIO_FPGA_CCLK |
242 GPIO_FPGA_NINIT |
243 GPIO_FPGA_NPROGRAM |
244 GPIO_FPGA_DONE |
245 GPIO_MUXSEL_HIPKD |
246 GPIO_MUXSEL_HIRAW |
247 GPIO_MUXSEL_LOPKD |
248 GPIO_MUXSEL_LORAW |
249 GPIO_RELAY |
250 GPIO_NVDD_ON;
251 // (and add GPIO_FPGA_ON)
252 // These pins are outputs
253 AT91C_BASE_PIOA->PIO_OER =
254 GPIO_LED_A |
255 GPIO_LED_B |
256 GPIO_LED_C |
257 GPIO_LED_D |
258 GPIO_RELAY |
259 GPIO_NVDD_ON;
260 // PIO controls the following pins
261 AT91C_BASE_PIOA->PIO_PER =
262 GPIO_USB_PU |
263 GPIO_LED_A |
264 GPIO_LED_B |
265 GPIO_LED_C |
266 GPIO_LED_D;
267
28fdb04f 268// USB_D_PLUS_PULLUP_OFF();
cf69eca0 269 usb_disable();
270 LED_D_OFF();
271 LED_C_ON();
272 LED_B_OFF();
273 LED_A_OFF();
15c4dc5a 274
07bc72b8 275 AT91C_BASE_EFC0->EFC_FMR = AT91C_MC_FWS_1FWS | MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
5a085457 276#ifdef HAS_512_FLASH
07bc72b8 277 AT91C_BASE_EFC1->EFC_FMR = AT91C_MC_FWS_1FWS | MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
5a085457 278#endif
15c4dc5a 279 // Initialize all system clocks
280 ConfigClocks();
281
282 LED_A_ON();
283
284 int common_area_present = 0;
285 switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
286 case AT91C_RSTC_RSTTYP_WATCHDOG:
287 case AT91C_RSTC_RSTTYP_SOFTWARE:
288 case AT91C_RSTC_RSTTYP_USER:
289 /* In these cases the common_area in RAM should be ok, retain it if it's there */
290 if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
291 common_area_present = 1;
292 }
293 break;
294 default: /* Otherwise, initialize it from scratch */
295 break;
296 }
297
298 if(!common_area_present){
299 /* Common area not ok, initialize it */
cf69eca0 300 int i;
301 /* Makeshift memset, no need to drag util.c into this */
302 for(i=0; i<sizeof(common_area); i++)
15c4dc5a 303 ((char*)&common_area)[i] = 0;
cf69eca0 304
15c4dc5a 305 common_area.magic = COMMON_AREA_MAGIC;
306 common_area.version = 1;
307 common_area.flags.bootrom_present = 1;
308 }
309
310 common_area.flags.bootrom_present = 1;
311 if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
312 common_area.command = COMMON_AREA_COMMAND_NONE;
313 flash_mode(1);
314 } else if(BUTTON_PRESS()) {
315 flash_mode(0);
28fdb04f 316 } else if(_osimage_entry == 0xffffffffU) {
15c4dc5a 317 flash_mode(1);
318 } else {
319 // jump to Flash address of the osimage entry point (LSBit set for thumb mode)
902cb3c0 320 __asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
15c4dc5a 321 }
322}
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