[proxmark3-svn] / armsrc / util.c

//-----------------------------------------------------------------------------
// Jonathan Westhues, Sept 2005
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Utility functions used in many places, not specific to any piece of code.
//-----------------------------------------------------------------------------

#include "proxmark3.h"
#include "util.h"
#include "string.h"
#include "apps.h"

size_t nbytes(size_t nbits) {
	return (nbits/8)+((nbits%8)>0);
}

uint32_t SwapBits(uint32_t value, int nrbits) {
	int i;
	uint32_t newvalue = 0;
	for(i = 0; i < nrbits; i++) {
		newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
	}
	return newvalue;
}

void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
{
	while (len--) {
		dest[len] = (uint8_t) n;
		n >>= 8;
	}
}

uint64_t bytes_to_num(uint8_t* src, size_t len)
{
	uint64_t num = 0;
	while (len--)
	{
		num = (num << 8) | (*src);
		src++;
	}
	return num;
}

void LEDsoff()
{
	LED_A_OFF();
	LED_B_OFF();
	LED_C_OFF();
	LED_D_OFF();
}

// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
void LED(int led, int ms)
{
	if (led & LED_RED)
		LED_C_ON();
	if (led & LED_ORANGE)
		LED_A_ON();
	if (led & LED_GREEN)
		LED_B_ON();
	if (led & LED_RED2)
		LED_D_ON();

	if (!ms)
		return;

	SpinDelay(ms);

	if (led & LED_RED)
		LED_C_OFF();
	if (led & LED_ORANGE)
		LED_A_OFF();
	if (led & LED_GREEN)
		LED_B_OFF();
	if (led & LED_RED2)
		LED_D_OFF();
}


// Determine if a button is double clicked, single clicked,
// not clicked, or held down (for ms || 1sec)
// In general, don't use this function unless you expect a
// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
int BUTTON_CLICKED(int ms)
{
	// Up to 500ms in between clicks to mean a double click
	int ticks = (48000 * (ms ? ms : 1000)) >> 10;

	// If we're not even pressed, forget about it!
	if (!BUTTON_PRESS())
		return BUTTON_NO_CLICK;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	int letoff = 0;
	for(;;)
	{
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

		// We haven't let off the button yet
		if (!letoff)
		{
			// We just let it off!
			if (!BUTTON_PRESS())
			{
				letoff = 1;

				// reset our timer for 500ms
				start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
				ticks = (48000 * (500)) >> 10;
			}

			// Still haven't let it off
			else
				// Have we held down a full second?
				if (now == (uint16_t)(start + ticks))
					return BUTTON_HOLD;
		}

		// We already let off, did we click again?
		else
			// Sweet, double click!
			if (BUTTON_PRESS())
				return BUTTON_DOUBLE_CLICK;

			// Have we ran out of time to double click?
			else
				if (now == (uint16_t)(start + ticks))
					// At least we did a single click
					return BUTTON_SINGLE_CLICK;

		WDT_HIT();
	}

	// We should never get here
	return BUTTON_ERROR;
}

// Determine if a button is held down
int BUTTON_HELD(int ms)
{
	// If button is held for one second
	int ticks = (48000 * (ms ? ms : 1000)) >> 10;

	// If we're not even pressed, forget about it!
	if (!BUTTON_PRESS())
		return BUTTON_NO_CLICK;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	for(;;)
	{
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

		// As soon as our button let go, we didn't hold long enough
		if (!BUTTON_PRESS())
			return BUTTON_SINGLE_CLICK;

		// Have we waited the full second?
		else
			if (now == (uint16_t)(start + ticks))
				return BUTTON_HOLD;

		WDT_HIT();
	}

	// We should never get here
	return BUTTON_ERROR;
}

// attempt at high resolution microsecond timer
// beware: timer counts in 21.3uS increments (1024/48Mhz)
void SpinDelayUs(int us)
{
	int ticks = (48*us) >> 10;

	// Borrow a PWM unit for my real-time clock
	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	// 48 MHz / 1024 gives 46.875 kHz
	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;

	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;

	for(;;) {
		uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
		if (now == (uint16_t)(start + ticks))
			return;

		WDT_HIT();
	}
}

void SpinDelay(int ms)
{
  // convert to uS and call microsecond delay function
	SpinDelayUs(ms*1000);
}

/* Similar to FpgaGatherVersion this formats stored version information
 * into a string representation. It takes a pointer to the struct version_information,
 * verifies the magic properties, then stores a formatted string, prefixed by
 * prefix in dst.
 */
void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
{
	struct version_information *v = (struct version_information*)version_information;
	dst[0] = 0;
	strncat(dst, prefix, len);
	if(v->magic != VERSION_INFORMATION_MAGIC) {
		strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);
		return;
	}
	if(v->versionversion != 1) {
		strncat(dst, "Version information not understood", len - strlen(dst) - 1);
		return;
	}
	if(!v->present) {
		strncat(dst, "Version information not available", len - strlen(dst) - 1);
		return;
	}

	strncat(dst, v->gitversion, len - strlen(dst) - 1);
	if(v->clean == 0) {
		strncat(dst, "-unclean", len - strlen(dst) - 1);
	} else if(v->clean == 2) {
		strncat(dst, "-suspect", len - strlen(dst) - 1);
	}

	strncat(dst, " ", len - strlen(dst) - 1);
	strncat(dst, v->buildtime, len - strlen(dst) - 1);
}

//  -------------------------------------------------------------------------
//  timer lib
//  -------------------------------------------------------------------------
//  test procedure:
//
//	ti = GetTickCount();
//	SpinDelay(1000);
//	ti = GetTickCount() - ti;
//	Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());

void StartTickCount()
{
//  must be 0x40, but on my cpu - included divider is optimal
//  0x20 - 1 ms / bit 
//  0x40 - 2 ms / bit

	AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B
}

/*
* Get the current count.
*/
uint32_t RAMFUNC GetTickCount(){
	return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
}

//  -------------------------------------------------------------------------
//  microseconds timer 
//  -------------------------------------------------------------------------
void StartCountUS()
{
	AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
//	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;

	// fast clock
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
														AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
														AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
	AT91C_BASE_TC0->TC_RA = 1;
	AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
	
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
	
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
	AT91C_BASE_TCB->TCB_BCR = 1;
	}

uint32_t RAMFUNC GetCountUS(){
	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
}

static uint32_t GlobalUsCounter = 0;

uint32_t RAMFUNC GetDeltaCountUS(){
	uint32_t g_cnt = GetCountUS();
	uint32_t g_res = g_cnt - GlobalUsCounter;
	GlobalUsCounter = g_cnt;
	return g_res;
}


//  -------------------------------------------------------------------------
//  Timer for iso14443 commands. Uses ssp_clk from FPGA 
//  -------------------------------------------------------------------------
void StartCountSspClk()
{
	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 		// XC0 Clock = TIOA1
							| AT91C_TCB_TC1XC1S_NONE 		// XC1 Clock = none
							| AT91C_TCB_TC2XC2S_TIOA0;		// XC2 Clock = TIOA0

	// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; 				// disable TC1
	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
							| AT91C_TC_CPCSTOP				// Stop clock on RC compare
							| AT91C_TC_EEVTEDG_RISING		// Trigger on rising edge of Event
							| AT91C_TC_EEVT_TIOB			// Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
							| AT91C_TC_ENETRG				// Enable external trigger event
							| AT91C_TC_WAVESEL_UP	 		// Upmode without automatic trigger on RC compare
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_AEEVT_SET 			// Set TIOA1 on external event
							| AT91C_TC_ACPC_CLEAR; 			// Clear TIOA1 on RC Compare
	AT91C_BASE_TC1->TC_RC = 0x04; 							// RC Compare value = 0x04

	// use TC0 to count TIOA1 pulses
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;				// disable TC0
	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0	 			// TC0 clock = XC0 clock = TIOA1
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_WAVESEL_UP	 		// just count
							| AT91C_TC_ACPA_CLEAR 			// Clear TIOA0 on RA Compare
							| AT91C_TC_ACPC_SET; 			// Set TIOA0 on RC Compare
	AT91C_BASE_TC0->TC_RA = 1;								// RA Compare value = 1; pulse width to TC2
	AT91C_BASE_TC0->TC_RC = 0; 								// RC Compare value = 0; increment TC2 on overflow

	// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; 				// disable TC2  
	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2	 			// TC2 clock = XC2 clock = TIOA0
							| AT91C_TC_WAVE 				// Waveform Mode
							| AT91C_TC_WAVESEL_UP;	 		// just count
	
	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;				// enable TC0
	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;				// enable TC1
	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;				// enable TC2

	//
	// synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
	//
	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); 	// wait for ssp_frame to go high (start of frame)
	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); 		// wait for ssp_frame to be low
	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); 	// wait for ssp_clk to go high
	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
	AT91C_BASE_TCB->TCB_BCR = 1;							// assert Sync (set all timers to 0 on next active clock edge)
	// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
	// (just started with the transfer of the 4th Bit).
	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
	// we can use the counter.
	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
}


uint32_t RAMFUNC GetCountSspClk(){
	uint32_t tmp_count;
	tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
	if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
		return (AT91C_BASE_TC2->TC_CV << 16);
	} 
	else {
		return tmp_count;
	}
}
Commit	Line	Data
e30c654b	1	//-----------------------------------------------------------------------------
e30c654b	2	// Jonathan Westhues, Sept 2005
bd20f8f4	3	//
	4	// This code is licensed to you under the terms of the GNU GPL, version 2 or,
	5	// at your option, any later version. See the LICENSE.txt file for the text of
	6	// the license.
	7	//-----------------------------------------------------------------------------
	8	// Utility functions used in many places, not specific to any piece of code.
e30c654b	9	//-----------------------------------------------------------------------------
bd20f8f4	10
e30c654b	11	#include "proxmark3.h"
f7e3ed82	12	#include "util.h"
9ab7a6c7	13	#include "string.h"
9492e0b0	14	#include "apps.h"
e30c654b	15
195af472	16	size_t nbytes(size_t nbits) {
	17	return (nbits/8)+((nbits%8)>0);
	18	}
	19
81cd0474	20	uint32_t SwapBits(uint32_t value, int nrbits) {
	21	int i;
	22	uint32_t newvalue = 0;
	23	for(i = 0; i < nrbits; i++) {
	24	newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
	25	}
	26	return newvalue;
	27	}
	28
f7e3ed82	29	void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
e30c654b	30	{
e30c654b	31	while (len--) {
f7e3ed82	32	dest[len] = (uint8_t) n;
e30c654b	33	n >>= 8;
	34	}
	35	}
	36
f7e3ed82	37	uint64_t bytes_to_num(uint8_t* src, size_t len)
e30c654b	38	{
	39	uint64_t num = 0;
	40	while (len--)
	41	{
	42	num = (num << 8) \| (*src);
	43	src++;
	44	}
	45	return num;
	46	}
	47
	48	void LEDsoff()
	49	{
	50	LED_A_OFF();
	51	LED_B_OFF();
	52	LED_C_OFF();
	53	LED_D_OFF();
	54	}
	55
	56	// LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
	57	void LED(int led, int ms)
	58	{
	59	if (led & LED_RED)
	60	LED_C_ON();
	61	if (led & LED_ORANGE)
	62	LED_A_ON();
	63	if (led & LED_GREEN)
	64	LED_B_ON();
	65	if (led & LED_RED2)
	66	LED_D_ON();
	67
	68	if (!ms)
	69	return;
	70
	71	SpinDelay(ms);
	72
	73	if (led & LED_RED)
	74	LED_C_OFF();
	75	if (led & LED_ORANGE)
	76	LED_A_OFF();
	77	if (led & LED_GREEN)
	78	LED_B_OFF();
	79	if (led & LED_RED2)
	80	LED_D_OFF();
	81	}
	82
	83
	84	// Determine if a button is double clicked, single clicked,
	85	// not clicked, or held down (for ms \|\| 1sec)
	86	// In general, don't use this function unless you expect a
	87	// double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
	88	int BUTTON_CLICKED(int ms)
	89	{
	90	// Up to 500ms in between clicks to mean a double click
	91	int ticks = (48000 * (ms ? ms : 1000)) >> 10;
	92
	93	// If we're not even pressed, forget about it!
	94	if (!BUTTON_PRESS())
	95	return BUTTON_NO_CLICK;
	96
	97	// Borrow a PWM unit for my real-time clock
	98	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	99	// 48 MHz / 1024 gives 46.875 kHz
	100	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	101	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
102	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
103
f7e3ed82	104	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	105
	106	int letoff = 0;
	107	for(;;)
	108	{
f7e3ed82	109	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	110
	111	// We haven't let off the button yet
	112	if (!letoff)
	113	{
	114	// We just let it off!
	115	if (!BUTTON_PRESS())
	116	{
	117	letoff = 1;
	118
	119	// reset our timer for 500ms
	120	start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
	121	ticks = (48000 * (500)) >> 10;
	122	}
	123
	124	// Still haven't let it off
	125	else
	126	// Have we held down a full second?
f7e3ed82	127	if (now == (uint16_t)(start + ticks))
e30c654b	128	return BUTTON_HOLD;
	129	}
	130
	131	// We already let off, did we click again?
	132	else
	133	// Sweet, double click!
	134	if (BUTTON_PRESS())
	135	return BUTTON_DOUBLE_CLICK;
	136
	137	// Have we ran out of time to double click?
	138	else
f7e3ed82	139	if (now == (uint16_t)(start + ticks))
e30c654b	140	// At least we did a single click
	141	return BUTTON_SINGLE_CLICK;
	142
	143	WDT_HIT();
	144	}
	145
	146	// We should never get here
	147	return BUTTON_ERROR;
	148	}
	149
	150	// Determine if a button is held down
	151	int BUTTON_HELD(int ms)
	152	{
	153	// If button is held for one second
	154	int ticks = (48000 * (ms ? ms : 1000)) >> 10;
	155
	156	// If we're not even pressed, forget about it!
	157	if (!BUTTON_PRESS())
	158	return BUTTON_NO_CLICK;
	159
	160	// Borrow a PWM unit for my real-time clock
	161	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	162	// 48 MHz / 1024 gives 46.875 kHz
	163	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	164	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	165	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
	166
f7e3ed82	167	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	168
	169	for(;;)
	170	{
f7e3ed82	171	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	172
	173	// As soon as our button let go, we didn't hold long enough
	174	if (!BUTTON_PRESS())
	175	return BUTTON_SINGLE_CLICK;
	176
	177	// Have we waited the full second?
	178	else
f7e3ed82	179	if (now == (uint16_t)(start + ticks))
e30c654b	180	return BUTTON_HOLD;
	181
	182	WDT_HIT();
	183	}
	184
	185	// We should never get here
	186	return BUTTON_ERROR;
	187	}
	188
	189	// attempt at high resolution microsecond timer
	190	// beware: timer counts in 21.3uS increments (1024/48Mhz)
	191	void SpinDelayUs(int us)
	192	{
	193	int ticks = (48*us) >> 10;
	194
	195	// Borrow a PWM unit for my real-time clock
	196	AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
	197	// 48 MHz / 1024 gives 46.875 kHz
	198	AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
	199	AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
	200	AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
	201
f7e3ed82	202	uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
e30c654b	203
e30c654b	204	for(;;) {
f7e3ed82	205	uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
f7e3ed82	206	if (now == (uint16_t)(start + ticks))
e30c654b	207	return;
	208
	209	WDT_HIT();
	210	}
	211	}
	212
	213	void SpinDelay(int ms)
	214	{
	215	// convert to uS and call microsecond delay function
	216	SpinDelayUs(ms*1000);
	217	}
	218
	219	/* Similar to FpgaGatherVersion this formats stored version information
	220	* into a string representation. It takes a pointer to the struct version_information,
	221	* verifies the magic properties, then stores a formatted string, prefixed by
	222	* prefix in dst.
	223	*/
	224	void FormatVersionInformation(char dst, int len, const char prefix, void *version_information)
	225	{
	226	struct version_information v = (struct version_information)version_information;
	227	dst[0] = 0;
	228	strncat(dst, prefix, len);
	229	if(v->magic != VERSION_INFORMATION_MAGIC) {
cba867f2	230	strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);
e30c654b	231	return;
	232	}
	233	if(v->versionversion != 1) {
cba867f2	234	strncat(dst, "Version information not understood", len - strlen(dst) - 1);
e30c654b	235	return;
	236	}
	237	if(!v->present) {
cba867f2	238	strncat(dst, "Version information not available", len - strlen(dst) - 1);
e30c654b	239	return;
	240	}
	241
cba867f2	242	strncat(dst, v->gitversion, len - strlen(dst) - 1);
e30c654b	243	if(v->clean == 0) {
cba867f2	244	strncat(dst, "-unclean", len - strlen(dst) - 1);
e30c654b	245	} else if(v->clean == 2) {
cba867f2	246	strncat(dst, "-suspect", len - strlen(dst) - 1);
e30c654b	247	}
e30c654b	248
cba867f2 MHS	249	strncat(dst, " ", len - strlen(dst) - 1);
cba867f2 MHS	250	strncat(dst, v->buildtime, len - strlen(dst) - 1);
e30c654b	251	}
9ca155ba M	252
	253	// -------------------------------------------------------------------------
	254	// timer lib
	255	// -------------------------------------------------------------------------
	256	// test procedure:
	257	//
	258	// ti = GetTickCount();
	259	// SpinDelay(1000);
	260	// ti = GetTickCount() - ti;
	261	// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
	262
	263	void StartTickCount()
	264	{
	265	// must be 0x40, but on my cpu - included divider is optimal
	266	// 0x20 - 1 ms / bit
	267	// 0x40 - 2 ms / bit
	268
0a39986e	269	AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B
9ca155ba M	270	}
	271
	272	/*
	273	* Get the current count.
	274	*/
	275	uint32_t RAMFUNC GetTickCount(){
8f51ddb0	276	return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
9ca155ba M	277	}
9ca155ba M	278
8f51ddb0 M	279	// -------------------------------------------------------------------------
	280	// microseconds timer
	281	// -------------------------------------------------------------------------
	282	void StartCountUS()
	283	{
	284	AT91C_BASE_PMC->PMC_PCER \|= (0x1 << 12) \| (0x1 << 13) \| (0x1 << 14);
	285	// AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
	286	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE \| AT91C_TCB_TC1XC1S_TIOA0 \| AT91C_TCB_TC2XC2S_NONE;
	287
	288	// fast clock
	289	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	290	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK \| // MCK(48MHz)/32 -- tick=1.5mks
	291	AT91C_TC_WAVE \| AT91C_TC_WAVESEL_UP_AUTO \| AT91C_TC_ACPA_CLEAR \|
	292	AT91C_TC_ACPC_SET \| AT91C_TC_ASWTRG_SET;
	293	AT91C_BASE_TC0->TC_RA = 1;
	294	AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
	295
	296	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
	297	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
1c611bbd	298
8f51ddb0 M	299	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
	300	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
	301	AT91C_BASE_TCB->TCB_BCR = 1;
1c611bbd	302	}
8f51ddb0 M	303
	304	uint32_t RAMFUNC GetCountUS(){
	305	return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
	306	}
	307
	308	static uint32_t GlobalUsCounter = 0;
	309
	310	uint32_t RAMFUNC GetDeltaCountUS(){
	311	uint32_t g_cnt = GetCountUS();
	312	uint32_t g_res = g_cnt - GlobalUsCounter;
	313	GlobalUsCounter = g_cnt;
	314	return g_res;
	315	}
	316
	317
1c611bbd	318	// -------------------------------------------------------------------------
7bc95e2e	319	// Timer for iso14443 commands. Uses ssp_clk from FPGA
1c611bbd	320	// -------------------------------------------------------------------------
7bc95e2e	321	void StartCountSspClk()
1c611bbd	322	{
	323	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) \| (1 << AT91C_ID_TC1) \| (1 << AT91C_ID_TC2); // Enable Clock to all timers
	324	AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
	325	\| AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
	326	\| AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
	327
	328	// configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
	329	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
	330	AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
	331	\| AT91C_TC_CPCSTOP // Stop clock on RC compare
	332	\| AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
7bc95e2e	333	\| AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
1c611bbd	334	\| AT91C_TC_ENETRG // Enable external trigger event
	335	\| AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
	336	\| AT91C_TC_WAVE // Waveform Mode
	337	\| AT91C_TC_AEEVT_SET // Set TIOA1 on external event
	338	\| AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
	339	AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
	340
	341	// use TC0 to count TIOA1 pulses
7bc95e2e	342	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
1c611bbd	343	AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
	344	\| AT91C_TC_WAVE // Waveform Mode
	345	\| AT91C_TC_WAVESEL_UP // just count
	346	\| AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
	347	\| AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
	348	AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
	349	AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
	350
	351	// use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
	352	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
	353	AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
	354	\| AT91C_TC_WAVE // Waveform Mode
	355	\| AT91C_TC_WAVESEL_UP; // just count
	356
1c611bbd	357	AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
	358	AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
	359	AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
9492e0b0	360
7bc95e2e	361	//
	362	// synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present
	363	//
	364	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
9492e0b0	365	while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
7bc95e2e	366	while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
	367	// note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
	368	// it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
1c611bbd	369	AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
7bc95e2e	370	// at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
	371	// at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
	372	// whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
	373	// (just started with the transfer of the 4th Bit).
	374	// The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
	375	// we can use the counter.
	376	while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
1c611bbd	377	}
	378
	379
7bc95e2e	380	uint32_t RAMFUNC GetCountSspClk(){
1c611bbd	381	uint32_t tmp_count;
1c611bbd	382	tmp_count = (AT91C_BASE_TC2->TC_CV << 16) \| AT91C_BASE_TC0->TC_CV;
7bc95e2e	383	if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
1c611bbd	384	return (AT91C_BASE_TC2->TC_CV << 16);
	385	}
	386	else {
	387	return tmp_count;
	388	}
	389	}
7bc95e2e	390
7bc95e2e	391