[proxmark3-svn] / fpga / testbed_lo_read.v

`include "lo_read.v"\r
/*\r
	pck0			- input main 24Mhz clock (PLL / 4)\r
	[7:0] adc_d		- input data from A/D converter\r
	lo_is_125khz	- input freq selector (1=125Khz, 0=136Khz)\r
\r
	pwr_lo			- output to coil drivers (ssp_clk / 8)\r
	adc_clk			- output A/D clock signal\r
	ssp_frame		- output SSS frame indicator (goes high while the 8 bits are shifted)\r
	ssp_din			- output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
	ssp_clk			- output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )\r
\r
	ck_1356meg		- input unused\r
	ck_1356megb		- input unused\r
	ssp_dout		- input unused\r
	cross_hi		- input unused\r
	cross_lo		- input unused\r
\r
	pwr_hi			- output unused, tied low\r
	pwr_oe1			- output unused, undefined\r
	pwr_oe2			- output unused, undefined\r
	pwr_oe3			- output unused, undefined\r
	pwr_oe4			- output unused, undefined\r
	dbg				- output alias for adc_clk\r
*/\r
\r
module testbed_lo_read;\r
	reg  pck0;\r
	reg  [7:0] adc_d;\r
	reg  lo_is_125khz;\r
	reg [15:0] divisor;\r
\r
	wire pwr_lo;\r
	wire adc_clk;\r
	wire ck_1356meg;\r
	wire ck_1356megb;\r
	wire ssp_frame;\r
	wire ssp_din;\r
	wire ssp_clk;\r
	reg ssp_dout;\r
	wire pwr_hi;\r
	wire pwr_oe1;\r
	wire pwr_oe2;\r
	wire pwr_oe3;\r
	wire pwr_oe4;\r
	wire cross_lo;\r
	wire cross_hi;\r
	wire dbg;\r
\r
	lo_read #(5,10) dut(\r
	.pck0(pck0),\r
	.ck_1356meg(ck_1356meg),\r
	.ck_1356megb(ck_1356megb),\r
	.pwr_lo(pwr_lo),\r
	.pwr_hi(pwr_hi),\r
	.pwr_oe1(pwr_oe1),\r
	.pwr_oe2(pwr_oe2),\r
	.pwr_oe3(pwr_oe3),\r
	.pwr_oe4(pwr_oe4),\r
	.adc_d(adc_d),\r
	.adc_clk(adc_clk),\r
	.ssp_frame(ssp_frame),\r
	.ssp_din(ssp_din),\r
	.ssp_dout(ssp_dout),\r
	.ssp_clk(ssp_clk),\r
	.cross_hi(cross_hi),\r
	.cross_lo(cross_lo),\r
	.dbg(dbg),\r
	.lo_is_125khz(lo_is_125khz),\r
	.divisor(divisor)\r
	);\r
\r
	integer idx, i, adc_val=8;\r
\r
	// main clock\r
	always #5 pck0 = !pck0;\r
\r
	task crank_dut;\r
	begin\r
		@(posedge adc_clk) ;\r
		adc_d = adc_val;\r
		adc_val = (adc_val *2) + 53;\r
	end\r
	endtask\r
\r
	initial begin\r
\r
		// init inputs\r
		pck0 = 0;\r
		adc_d = 0;\r
		ssp_dout = 0;\r
		lo_is_125khz = 1;\r
		divisor = 255;  //min 16, 95=125Khz, max 255\r
\r
		// simulate 4 A/D cycles at 125Khz\r
		for (i = 0 ;  i < 8 ;  i = i + 1) begin\r
			crank_dut;\r
		end\r
		$finish;\r
	end\r
endmodule // main\r
Commit	Line	Data
6658905f	1	`include "lo_read.v"\r
6658905f	2	/*\r
	3	pck0 - input main 24Mhz clock (PLL / 4)\r
	4	[7:0] adc_d - input data from A/D converter\r
	5	lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)\r
	6	\r
	7	pwr_lo - output to coil drivers (ssp_clk / 8)\r
	8	adc_clk - output A/D clock signal\r
	9	ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)\r
	10	ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
	11	ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )\r
	12	\r
	13	ck_1356meg - input unused\r
	14	ck_1356megb - input unused\r
	15	ssp_dout - input unused\r
	16	cross_hi - input unused\r
	17	cross_lo - input unused\r
	18	\r
	19	pwr_hi - output unused, tied low\r
	20	pwr_oe1 - output unused, undefined\r
	21	pwr_oe2 - output unused, undefined\r
	22	pwr_oe3 - output unused, undefined\r
	23	pwr_oe4 - output unused, undefined\r
	24	dbg - output alias for adc_clk\r
	25	*/\r
	26	\r
	27	module testbed_lo_read;\r
	28	reg pck0;\r
	29	reg [7:0] adc_d;\r
	30	reg lo_is_125khz;\r
30f2a7d3	31	reg [15:0] divisor;\r
6658905f	32	\r
	33	wire pwr_lo;\r
	34	wire adc_clk;\r
	35	wire ck_1356meg;\r
	36	wire ck_1356megb;\r
	37	wire ssp_frame;\r
	38	wire ssp_din;\r
	39	wire ssp_clk;\r
1c38843b	40	reg ssp_dout;\r
6658905f	41	wire pwr_hi;\r
	42	wire pwr_oe1;\r
	43	wire pwr_oe2;\r
	44	wire pwr_oe3;\r
	45	wire pwr_oe4;\r
	46	wire cross_lo;\r
	47	wire cross_hi;\r
	48	wire dbg;\r
	49	\r
1c38843b	50	lo_read #(5,10) dut(\r
6658905f	51	.pck0(pck0),\r
1c38843b	52	.ck_1356meg(ck_1356meg),\r
	53	.ck_1356megb(ck_1356megb),\r
	54	.pwr_lo(pwr_lo),\r
	55	.pwr_hi(pwr_hi),\r
	56	.pwr_oe1(pwr_oe1),\r
	57	.pwr_oe2(pwr_oe2),\r
	58	.pwr_oe3(pwr_oe3),\r
	59	.pwr_oe4(pwr_oe4),\r
6658905f	60	.adc_d(adc_d),\r
6658905f	61	.adc_clk(adc_clk),\r
1c38843b	62	.ssp_frame(ssp_frame),\r
	63	.ssp_din(ssp_din),\r
	64	.ssp_dout(ssp_dout),\r
	65	.ssp_clk(ssp_clk),\r
	66	.cross_hi(cross_hi),\r
	67	.cross_lo(cross_lo),\r
	68	.dbg(dbg),\r
30f2a7d3	69	.lo_is_125khz(lo_is_125khz),\r
	70	.divisor(divisor)\r
	71	);\r
	72	\r
	73	integer idx, i, adc_val=8;\r
6658905f	74	\r
	75	// main clock\r
	76	always #5 pck0 = !pck0;\r
	77	\r
6658905f	78	task crank_dut;\r
	79	begin\r
	80	@(posedge adc_clk) ;\r
30f2a7d3	81	adc_d = adc_val;\r
30f2a7d3	82	adc_val = (adc_val *2) + 53;\r
6658905f	83	end\r
	84	endtask\r
	85	\r
	86	initial begin\r
	87	\r
	88	// init inputs\r
	89	pck0 = 0;\r
	90	adc_d = 0;\r
1c38843b	91	ssp_dout = 0;\r
30f2a7d3	92	lo_is_125khz = 1;\r
1c38843b	93	divisor = 255; //min 16, 95=125Khz, max 255\r
6658905f	94	\r
6658905f	95	// simulate 4 A/D cycles at 125Khz\r
30f2a7d3	96	for (i = 0 ; i < 8 ; i = i + 1) begin\r
6658905f	97	crank_dut;\r
	98	end\r
	99	$finish;\r
	100	end\r
6658905f	101	endmodule // main\r