[proxmark3-svn] / bootrom / bootrom.c

//-----------------------------------------------------------------------------
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Main code for the bootloader
//-----------------------------------------------------------------------------

#include <proxmark3.h>
#include "usb_cdc.h"
#include "cmd.h"
//#include "usb_hid.h"

void DbpString(char *str) {
  byte_t len = 0;
  while (str[len] != 0x00) {
    len++;
  }
  cmd_send(CMD_DEBUG_PRINT_STRING,len,0,0,(byte_t*)str,len);
}

struct common_area common_area __attribute__((section(".commonarea")));
unsigned int start_addr, end_addr, bootrom_unlocked;
extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;

static void ConfigClocks(void)
{
    // we are using a 16 MHz crystal as the basis for everything
    // slow clock runs at 32Khz typical regardless of crystal

    // enable system clock and USB clock
    AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;

	// enable the clock to the following peripherals
    AT91C_BASE_PMC->PMC_PCER =
		(1<<AT91C_ID_PIOA)	|
		(1<<AT91C_ID_ADC)	|
		(1<<AT91C_ID_SPI)	|
		(1<<AT91C_ID_SSC)	|
		(1<<AT91C_ID_PWMC)	|
		(1<<AT91C_ID_UDP);

	// worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
	// if SLCK slow clock runs at its worst case (max) frequency of 42khz
	// max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8

	// enable main oscillator and set startup delay
    AT91C_BASE_PMC->PMC_MOR =
        AT91C_CKGR_MOSCEN |
        PMC_MAIN_OSC_STARTUP_DELAY(8);

	// wait for main oscillator to stabilize
	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
		;

    // PLL output clock frequency in range  80 - 160 MHz needs CKGR_PLL = 00
    // PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
    // PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
    AT91C_BASE_PMC->PMC_PLLR =
    	PMC_PLL_DIVISOR(2) |
		PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
		PMC_PLL_FREQUENCY_RANGE(0) |
		PMC_PLL_MULTIPLIER(12) |
		PMC_PLL_USB_DIVISOR(1);

	// wait for PLL to lock
	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
		;

	// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
	// datasheet recommends that this register is programmed in two operations
	// when changing to PLL, program the prescaler first then the source
    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;

	// wait for main clock ready signal
	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
		;

	// set the source to PLL
    AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;

	// wait for main clock ready signal
	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
		;
}

static void Fatal(void)
{
  for(;;);
}

void UsbPacketReceived(uint8_t *packet, int len) {
  int i, dont_ack=0;
  UsbCommand* c = (UsbCommand *)packet;
  volatile uint32_t *p;
  
  if(len != sizeof(UsbCommand)) {
    Fatal();
  }
  
  uint32_t arg0 = (uint32_t)c->arg[0];
  
  switch(c->cmd) {
    case CMD_DEVICE_INFO: {
      dont_ack = 1;
      arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT | DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM |
      DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
      if(common_area.flags.osimage_present) {
        arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
      }
      cmd_send(CMD_DEVICE_INFO,arg0,1,2,0,0);
    } break;
      
    case CMD_SETUP_WRITE: {
      /* The temporary write buffer of the embedded flash controller is mapped to the
       * whole memory region, only the last 8 bits are decoded.
       */
      p = (volatile uint32_t *)&_flash_start;
      for(i = 0; i < 12; i++) {
        p[i+arg0] = c->d.asDwords[i];
      }
    } break;
      
    case CMD_FINISH_WRITE: {
      uint32_t* flash_mem = (uint32_t*)(&_flash_start);
      for (size_t j=0; j<2; j++) {
        for(i = 0+(64*j); i < 64+(64*j); i++) {
          flash_mem[i] = c->d.asDwords[i];
        }
        
        uint32_t flash_address = arg0 + (0x100*j);
        
        /* Check that the address that we are supposed to write to is within our allowed region */
        if( ((flash_address+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (flash_address < start_addr) ) {
          /* Disallow write */
          dont_ack = 1;
          cmd_send(CMD_NACK,0,0,0,0,0);
        } else {
          uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
          /* Translate address to flash page and do flash, update here for the 512k part */
          AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
          MC_FLASH_COMMAND_PAGEN(page_n) |
          AT91C_MC_FCMD_START_PROG;
        }
        
        // Wait until flashing of page finishes
        uint32_t sr;
        while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
        if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
          dont_ack = 1;
          cmd_send(CMD_NACK,0,0,0,0,0);
        }
      }
    } break;
      
    case CMD_HARDWARE_RESET: {
      usb_disable();
      AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
    } break;
      
    case CMD_START_FLASH: {
      if(c->arg[2] == START_FLASH_MAGIC) bootrom_unlocked = 1;
      else bootrom_unlocked = 0;
      {
        int prot_start = (int)&_bootrom_start;
        int prot_end = (int)&_bootrom_end;
        int allow_start = (int)&_flash_start;
        int allow_end = (int)&_flash_end;
        int cmd_start = c->arg[0];
        int cmd_end = c->arg[1];
        
        /* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
         * bootrom area. In any case they must be within the flash area.
         */
        if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))
           && (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
          start_addr = cmd_start;
          end_addr = cmd_end;
        } else {
          start_addr = end_addr = 0;
          dont_ack = 1;
          cmd_send(CMD_NACK,0,0,0,0,0);
        }
      }
    } break;
      
    default: {
      Fatal();
    } break;
  }
  
  if(!dont_ack) {
    cmd_send(CMD_ACK,arg0,0,0,0,0);
  }
}

static void flash_mode(int externally_entered)
{
	start_addr = 0;
	end_addr = 0;
	bootrom_unlocked = 0;
  byte_t rx[sizeof(UsbCommand)];
	size_t rx_len;

  usb_enable();
  for (volatile size_t i=0; i<0x100000; i++);

	for(;;) {
		WDT_HIT();

    if (usb_poll()) {
      rx_len = usb_read(rx,sizeof(UsbCommand));
      if (rx_len) {
        UsbPacketReceived(rx,rx_len);
      }
    }

		if(!externally_entered && !BUTTON_PRESS()) {
			/* Perform a reset to leave flash mode */
      usb_disable();
			LED_B_ON();
			AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
			for(;;);
		}
		if(externally_entered && BUTTON_PRESS()) {
			/* Let the user's button press override the automatic leave */
			externally_entered = 0;
		}
	}
}

extern uint32_t _osimage_entry;
void BootROM(void)
{
    //------------
    // First set up all the I/O pins; GPIOs configured directly, other ones
    // just need to be assigned to the appropriate peripheral.

    // Kill all the pullups, especially the one on USB D+; leave them for
    // the unused pins, though.
    AT91C_BASE_PIOA->PIO_PPUDR =
    	GPIO_USB_PU			|
		GPIO_LED_A			|
		GPIO_LED_B			|
		GPIO_LED_C			|
		GPIO_LED_D			|
		GPIO_FPGA_DIN		|
		GPIO_FPGA_DOUT		|
		GPIO_FPGA_CCLK		|
		GPIO_FPGA_NINIT		|
		GPIO_FPGA_NPROGRAM	|
		GPIO_FPGA_DONE		|
		GPIO_MUXSEL_HIPKD	|
		GPIO_MUXSEL_HIRAW	|
		GPIO_MUXSEL_LOPKD	|
		GPIO_MUXSEL_LORAW	|
		GPIO_RELAY			|
		GPIO_NVDD_ON;
		// (and add GPIO_FPGA_ON)
	// These pins are outputs
    AT91C_BASE_PIOA->PIO_OER =
    	GPIO_LED_A			|
		GPIO_LED_B			|
		GPIO_LED_C			|
		GPIO_LED_D			|
		GPIO_RELAY			|
		GPIO_NVDD_ON;
	// PIO controls the following pins
    AT91C_BASE_PIOA->PIO_PER =
    	GPIO_USB_PU			|
		GPIO_LED_A			|
		GPIO_LED_B			|
		GPIO_LED_C			|
		GPIO_LED_D;

//    USB_D_PLUS_PULLUP_OFF();
  usb_disable();
    LED_D_OFF();
    LED_C_ON();
    LED_B_OFF();
    LED_A_OFF();

	AT91C_BASE_EFC0->EFC_FMR =
		AT91C_MC_FWS_1FWS |
		MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);

    // Initialize all system clocks
    ConfigClocks();

    LED_A_ON();

    int common_area_present = 0;
    switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
    case AT91C_RSTC_RSTTYP_WATCHDOG:
    case AT91C_RSTC_RSTTYP_SOFTWARE:
    case AT91C_RSTC_RSTTYP_USER:
	    /* In these cases the common_area in RAM should be ok, retain it if it's there */
	    if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
		    common_area_present = 1;
	    }
	    break;
    default: /* Otherwise, initialize it from scratch */
	    break;
    }

    if(!common_area_present){
	    /* Common area not ok, initialize it */
	    int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
		    ((char*)&common_area)[i] = 0;
	    }
	    common_area.magic = COMMON_AREA_MAGIC;
	    common_area.version = 1;
	    common_area.flags.bootrom_present = 1;
    }

    common_area.flags.bootrom_present = 1;
    if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
	    common_area.command = COMMON_AREA_COMMAND_NONE;
	    flash_mode(1);
    } else if(BUTTON_PRESS()) {
	    flash_mode(0);
    } else if(_osimage_entry == 0xffffffffU) {
	    flash_mode(1);
    } else {
	    // jump to Flash address of the osimage entry point (LSBit set for thumb mode)
	    __asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
    }
}
Commit	Line	Data
bd20f8f4	1	//-----------------------------------------------------------------------------
	2	// This code is licensed to you under the terms of the GNU GPL, version 2 or,
	3	// at your option, any later version. See the LICENSE.txt file for the text of
	4	// the license.
	5	//-----------------------------------------------------------------------------
	6	// Main code for the bootloader
	7	//-----------------------------------------------------------------------------
	8
15c4dc5a	9	#include <proxmark3.h>
28fdb04f	10	#include "usb_cdc.h"
	11	#include "cmd.h"
	12	//#include "usb_hid.h"
	13
	14	void DbpString(char *str) {
	15	byte_t len = 0;
	16	while (str[len] != 0x00) {
	17	len++;
	18	}
	19	cmd_send(CMD_DEBUG_PRINT_STRING,len,0,0,(byte_t*)str,len);
	20	}
15c4dc5a	21
	22	struct common_area common_area __attribute__((section(".commonarea")));
	23	unsigned int start_addr, end_addr, bootrom_unlocked;
	24	extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
	25
	26	static void ConfigClocks(void)
	27	{
	28	// we are using a 16 MHz crystal as the basis for everything
	29	// slow clock runs at 32Khz typical regardless of crystal
	30
	31	// enable system clock and USB clock
	32	AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK \| AT91C_PMC_UDP;
	33
	34	// enable the clock to the following peripherals
	35	AT91C_BASE_PMC->PMC_PCER =
	36	(1<<AT91C_ID_PIOA) \|
	37	(1<<AT91C_ID_ADC) \|
	38	(1<<AT91C_ID_SPI) \|
	39	(1<<AT91C_ID_SSC) \|
	40	(1<<AT91C_ID_PWMC) \|
	41	(1<<AT91C_ID_UDP);
	42
0aa4cfc2	43	// worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
	44	// if SLCK slow clock runs at its worst case (max) frequency of 42khz
	45	// max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
15c4dc5a	46
	47	// enable main oscillator and set startup delay
	48	AT91C_BASE_PMC->PMC_MOR =
0aa4cfc2	49	AT91C_CKGR_MOSCEN \|
0aa4cfc2	50	PMC_MAIN_OSC_STARTUP_DELAY(8);
15c4dc5a	51
15c4dc5a	52	// wait for main oscillator to stabilize
0aa4cfc2	53	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
15c4dc5a	54	;
15c4dc5a	55
0aa4cfc2	56	// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
	57	// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
	58	// PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
15c4dc5a	59	AT91C_BASE_PMC->PMC_PLLR =
	60	PMC_PLL_DIVISOR(2) \|
	61	PMC_PLL_COUNT_BEFORE_LOCK(0x50) \|
	62	PMC_PLL_FREQUENCY_RANGE(0) \|
	63	PMC_PLL_MULTIPLIER(12) \|
	64	PMC_PLL_USB_DIVISOR(1);
	65
	66	// wait for PLL to lock
0aa4cfc2	67	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
15c4dc5a	68	;
	69
	70	// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
0aa4cfc2	71	// datasheet recommends that this register is programmed in two operations
15c4dc5a	72	// when changing to PLL, program the prescaler first then the source
0aa4cfc2	73	AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
15c4dc5a	74
15c4dc5a	75	// wait for main clock ready signal
0aa4cfc2	76	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
15c4dc5a	77	;
	78
	79	// set the source to PLL
0aa4cfc2	80	AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 \| AT91C_PMC_CSS_PLL_CLK;
15c4dc5a	81
15c4dc5a	82	// wait for main clock ready signal
0aa4cfc2	83	while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
15c4dc5a	84	;
	85	}
	86
	87	static void Fatal(void)
	88	{
28fdb04f	89	for(;;);
15c4dc5a	90	}
15c4dc5a	91
28fdb04f	92	void UsbPacketReceived(uint8_t *packet, int len) {
	93	int i, dont_ack=0;
	94	UsbCommand* c = (UsbCommand *)packet;
	95	volatile uint32_t *p;
	96
	97	if(len != sizeof(UsbCommand)) {
	98	Fatal();
	99	}
	100
	101	uint32_t arg0 = (uint32_t)c->arg[0];
	102
	103	switch(c->cmd) {
	104	case CMD_DEVICE_INFO: {
	105	dont_ack = 1;
28fdb04f	106	arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT \| DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM \|
	107	DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
	108	if(common_area.flags.osimage_present) {
	109	arg0 \|= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
	110	}
28fdb04f	111	cmd_send(CMD_DEVICE_INFO,arg0,1,2,0,0);
	112	} break;
	113
	114	case CMD_SETUP_WRITE: {
	115	/* The temporary write buffer of the embedded flash controller is mapped to the
	116	* whole memory region, only the last 8 bits are decoded.
	117	*/
	118	p = (volatile uint32_t *)&_flash_start;
	119	for(i = 0; i < 12; i++) {
	120	p[i+arg0] = c->d.asDwords[i];
	121	}
	122	} break;
	123
	124	case CMD_FINISH_WRITE: {
	125	uint32_t* flash_mem = (uint32_t*)(&_flash_start);
28fdb04f	126	for (size_t j=0; j<2; j++) {
28fdb04f	127	for(i = 0+(64j); i < 64+(64j); i++) {
28fdb04f	128	flash_mem[i] = c->d.asDwords[i];
	129	}
	130
	131	uint32_t flash_address = arg0 + (0x100*j);
	132
	133	/* Check that the address that we are supposed to write to is within our allowed region */
	134	if( ((flash_address+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) \|\| (flash_address < start_addr) ) {
	135	/* Disallow write */
	136	dont_ack = 1;
28fdb04f	137	cmd_send(CMD_NACK,0,0,0,0,0);
	138	} else {
	139	uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
	140	/* Translate address to flash page and do flash, update here for the 512k part */
	141	AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY \|
	142	MC_FLASH_COMMAND_PAGEN(page_n) \|
	143	AT91C_MC_FCMD_START_PROG;
28fdb04f	144	}
	145
	146	// Wait until flashing of page finishes
	147	uint32_t sr;
	148	while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
	149	if(sr & (AT91C_MC_LOCKE \| AT91C_MC_PROGE)) {
	150	dont_ack = 1;
28fdb04f	151	cmd_send(CMD_NACK,0,0,0,0,0);
28fdb04f	152	}
	153	}
	154	} break;
	155
	156	case CMD_HARDWARE_RESET: {
28fdb04f	157	usb_disable();
	158	AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY \| AT91C_RSTC_PROCRST;
	159	} break;
	160
	161	case CMD_START_FLASH: {
	162	if(c->arg[2] == START_FLASH_MAGIC) bootrom_unlocked = 1;
	163	else bootrom_unlocked = 0;
	164	{
	165	int prot_start = (int)&_bootrom_start;
	166	int prot_end = (int)&_bootrom_end;
	167	int allow_start = (int)&_flash_start;
	168	int allow_end = (int)&_flash_end;
	169	int cmd_start = c->arg[0];
	170	int cmd_end = c->arg[1];
	171
	172	/* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
	173	* bootrom area. In any case they must be within the flash area.
	174	*/
	175	if( (bootrom_unlocked \|\| ((cmd_start >= prot_end) \|\| (cmd_end < prot_start)))
	176	&& (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
	177	start_addr = cmd_start;
	178	end_addr = cmd_end;
	179	} else {
	180	start_addr = end_addr = 0;
	181	dont_ack = 1;
28fdb04f	182	cmd_send(CMD_NACK,0,0,0,0,0);
	183	}
	184	}
	185	} break;
	186
	187	default: {
	188	Fatal();
	189	} break;
	190	}
	191
	192	if(!dont_ack) {
28fdb04f	193	cmd_send(CMD_ACK,arg0,0,0,0,0);
28fdb04f	194	}
15c4dc5a	195	}
	196
	197	static void flash_mode(int externally_entered)
	198	{
	199	start_addr = 0;
	200	end_addr = 0;
	201	bootrom_unlocked = 0;
28fdb04f	202	byte_t rx[sizeof(UsbCommand)];
	203	size_t rx_len;
	204
	205	usb_enable();
	206	for (volatile size_t i=0; i<0x100000; i++);
15c4dc5a	207
15c4dc5a	208	for(;;) {
	209	WDT_HIT();
	210
28fdb04f	211	if (usb_poll()) {
	212	rx_len = usb_read(rx,sizeof(UsbCommand));
	213	if (rx_len) {
28fdb04f	214	UsbPacketReceived(rx,rx_len);
	215	}
	216	}
	217
15c4dc5a	218	if(!externally_entered && !BUTTON_PRESS()) {
15c4dc5a	219	/* Perform a reset to leave flash mode */
28fdb04f	220	usb_disable();
15c4dc5a	221	LED_B_ON();
	222	AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY \| AT91C_RSTC_PROCRST;
	223	for(;;);
	224	}
	225	if(externally_entered && BUTTON_PRESS()) {
	226	/* Let the user's button press override the automatic leave */
	227	externally_entered = 0;
	228	}
	229	}
	230	}
	231
28fdb04f	232	extern uint32_t _osimage_entry;
15c4dc5a	233	void BootROM(void)
	234	{
	235	//------------
	236	// First set up all the I/O pins; GPIOs configured directly, other ones
	237	// just need to be assigned to the appropriate peripheral.
	238
	239	// Kill all the pullups, especially the one on USB D+; leave them for
	240	// the unused pins, though.
	241	AT91C_BASE_PIOA->PIO_PPUDR =
	242	GPIO_USB_PU \|
	243	GPIO_LED_A \|
	244	GPIO_LED_B \|
	245	GPIO_LED_C \|
	246	GPIO_LED_D \|
	247	GPIO_FPGA_DIN \|
	248	GPIO_FPGA_DOUT \|
	249	GPIO_FPGA_CCLK \|
	250	GPIO_FPGA_NINIT \|
	251	GPIO_FPGA_NPROGRAM \|
	252	GPIO_FPGA_DONE \|
	253	GPIO_MUXSEL_HIPKD \|
	254	GPIO_MUXSEL_HIRAW \|
	255	GPIO_MUXSEL_LOPKD \|
	256	GPIO_MUXSEL_LORAW \|
	257	GPIO_RELAY \|
	258	GPIO_NVDD_ON;
	259	// (and add GPIO_FPGA_ON)
	260	// These pins are outputs
	261	AT91C_BASE_PIOA->PIO_OER =
	262	GPIO_LED_A \|
	263	GPIO_LED_B \|
	264	GPIO_LED_C \|
	265	GPIO_LED_D \|
	266	GPIO_RELAY \|
	267	GPIO_NVDD_ON;
	268	// PIO controls the following pins
	269	AT91C_BASE_PIOA->PIO_PER =
	270	GPIO_USB_PU \|
	271	GPIO_LED_A \|
	272	GPIO_LED_B \|
	273	GPIO_LED_C \|
	274	GPIO_LED_D;
	275
28fdb04f	276	// USB_D_PLUS_PULLUP_OFF();
28fdb04f	277	usb_disable();
15c4dc5a	278	LED_D_OFF();
	279	LED_C_ON();
	280	LED_B_OFF();
	281	LED_A_OFF();
	282
24b182d0	283	AT91C_BASE_EFC0->EFC_FMR =
0aa4cfc2	284	AT91C_MC_FWS_1FWS \|
24b182d0	285	MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
15c4dc5a	286
	287	// Initialize all system clocks
	288	ConfigClocks();
	289
	290	LED_A_ON();
	291
	292	int common_area_present = 0;
	293	switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
	294	case AT91C_RSTC_RSTTYP_WATCHDOG:
	295	case AT91C_RSTC_RSTTYP_SOFTWARE:
	296	case AT91C_RSTC_RSTTYP_USER:
	297	/* In these cases the common_area in RAM should be ok, retain it if it's there */
	298	if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
	299	common_area_present = 1;
	300	}
	301	break;
	302	default: /* Otherwise, initialize it from scratch */
	303	break;
	304	}
	305
	306	if(!common_area_present){
	307	/* Common area not ok, initialize it */
	308	int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
	309	((char*)&common_area)[i] = 0;
	310	}
	311	common_area.magic = COMMON_AREA_MAGIC;
	312	common_area.version = 1;
	313	common_area.flags.bootrom_present = 1;
	314	}
	315
	316	common_area.flags.bootrom_present = 1;
	317	if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
	318	common_area.command = COMMON_AREA_COMMAND_NONE;
	319	flash_mode(1);
	320	} else if(BUTTON_PRESS()) {
	321	flash_mode(0);
28fdb04f	322	} else if(_osimage_entry == 0xffffffffU) {
15c4dc5a	323	flash_mode(1);
	324	} else {
	325	// jump to Flash address of the osimage entry point (LSBit set for thumb mode)
902cb3c0	326	__asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) \| 0x1 ) );
15c4dc5a	327	}
15c4dc5a	328	}