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e30c654b | 1 | //----------------------------------------------------------------------------- |
e30c654b | 2 | // Jonathan Westhues, Sept 2005 |
bd20f8f4 | 3 | // |
4 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, | |
5 | // at your option, any later version. See the LICENSE.txt file for the text of | |
6 | // the license. | |
7 | //----------------------------------------------------------------------------- | |
8 | // Utility functions used in many places, not specific to any piece of code. | |
e30c654b | 9 | //----------------------------------------------------------------------------- |
bd20f8f4 | 10 | |
e30c654b | 11 | #include "proxmark3.h" |
f7e3ed82 | 12 | #include "util.h" |
9ab7a6c7 | 13 | #include "string.h" |
9492e0b0 | 14 | #include "apps.h" |
7d5ebac9 | 15 | #include "BigBuf.h" |
e30c654b | 16 | |
787b5bd8 | 17 | |
18 | ||
19 | void print_result(char *name, uint8_t *buf, size_t len) { | |
20 | uint8_t *p = buf; | |
21 | ||
22 | if ( len % 16 == 0 ) { | |
23 | for(; p-buf < len; p += 16) | |
24 | Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", | |
25 | name, | |
26 | p-buf, | |
27 | len, | |
28 | p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15] | |
29 | ); | |
30 | } | |
31 | else { | |
32 | for(; p-buf < len; p += 8) | |
33 | Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); | |
34 | } | |
35 | } | |
36 | ||
195af472 | 37 | size_t nbytes(size_t nbits) { |
665775c8 | 38 | return (nbits >> 3)+((nbits % 8) > 0); |
195af472 | 39 | } |
40 | ||
81cd0474 | 41 | uint32_t SwapBits(uint32_t value, int nrbits) { |
42 | int i; | |
43 | uint32_t newvalue = 0; | |
44 | for(i = 0; i < nrbits; i++) { | |
45 | newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i); | |
46 | } | |
47 | return newvalue; | |
48 | } | |
49 | ||
f7e3ed82 | 50 | void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) |
e30c654b | 51 | { |
52 | while (len--) { | |
f7e3ed82 | 53 | dest[len] = (uint8_t) n; |
e30c654b | 54 | n >>= 8; |
55 | } | |
56 | } | |
57 | ||
f7e3ed82 | 58 | uint64_t bytes_to_num(uint8_t* src, size_t len) |
e30c654b | 59 | { |
60 | uint64_t num = 0; | |
61 | while (len--) | |
62 | { | |
63 | num = (num << 8) | (*src); | |
64 | src++; | |
65 | } | |
66 | return num; | |
67 | } | |
68 | ||
787b5bd8 | 69 | // RotateLeft - Ultralight, Desfire |
70 | void rol(uint8_t *data, const size_t len){ | |
71 | uint8_t first = data[0]; | |
72 | for (size_t i = 0; i < len-1; i++) { | |
73 | data[i] = data[i+1]; | |
74 | } | |
75 | data[len-1] = first; | |
76 | } | |
77 | void lsl (uint8_t *data, size_t len) { | |
78 | for (size_t n = 0; n < len - 1; n++) { | |
79 | data[n] = (data[n] << 1) | (data[n+1] >> 7); | |
80 | } | |
81 | data[len - 1] <<= 1; | |
82 | } | |
83 | ||
84 | int32_t le24toh (uint8_t data[3]) | |
85 | { | |
86 | return (data[2] << 16) | (data[1] << 8) | data[0]; | |
87 | } | |
88 | ||
e30c654b | 89 | void LEDsoff() |
90 | { | |
91 | LED_A_OFF(); | |
92 | LED_B_OFF(); | |
93 | LED_C_OFF(); | |
94 | LED_D_OFF(); | |
95 | } | |
96 | ||
97 | // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8] | |
98 | void LED(int led, int ms) | |
99 | { | |
100 | if (led & LED_RED) | |
101 | LED_C_ON(); | |
102 | if (led & LED_ORANGE) | |
103 | LED_A_ON(); | |
104 | if (led & LED_GREEN) | |
105 | LED_B_ON(); | |
106 | if (led & LED_RED2) | |
107 | LED_D_ON(); | |
108 | ||
109 | if (!ms) | |
110 | return; | |
111 | ||
112 | SpinDelay(ms); | |
113 | ||
114 | if (led & LED_RED) | |
115 | LED_C_OFF(); | |
116 | if (led & LED_ORANGE) | |
117 | LED_A_OFF(); | |
118 | if (led & LED_GREEN) | |
119 | LED_B_OFF(); | |
120 | if (led & LED_RED2) | |
121 | LED_D_OFF(); | |
122 | } | |
123 | ||
124 | ||
125 | // Determine if a button is double clicked, single clicked, | |
126 | // not clicked, or held down (for ms || 1sec) | |
127 | // In general, don't use this function unless you expect a | |
128 | // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead | |
129 | int BUTTON_CLICKED(int ms) | |
130 | { | |
131 | // Up to 500ms in between clicks to mean a double click | |
132 | int ticks = (48000 * (ms ? ms : 1000)) >> 10; | |
133 | ||
134 | // If we're not even pressed, forget about it! | |
135 | if (!BUTTON_PRESS()) | |
136 | return BUTTON_NO_CLICK; | |
137 | ||
138 | // Borrow a PWM unit for my real-time clock | |
139 | AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0); | |
140 | // 48 MHz / 1024 gives 46.875 kHz | |
141 | AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10); | |
142 | AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; | |
143 | AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; | |
144 | ||
f7e3ed82 | 145 | uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; |
e30c654b | 146 | |
147 | int letoff = 0; | |
148 | for(;;) | |
149 | { | |
f7e3ed82 | 150 | uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; |
e30c654b | 151 | |
152 | // We haven't let off the button yet | |
153 | if (!letoff) | |
154 | { | |
155 | // We just let it off! | |
156 | if (!BUTTON_PRESS()) | |
157 | { | |
158 | letoff = 1; | |
159 | ||
160 | // reset our timer for 500ms | |
161 | start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; | |
162 | ticks = (48000 * (500)) >> 10; | |
163 | } | |
164 | ||
165 | // Still haven't let it off | |
166 | else | |
167 | // Have we held down a full second? | |
f7e3ed82 | 168 | if (now == (uint16_t)(start + ticks)) |
e30c654b | 169 | return BUTTON_HOLD; |
170 | } | |
171 | ||
172 | // We already let off, did we click again? | |
173 | else | |
174 | // Sweet, double click! | |
175 | if (BUTTON_PRESS()) | |
176 | return BUTTON_DOUBLE_CLICK; | |
177 | ||
178 | // Have we ran out of time to double click? | |
179 | else | |
f7e3ed82 | 180 | if (now == (uint16_t)(start + ticks)) |
e30c654b | 181 | // At least we did a single click |
182 | return BUTTON_SINGLE_CLICK; | |
183 | ||
184 | WDT_HIT(); | |
185 | } | |
186 | ||
187 | // We should never get here | |
188 | return BUTTON_ERROR; | |
189 | } | |
190 | ||
191 | // Determine if a button is held down | |
192 | int BUTTON_HELD(int ms) | |
193 | { | |
194 | // If button is held for one second | |
195 | int ticks = (48000 * (ms ? ms : 1000)) >> 10; | |
196 | ||
197 | // If we're not even pressed, forget about it! | |
198 | if (!BUTTON_PRESS()) | |
199 | return BUTTON_NO_CLICK; | |
200 | ||
201 | // Borrow a PWM unit for my real-time clock | |
202 | AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0); | |
203 | // 48 MHz / 1024 gives 46.875 kHz | |
204 | AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10); | |
205 | AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; | |
206 | AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; | |
207 | ||
f7e3ed82 | 208 | uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; |
e30c654b | 209 | |
210 | for(;;) | |
211 | { | |
f7e3ed82 | 212 | uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; |
e30c654b | 213 | |
214 | // As soon as our button let go, we didn't hold long enough | |
215 | if (!BUTTON_PRESS()) | |
216 | return BUTTON_SINGLE_CLICK; | |
217 | ||
218 | // Have we waited the full second? | |
219 | else | |
f7e3ed82 | 220 | if (now == (uint16_t)(start + ticks)) |
e30c654b | 221 | return BUTTON_HOLD; |
222 | ||
223 | WDT_HIT(); | |
224 | } | |
225 | ||
226 | // We should never get here | |
227 | return BUTTON_ERROR; | |
228 | } | |
229 | ||
230 | // attempt at high resolution microsecond timer | |
231 | // beware: timer counts in 21.3uS increments (1024/48Mhz) | |
232 | void SpinDelayUs(int us) | |
233 | { | |
234 | int ticks = (48*us) >> 10; | |
235 | ||
236 | // Borrow a PWM unit for my real-time clock | |
237 | AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0); | |
238 | // 48 MHz / 1024 gives 46.875 kHz | |
239 | AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10); | |
240 | AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0; | |
241 | AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff; | |
242 | ||
f7e3ed82 | 243 | uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; |
e30c654b | 244 | |
245 | for(;;) { | |
f7e3ed82 | 246 | uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR; |
247 | if (now == (uint16_t)(start + ticks)) | |
e30c654b | 248 | return; |
249 | ||
250 | WDT_HIT(); | |
251 | } | |
252 | } | |
253 | ||
254 | void SpinDelay(int ms) | |
255 | { | |
256 | // convert to uS and call microsecond delay function | |
257 | SpinDelayUs(ms*1000); | |
258 | } | |
259 | ||
260 | /* Similar to FpgaGatherVersion this formats stored version information | |
261 | * into a string representation. It takes a pointer to the struct version_information, | |
262 | * verifies the magic properties, then stores a formatted string, prefixed by | |
263 | * prefix in dst. | |
264 | */ | |
265 | void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information) | |
266 | { | |
267 | struct version_information *v = (struct version_information*)version_information; | |
268 | dst[0] = 0; | |
2ed270a8 | 269 | strncat(dst, prefix, len-1); |
e30c654b | 270 | if(v->magic != VERSION_INFORMATION_MAGIC) { |
8e074056 | 271 | strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1); |
e30c654b | 272 | return; |
273 | } | |
274 | if(v->versionversion != 1) { | |
8e074056 | 275 | strncat(dst, "Version information not understood\n", len - strlen(dst) - 1); |
e30c654b | 276 | return; |
277 | } | |
278 | if(!v->present) { | |
8e074056 | 279 | strncat(dst, "Version information not available\n", len - strlen(dst) - 1); |
e30c654b | 280 | return; |
281 | } | |
282 | ||
cba867f2 | 283 | strncat(dst, v->gitversion, len - strlen(dst) - 1); |
e30c654b | 284 | if(v->clean == 0) { |
cba867f2 | 285 | strncat(dst, "-unclean", len - strlen(dst) - 1); |
e30c654b | 286 | } else if(v->clean == 2) { |
cba867f2 | 287 | strncat(dst, "-suspect", len - strlen(dst) - 1); |
e30c654b | 288 | } |
289 | ||
cba867f2 MHS |
290 | strncat(dst, " ", len - strlen(dst) - 1); |
291 | strncat(dst, v->buildtime, len - strlen(dst) - 1); | |
8e074056 | 292 | strncat(dst, "\n", len - strlen(dst) - 1); |
e30c654b | 293 | } |
9ca155ba M |
294 | |
295 | // ------------------------------------------------------------------------- | |
296 | // timer lib | |
297 | // ------------------------------------------------------------------------- | |
298 | // test procedure: | |
299 | // | |
300 | // ti = GetTickCount(); | |
301 | // SpinDelay(1000); | |
302 | // ti = GetTickCount() - ti; | |
303 | // Dbprintf("timer(1s): %d t=%d", ti, GetTickCount()); | |
304 | ||
305 | void StartTickCount() | |
306 | { | |
bfb01844 | 307 | // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz. |
308 | // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register. | |
309 | uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff; // = 16 * main clock frequency (16MHz) / slow clock frequency | |
310 | // set RealTimeCounter divider to count at 1kHz: | |
311 | AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf); | |
312 | // note: worst case precision is approx 2.5% | |
9ca155ba M |
313 | } |
314 | ||
315 | /* | |
316 | * Get the current count. | |
317 | */ | |
318 | uint32_t RAMFUNC GetTickCount(){ | |
8f51ddb0 | 319 | return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2; |
9ca155ba M |
320 | } |
321 | ||
8f51ddb0 M |
322 | // ------------------------------------------------------------------------- |
323 | // microseconds timer | |
324 | // ------------------------------------------------------------------------- | |
325 | void StartCountUS() | |
326 | { | |
327 | AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14); | |
328 | // AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0; | |
329 | AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE; | |
330 | ||
331 | // fast clock | |
332 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable | |
333 | AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks | |
334 | AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR | | |
335 | AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET; | |
336 | AT91C_BASE_TC0->TC_RA = 1; | |
337 | AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000 | |
338 | ||
339 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable | |
340 | AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0 | |
1c611bbd | 341 | |
8f51ddb0 M |
342 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; |
343 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; | |
344 | AT91C_BASE_TCB->TCB_BCR = 1; | |
1c611bbd | 345 | } |
8f51ddb0 M |
346 | |
347 | uint32_t RAMFUNC GetCountUS(){ | |
348 | return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10); | |
349 | } | |
350 | ||
351 | static uint32_t GlobalUsCounter = 0; | |
352 | ||
353 | uint32_t RAMFUNC GetDeltaCountUS(){ | |
354 | uint32_t g_cnt = GetCountUS(); | |
355 | uint32_t g_res = g_cnt - GlobalUsCounter; | |
356 | GlobalUsCounter = g_cnt; | |
357 | return g_res; | |
358 | } | |
359 | ||
360 | ||
1c611bbd | 361 | // ------------------------------------------------------------------------- |
7bc95e2e | 362 | // Timer for iso14443 commands. Uses ssp_clk from FPGA |
1c611bbd | 363 | // ------------------------------------------------------------------------- |
7bc95e2e | 364 | void StartCountSspClk() |
1c611bbd | 365 | { |
366 | AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers | |
367 | AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1 | |
368 | | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none | |
369 | | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0 | |
370 | ||
371 | // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs: | |
372 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1 | |
373 | AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz | |
374 | | AT91C_TC_CPCSTOP // Stop clock on RC compare | |
375 | | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event | |
7bc95e2e | 376 | | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16) |
1c611bbd | 377 | | AT91C_TC_ENETRG // Enable external trigger event |
378 | | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare | |
379 | | AT91C_TC_WAVE // Waveform Mode | |
380 | | AT91C_TC_AEEVT_SET // Set TIOA1 on external event | |
381 | | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare | |
382 | AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04 | |
383 | ||
384 | // use TC0 to count TIOA1 pulses | |
7bc95e2e | 385 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0 |
1c611bbd | 386 | AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1 |
387 | | AT91C_TC_WAVE // Waveform Mode | |
388 | | AT91C_TC_WAVESEL_UP // just count | |
389 | | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare | |
390 | | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare | |
391 | AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2 | |
392 | AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow | |
393 | ||
394 | // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk) | |
395 | AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2 | |
396 | AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0 | |
397 | | AT91C_TC_WAVE // Waveform Mode | |
398 | | AT91C_TC_WAVESEL_UP; // just count | |
399 | ||
1c611bbd | 400 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0 |
401 | AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1 | |
402 | AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2 | |
9492e0b0 | 403 | |
7bc95e2e | 404 | // |
405 | // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present | |
406 | // | |
407 | while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame) | |
9492e0b0 | 408 | while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low |
7bc95e2e | 409 | while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high |
410 | // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame | |
411 | // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge | |
1c611bbd | 412 | AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge) |
7bc95e2e | 413 | // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0) |
414 | // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on, | |
415 | // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer. | |
416 | // (just started with the transfer of the 4th Bit). | |
417 | // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before | |
418 | // we can use the counter. | |
419 | while (AT91C_BASE_TC0->TC_CV < 0xFFF0); | |
1c611bbd | 420 | } |
421 | ||
422 | ||
7bc95e2e | 423 | uint32_t RAMFUNC GetCountSspClk(){ |
1c611bbd | 424 | uint32_t tmp_count; |
425 | tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV; | |
7bc95e2e | 426 | if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2 |
1c611bbd | 427 | return (AT91C_BASE_TC2->TC_CV << 16); |
428 | } | |
429 | else { | |
430 | return tmp_count; | |
431 | } | |
432 | } | |
7bc95e2e | 433 |