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1 | //----------------------------------------------------------------------------- |
2 | // The way that we connect things in low-frequency simulation mode. In this |
3 | // case just pass everything through to the ARM, which can bit-bang this |
4 | // (because it is so slow). |
5 | // |
6 | // Jonathan Westhues, April 2006 |
7 | //----------------------------------------------------------------------------- |
8 | |
9 | module lo_simulate( |
10 | pck0, ck_1356meg, ck_1356megb, |
11 | pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4, |
12 | adc_d, adc_clk, |
13 | ssp_frame, ssp_din, ssp_dout, ssp_clk, |
14 | cross_hi, cross_lo, |
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15 | dbg, |
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16 | divisor |
17 | ); |
18 | input pck0, ck_1356meg, ck_1356megb; |
19 | output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4; |
20 | input [7:0] adc_d; |
21 | output adc_clk; |
22 | input ssp_dout; |
23 | output ssp_frame, ssp_din, ssp_clk; |
24 | input cross_hi, cross_lo; |
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25 | output dbg; |
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26 | input [7:0] divisor; |
27 | |
28 | // No logic, straight through. |
29 | assign pwr_oe3 = 1'b0; |
30 | assign pwr_oe1 = ssp_dout; |
31 | assign pwr_oe2 = ssp_dout; |
32 | assign pwr_oe4 = ssp_dout; |
33 | assign ssp_clk = cross_lo; |
34 | assign pwr_lo = 1'b0; |
35 | assign pwr_hi = 1'b0; |
36 | assign dbg = ssp_frame; |
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37 | |
38 | // Divide the clock to be used for the ADC |
39 | reg [7:0] pck_divider; |
40 | reg clk_state; |
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41 | |
42 | always @(posedge pck0) |
43 | begin |
44 | if(pck_divider == divisor[7:0]) |
45 | begin |
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46 | pck_divider <= 8'd0; |
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47 | clk_state = !clk_state; |
48 | end |
49 | else |
50 | begin |
51 | pck_divider <= pck_divider + 1; |
52 | end |
53 | end |
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54 | |
55 | assign adc_clk = ~clk_state; |
56 | |
57 | // Toggle the output with hysteresis |
58 | // Set to high if the ADC value is above 200 |
59 | // Set to low if the ADC value is below 64 |
60 | reg is_high; |
61 | reg is_low; |
62 | reg output_state; |
63 | |
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64 | always @(posedge pck0) |
65 | begin |
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66 | if((pck_divider == 8'd7) && !clk_state) begin |
67 | is_high = (adc_d >= 8'd200); |
68 | is_low = (adc_d <= 8'd64); |
69 | end |
70 | end |
71 | |
72 | always @(posedge is_high or posedge is_low) |
73 | begin |
74 | if(is_high) |
75 | output_state <= 1'd1; |
76 | else if(is_low) |
77 | output_state <= 1'd0; |
78 | end |
79 | |
80 | assign ssp_frame = output_state; |
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81 | |
82 | endmodule |
83 | |