]> git.zerfleddert.de Git - proxmark3-svn/blame_incremental - tools/at91sam7s512-busblaster.cfg
fix: hf mf mifare - populate keylist (#568)
[proxmark3-svn] / tools / at91sam7s512-busblaster.cfg
... / ...
CommitLineData
1## General OpenOCD configuration
2# Ports
3telnet_port 4444
4gdb_port 3333
5
6## Interface configuration section
7# Interface
8
9# you can use
10#source [find interface/ftdi/dp_busblaster.cfg]
11# or
12
13interface ftdi
14ftdi_device_desc "Dual RS232-HS"
15ftdi_vid_pid 0x0403 0x6010
16
17ftdi_layout_init 0x0c08 0x0f1b
18ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
19ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
20
21adapter_khz 1000
22
23## Chipset configuration section
24# use combined on interfaces or targets that can't set TRST/SRST separately
25reset_config srst_only srst_pulls_trst
26
27jtag newtap sam7x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f
28
29target create sam7x.cpu arm7tdmi -endian little -chain-position sam7x.cpu
30
31sam7x.cpu configure -event reset-init {
32 soft_reset_halt
33 mww 0xfffffd00 0xa5000004 # RSTC_CR: Reset peripherals
34 mww 0xfffffd44 0x00008000 # WDT_MR: disable watchdog
35 mww 0xfffffd08 0xa5000001 # RSTC_MR enable user reset
36 mww 0xfffffc20 0x00005001 # CKGR_MOR : enable the main oscillator
37 sleep 10
38 mww 0xfffffc2c 0x000b1c02 # CKGR_PLLR: 16MHz * 12/2 = 96MHz
39 sleep 10
40 mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 = 48 MHz
41 sleep 10
42 mww 0xffffff60 0x00480100 # MC_FMR: flash mode (FWS=1,FMCN=72)
43 sleep 100
44
45}
46
47# GDB can also flash my flash!
48gdb_memory_map enable
49gdb_breakpoint_override hard
50#armv4_5 core_state arm
51
52sam7x.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0
53flash bank sam7x512.flash.0 at91sam7 0 0 0 0 sam7x.cpu 0 0 0 0 0 0 0 18432
54flash bank sam7x512.flash.1 at91sam7 0 0 0 0 sam7x.cpu 1 0 0 0 0 0 0 18432
Impressum, Datenschutz