]> git.zerfleddert.de Git - proxmark3-svn/blame_incremental - include/at91sam7s512.h
projects / proxmark3-svn / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
fix broken formatting in command table
[proxmark3-svn] / include / at91sam7s512.h
... / ...
CommitLineData
1// ----------------------------------------------------------------------------\r
2// ATMEL Microcontroller Software Support - ROUSSET -\r
3// ----------------------------------------------------------------------------\r
4// Copyright (c) 2006, Atmel Corporation\r
5//\r
6// All rights reserved.\r
7//\r
8// Redistribution and use in source and binary forms, with or without\r
9// modification, are permitted provided that the following conditions are met:\r
10//\r
11// - Redistributions of source code must retain the above copyright notice,\r
12// this list of conditions and the disclaimer below.\r
13//\r
14// Atmel's name may not be used to endorse or promote products derived from\r
15// this software without specific prior written permission.\r
16//\r
17// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR\r
18// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
19// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
20// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,\r
21// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
22// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\r
23// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
24// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
25// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
26// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
27// ----------------------------------------------------------------------------\r
28// File Name : AT91SAM7S512.h\r
29// Object : AT91SAM7S512 definitions\r
30// Generated : AT91 SW Application Group 07/07/2008 (16:13:20)\r
31//\r
32// CVS Reference : /AT91SAM7S512.pl/1.6/Wed Aug 30 14:08:44 2006//\r
33// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005//\r
34// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006//\r
35// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005//\r
36// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//\r
37// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006//\r
38// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//\r
39// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//\r
40// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//\r
41// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//\r
42// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//\r
43// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//\r
44// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//\r
45// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//\r
46// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//\r
47// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//\r
48// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//\r
49// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//\r
50// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//\r
51// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//\r
52// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//\r
53// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005//\r
54// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005//\r
55// CVS Reference : /SDRC_SAM7SE512.pl/1.7/Fri Jul 8 07:50:18 2005//\r
56// CVS Reference : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005//\r
57// ----------------------------------------------------------------------------\r
58\r
59#ifndef AT91SAM7S512_H\r
60#define AT91SAM7S512_H\r
61\r
62#ifndef __ASSEMBLY__\r
63typedef volatile unsigned int AT91_REG;// Hardware register definition\r
64#define AT91_CAST(a) (a)\r
65#else\r
66#define AT91_CAST(a)\r
67#endif\r
68\r
69// *****************************************************************************\r
70// SOFTWARE API DEFINITION FOR System Peripherals\r
71// *****************************************************************************\r
72#ifndef __ASSEMBLY__\r
73typedef struct _AT91S_SYS {\r
74 AT91_REG AIC_SMR[32]; // Source Mode Register\r
75 AT91_REG AIC_SVR[32]; // Source Vector Register\r
76 AT91_REG AIC_IVR; // IRQ Vector Register\r
77 AT91_REG AIC_FVR; // FIQ Vector Register\r
78 AT91_REG AIC_ISR; // Interrupt Status Register\r
79 AT91_REG AIC_IPR; // Interrupt Pending Register\r
80 AT91_REG AIC_IMR; // Interrupt Mask Register\r
81 AT91_REG AIC_CISR; // Core Interrupt Status Register\r
82 AT91_REG Reserved0[2]; //\r
83 AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
84 AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
85 AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
86 AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
87 AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
88 AT91_REG AIC_SPU; // Spurious Vector Register\r
89 AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
90 AT91_REG Reserved1[1]; //\r
91 AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
92 AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
93 AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
94 AT91_REG Reserved2[45]; //\r
95 AT91_REG DBGU_CR; // Control Register\r
96 AT91_REG DBGU_MR; // Mode Register\r
97 AT91_REG DBGU_IER; // Interrupt Enable Register\r
98 AT91_REG DBGU_IDR; // Interrupt Disable Register\r
99 AT91_REG DBGU_IMR; // Interrupt Mask Register\r
100 AT91_REG DBGU_CSR; // Channel Status Register\r
101 AT91_REG DBGU_RHR; // Receiver Holding Register\r
102 AT91_REG DBGU_THR; // Transmitter Holding Register\r
103 AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
104 AT91_REG Reserved3[7]; //\r
105 AT91_REG DBGU_CIDR; // Chip ID Register\r
106 AT91_REG DBGU_EXID; // Chip ID Extension Register\r
107 AT91_REG DBGU_FNTR; // Force NTRST Register\r
108 AT91_REG Reserved4[45]; //\r
109 AT91_REG DBGU_RPR; // Receive Pointer Register\r
110 AT91_REG DBGU_RCR; // Receive Counter Register\r
111 AT91_REG DBGU_TPR; // Transmit Pointer Register\r
112 AT91_REG DBGU_TCR; // Transmit Counter Register\r
113 AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
114 AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
115 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
116 AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
117 AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
118 AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
119 AT91_REG Reserved5[54]; //\r
120 AT91_REG PIOA_PER; // PIO Enable Register\r
121 AT91_REG PIOA_PDR; // PIO Disable Register\r
122 AT91_REG PIOA_PSR; // PIO Status Register\r
123 AT91_REG Reserved6[1]; //\r
124 AT91_REG PIOA_OER; // Output Enable Register\r
125 AT91_REG PIOA_ODR; // Output Disable Registerr\r
126 AT91_REG PIOA_OSR; // Output Status Register\r
127 AT91_REG Reserved7[1]; //\r
128 AT91_REG PIOA_IFER; // Input Filter Enable Register\r
129 AT91_REG PIOA_IFDR; // Input Filter Disable Register\r
130 AT91_REG PIOA_IFSR; // Input Filter Status Register\r
131 AT91_REG Reserved8[1]; //\r
132 AT91_REG PIOA_SODR; // Set Output Data Register\r
133 AT91_REG PIOA_CODR; // Clear Output Data Register\r
134 AT91_REG PIOA_ODSR; // Output Data Status Register\r
135 AT91_REG PIOA_PDSR; // Pin Data Status Register\r
136 AT91_REG PIOA_IER; // Interrupt Enable Register\r
137 AT91_REG PIOA_IDR; // Interrupt Disable Register\r
138 AT91_REG PIOA_IMR; // Interrupt Mask Register\r
139 AT91_REG PIOA_ISR; // Interrupt Status Register\r
140 AT91_REG PIOA_MDER; // Multi-driver Enable Register\r
141 AT91_REG PIOA_MDDR; // Multi-driver Disable Register\r
142 AT91_REG PIOA_MDSR; // Multi-driver Status Register\r
143 AT91_REG Reserved9[1]; //\r
144 AT91_REG PIOA_PPUDR; // Pull-up Disable Register\r
145 AT91_REG PIOA_PPUER; // Pull-up Enable Register\r
146 AT91_REG PIOA_PPUSR; // Pull-up Status Register\r
147 AT91_REG Reserved10[1]; //\r
148 AT91_REG PIOA_ASR; // Select A Register\r
149 AT91_REG PIOA_BSR; // Select B Register\r
150 AT91_REG PIOA_ABSR; // AB Select Status Register\r
151 AT91_REG Reserved11[9]; //\r
152 AT91_REG PIOA_OWER; // Output Write Enable Register\r
153 AT91_REG PIOA_OWDR; // Output Write Disable Register\r
154 AT91_REG PIOA_OWSR; // Output Write Status Register\r
155 AT91_REG Reserved12[469]; //\r
156 AT91_REG PMC_SCER; // System Clock Enable Register\r
157 AT91_REG PMC_SCDR; // System Clock Disable Register\r
158 AT91_REG PMC_SCSR; // System Clock Status Register\r
159 AT91_REG Reserved13[1]; //\r
160 AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
161 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
162 AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
163 AT91_REG Reserved14[1]; //\r
164 AT91_REG PMC_MOR; // Main Oscillator Register\r
165 AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
166 AT91_REG Reserved15[1]; //\r
167 AT91_REG PMC_PLLR; // PLL Register\r
168 AT91_REG PMC_MCKR; // Master Clock Register\r
169 AT91_REG Reserved16[3]; //\r
170 AT91_REG PMC_PCKR[3]; // Programmable Clock Register\r
171 AT91_REG Reserved17[5]; //\r
172 AT91_REG PMC_IER; // Interrupt Enable Register\r
173 AT91_REG PMC_IDR; // Interrupt Disable Register\r
174 AT91_REG PMC_SR; // Status Register\r
175 AT91_REG PMC_IMR; // Interrupt Mask Register\r
176 AT91_REG Reserved18[36]; //\r
177 AT91_REG RSTC_RCR; // Reset Control Register\r
178 AT91_REG RSTC_RSR; // Reset Status Register\r
179 AT91_REG RSTC_RMR; // Reset Mode Register\r
180 AT91_REG Reserved19[5]; //\r
181 AT91_REG RTTC_RTMR; // Real-time Mode Register\r
182 AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
183 AT91_REG RTTC_RTVR; // Real-time Value Register\r
184 AT91_REG RTTC_RTSR; // Real-time Status Register\r
185 AT91_REG PITC_PIMR; // Period Interval Mode Register\r
186 AT91_REG PITC_PISR; // Period Interval Status Register\r
187 AT91_REG PITC_PIVR; // Period Interval Value Register\r
188 AT91_REG PITC_PIIR; // Period Interval Image Register\r
189 AT91_REG WDTC_WDCR; // Watchdog Control Register\r
190 AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
191 AT91_REG WDTC_WDSR; // Watchdog Status Register\r
192 AT91_REG Reserved20[5]; //\r
193 AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
194} AT91S_SYS, *AT91PS_SYS;\r
195#else\r
196\r
197#endif\r
198\r
199// *****************************************************************************\r
200// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
201// *****************************************************************************\r
202#ifndef __ASSEMBLY__\r
203typedef struct _AT91S_AIC {\r
204 AT91_REG AIC_SMR[32]; // Source Mode Register\r
205 AT91_REG AIC_SVR[32]; // Source Vector Register\r
206 AT91_REG AIC_IVR; // IRQ Vector Register\r
207 AT91_REG AIC_FVR; // FIQ Vector Register\r
208 AT91_REG AIC_ISR; // Interrupt Status Register\r
209 AT91_REG AIC_IPR; // Interrupt Pending Register\r
210 AT91_REG AIC_IMR; // Interrupt Mask Register\r
211 AT91_REG AIC_CISR; // Core Interrupt Status Register\r
212 AT91_REG Reserved0[2]; //\r
213 AT91_REG AIC_IECR; // Interrupt Enable Command Register\r
214 AT91_REG AIC_IDCR; // Interrupt Disable Command Register\r
215 AT91_REG AIC_ICCR; // Interrupt Clear Command Register\r
216 AT91_REG AIC_ISCR; // Interrupt Set Command Register\r
217 AT91_REG AIC_EOICR; // End of Interrupt Command Register\r
218 AT91_REG AIC_SPU; // Spurious Vector Register\r
219 AT91_REG AIC_DCR; // Debug Control Register (Protect)\r
220 AT91_REG Reserved1[1]; //\r
221 AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
222 AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
223 AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
224} AT91S_AIC, *AT91PS_AIC;\r
225#else\r
226#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register\r
227#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register\r
228#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register\r
229#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register\r
230#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register\r
231#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register\r
232#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register\r
233#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register\r
234#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register\r
235#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register\r
236#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register\r
237#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register\r
238#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register\r
239#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register\r
240#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)\r
241#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register\r
242#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register\r
243#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register\r
244\r
245#endif\r
246// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------\r
247#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level\r
248#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level\r
249#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level\r
250#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type\r
251#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive\r
252#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive\r
253#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered\r
254#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered\r
255#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive\r
256#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered\r
257// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------\r
258#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status\r
259#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status\r
260// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------\r
261#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode\r
262#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask\r
263\r
264// *****************************************************************************\r
265// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
266// *****************************************************************************\r
267#ifndef __ASSEMBLY__\r
268typedef struct _AT91S_PDC {\r
269 AT91_REG PDC_RPR; // Receive Pointer Register\r
270 AT91_REG PDC_RCR; // Receive Counter Register\r
271 AT91_REG PDC_TPR; // Transmit Pointer Register\r
272 AT91_REG PDC_TCR; // Transmit Counter Register\r
273 AT91_REG PDC_RNPR; // Receive Next Pointer Register\r
274 AT91_REG PDC_RNCR; // Receive Next Counter Register\r
275 AT91_REG PDC_TNPR; // Transmit Next Pointer Register\r
276 AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
277 AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
278 AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
279} AT91S_PDC, *AT91PS_PDC;\r
280#else\r
281#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register\r
282#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register\r
283#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register\r
284#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register\r
285#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register\r
286#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register\r
287#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register\r
288#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register\r
289#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register\r
290#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register\r
291\r
292#endif\r
293// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------\r
294#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable\r
295#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable\r
296#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable\r
297#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable\r
298// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------\r
299\r
300// *****************************************************************************\r
301// SOFTWARE API DEFINITION FOR Debug Unit\r
302// *****************************************************************************\r
303#ifndef __ASSEMBLY__\r
304typedef struct _AT91S_DBGU {\r
305 AT91_REG DBGU_CR; // Control Register\r
306 AT91_REG DBGU_MR; // Mode Register\r
307 AT91_REG DBGU_IER; // Interrupt Enable Register\r
308 AT91_REG DBGU_IDR; // Interrupt Disable Register\r
309 AT91_REG DBGU_IMR; // Interrupt Mask Register\r
310 AT91_REG DBGU_CSR; // Channel Status Register\r
311 AT91_REG DBGU_RHR; // Receiver Holding Register\r
312 AT91_REG DBGU_THR; // Transmitter Holding Register\r
313 AT91_REG DBGU_BRGR; // Baud Rate Generator Register\r
314 AT91_REG Reserved0[7]; //\r
315 AT91_REG DBGU_CIDR; // Chip ID Register\r
316 AT91_REG DBGU_EXID; // Chip ID Extension Register\r
317 AT91_REG DBGU_FNTR; // Force NTRST Register\r
318 AT91_REG Reserved1[45]; //\r
319 AT91_REG DBGU_RPR; // Receive Pointer Register\r
320 AT91_REG DBGU_RCR; // Receive Counter Register\r
321 AT91_REG DBGU_TPR; // Transmit Pointer Register\r
322 AT91_REG DBGU_TCR; // Transmit Counter Register\r
323 AT91_REG DBGU_RNPR; // Receive Next Pointer Register\r
324 AT91_REG DBGU_RNCR; // Receive Next Counter Register\r
325 AT91_REG DBGU_TNPR; // Transmit Next Pointer Register\r
326 AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
327 AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
328 AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
329} AT91S_DBGU, *AT91PS_DBGU;\r
330#else\r
331#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register\r
332#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register\r
333#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register\r
334#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register\r
335#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register\r
336#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register\r
337#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register\r
338#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register\r
339#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register\r
340//#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register\r
341#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register\r
342#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register\r
343\r
344#endif\r
345// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------\r
346#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver\r
347#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter\r
348#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable\r
349#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable\r
350#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable\r
351#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable\r
352#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits\r
353// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------\r
354#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type\r
355#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity\r
356#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity\r
357#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)\r
358#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)\r
359#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity\r
360#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode\r
361#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode\r
362#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\r
363#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\r
364#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\r
365#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\r
366// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------\r
367#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt\r
368#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt\r
369#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt\r
370#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt\r
371#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt\r
372#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt\r
373#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt\r
374#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt\r
375#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt\r
376#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt\r
377#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt\r
378#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt\r
379// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------\r
380// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------\r
381// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------\r
382// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------\r
383#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG\r
384\r
385// *****************************************************************************\r
386// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
387// *****************************************************************************\r
388#ifndef __ASSEMBLY__\r
389typedef struct _AT91S_PIO {\r
390 AT91_REG PIO_PER; // PIO Enable Register\r
391 AT91_REG PIO_PDR; // PIO Disable Register\r
392 AT91_REG PIO_PSR; // PIO Status Register\r
393 AT91_REG Reserved0[1]; //\r
394 AT91_REG PIO_OER; // Output Enable Register\r
395 AT91_REG PIO_ODR; // Output Disable Registerr\r
396 AT91_REG PIO_OSR; // Output Status Register\r
397 AT91_REG Reserved1[1]; //\r
398 AT91_REG PIO_IFER; // Input Filter Enable Register\r
399 AT91_REG PIO_IFDR; // Input Filter Disable Register\r
400 AT91_REG PIO_IFSR; // Input Filter Status Register\r
401 AT91_REG Reserved2[1]; //\r
402 AT91_REG PIO_SODR; // Set Output Data Register\r
403 AT91_REG PIO_CODR; // Clear Output Data Register\r
404 AT91_REG PIO_ODSR; // Output Data Status Register\r
405 AT91_REG PIO_PDSR; // Pin Data Status Register\r
406 AT91_REG PIO_IER; // Interrupt Enable Register\r
407 AT91_REG PIO_IDR; // Interrupt Disable Register\r
408 AT91_REG PIO_IMR; // Interrupt Mask Register\r
409 AT91_REG PIO_ISR; // Interrupt Status Register\r
410 AT91_REG PIO_MDER; // Multi-driver Enable Register\r
411 AT91_REG PIO_MDDR; // Multi-driver Disable Register\r
412 AT91_REG PIO_MDSR; // Multi-driver Status Register\r
413 AT91_REG Reserved3[1]; //\r
414 AT91_REG PIO_PPUDR; // Pull-up Disable Register\r
415 AT91_REG PIO_PPUER; // Pull-up Enable Register\r
416 AT91_REG PIO_PPUSR; // Pull-up Status Register\r
417 AT91_REG Reserved4[1]; //\r
418 AT91_REG PIO_ASR; // Select A Register\r
419 AT91_REG PIO_BSR; // Select B Register\r
420 AT91_REG PIO_ABSR; // AB Select Status Register\r
421 AT91_REG Reserved5[9]; //\r
422 AT91_REG PIO_OWER; // Output Write Enable Register\r
423 AT91_REG PIO_OWDR; // Output Write Disable Register\r
424 AT91_REG PIO_OWSR; // Output Write Status Register\r
425} AT91S_PIO, *AT91PS_PIO;\r
426#else\r
427#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register\r
428#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register\r
429#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register\r
430#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register\r
431#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr\r
432#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register\r
433#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register\r
434#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register\r
435#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register\r
436#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register\r
437#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register\r
438#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register\r
439#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register\r
440#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register\r
441#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register\r
442#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register\r
443#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register\r
444#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register\r
445#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register\r
446#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register\r
447#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register\r
448#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register\r
449#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register\r
450#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register\r
451#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register\r
452#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register\r
453#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register\r
454#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register\r
455#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register\r
456\r
457#endif\r
458\r
459// *****************************************************************************\r
460// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
461// *****************************************************************************\r
462#ifndef __ASSEMBLY__\r
463typedef struct _AT91S_CKGR {\r
464 AT91_REG CKGR_MOR; // Main Oscillator Register\r
465 AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
466 AT91_REG Reserved0[1]; //\r
467 AT91_REG CKGR_PLLR; // PLL Register\r
468} AT91S_CKGR, *AT91PS_CKGR;\r
469#else\r
470#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register\r
471#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register\r
472#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register\r
473\r
474#endif\r
475// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------\r
476#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable\r
477#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass\r
478#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time\r
479// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------\r
480#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency\r
481#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready\r
482// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------\r
483#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected\r
484#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0\r
485#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed\r
486#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter\r
487#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range\r
488#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet\r
489#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet\r
490#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet\r
491#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet\r
492#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier\r
493#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks\r
494#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output\r
495#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2\r
496#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4\r
497\r
498// *****************************************************************************\r
499// SOFTWARE API DEFINITION FOR Power Management Controler\r
500// *****************************************************************************\r
501#ifndef __ASSEMBLY__\r
502typedef struct _AT91S_PMC {\r
503 AT91_REG PMC_SCER; // System Clock Enable Register\r
504 AT91_REG PMC_SCDR; // System Clock Disable Register\r
505 AT91_REG PMC_SCSR; // System Clock Status Register\r
506 AT91_REG Reserved0[1]; //\r
507 AT91_REG PMC_PCER; // Peripheral Clock Enable Register\r
508 AT91_REG PMC_PCDR; // Peripheral Clock Disable Register\r
509 AT91_REG PMC_PCSR; // Peripheral Clock Status Register\r
510 AT91_REG Reserved1[1]; //\r
511 AT91_REG PMC_MOR; // Main Oscillator Register\r
512 AT91_REG PMC_MCFR; // Main Clock Frequency Register\r
513 AT91_REG Reserved2[1]; //\r
514 AT91_REG PMC_PLLR; // PLL Register\r
515 AT91_REG PMC_MCKR; // Master Clock Register\r
516 AT91_REG Reserved3[3]; //\r
517 AT91_REG PMC_PCKR[3]; // Programmable Clock Register\r
518 AT91_REG Reserved4[5]; //\r
519 AT91_REG PMC_IER; // Interrupt Enable Register\r
520 AT91_REG PMC_IDR; // Interrupt Disable Register\r
521 AT91_REG PMC_SR; // Status Register\r
522 AT91_REG PMC_IMR; // Interrupt Mask Register\r
523} AT91S_PMC, *AT91PS_PMC;\r
524#else\r
525#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register\r
526#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register\r
527#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register\r
528#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register\r
529#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register\r
530#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register\r
531#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register\r
532#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register\r
533#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register\r
534#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register\r
535#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register\r
536#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register\r
537\r
538#endif\r
539// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------\r
540#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock\r
541#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock\r
542#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output\r
543#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output\r
544#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output\r
545// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------\r
546// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------\r
547// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------\r
548// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------\r
549// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------\r
550// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------\r
551#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection\r
552#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected\r
553#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected\r
554#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected\r
555#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler\r
556#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock\r
557#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2\r
558#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4\r
559#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8\r
560#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16\r
561#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32\r
562#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64\r
563// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------\r
564// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------\r
565#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask\r
566#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask\r
567#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\r
568#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\r
569#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\r
570#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\r
571// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------\r
572// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------\r
573// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------\r
574\r
575// *****************************************************************************\r
576// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
577// *****************************************************************************\r
578#ifndef __ASSEMBLY__\r
579typedef struct _AT91S_RSTC {\r
580 AT91_REG RSTC_RCR; // Reset Control Register\r
581 AT91_REG RSTC_RSR; // Reset Status Register\r
582 AT91_REG RSTC_RMR; // Reset Mode Register\r
583} AT91S_RSTC, *AT91PS_RSTC;\r
584#else\r
585#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register\r
586#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register\r
587#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register\r
588\r
589#endif\r
590// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------\r
591#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset\r
592#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset\r
593#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset\r
594#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password\r
595// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------\r
596#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status\r
597#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status\r
598#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type\r
599#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.\r
600#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.\r
601#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.\r
602#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.\r
603#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.\r
604#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.\r
605#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level\r
606#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.\r
607// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------\r
608#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable\r
609#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable\r
610#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length\r
611#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable\r
612\r
613// *****************************************************************************\r
614// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
615// *****************************************************************************\r
616#ifndef __ASSEMBLY__\r
617typedef struct _AT91S_RTTC {\r
618 AT91_REG RTTC_RTMR; // Real-time Mode Register\r
619 AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
620 AT91_REG RTTC_RTVR; // Real-time Value Register\r
621 AT91_REG RTTC_RTSR; // Real-time Status Register\r
622} AT91S_RTTC, *AT91PS_RTTC;\r
623#else\r
624#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register\r
625#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register\r
626#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register\r
627#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register\r
628\r
629#endif\r
630// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------\r
631#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
632#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
633#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable\r
634#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart\r
635// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------\r
636#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value\r
637// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------\r
638#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value\r
639// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------\r
640#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status\r
641#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment\r
642\r
643// *****************************************************************************\r
644// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
645// *****************************************************************************\r
646#ifndef __ASSEMBLY__\r
647typedef struct _AT91S_PITC {\r
648 AT91_REG PITC_PIMR; // Period Interval Mode Register\r
649 AT91_REG PITC_PISR; // Period Interval Status Register\r
650 AT91_REG PITC_PIVR; // Period Interval Value Register\r
651 AT91_REG PITC_PIIR; // Period Interval Image Register\r
652} AT91S_PITC, *AT91PS_PITC;\r
653#else\r
654#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register\r
655#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register\r
656#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register\r
657#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register\r
658\r
659#endif\r
660// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------\r
661#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value\r
662#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
663#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable\r
664// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------\r
665#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status\r
666// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------\r
667#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value\r
668#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter\r
669// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------\r
670\r
671// *****************************************************************************\r
672// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
673// *****************************************************************************\r
674#ifndef __ASSEMBLY__\r
675typedef struct _AT91S_WDTC {\r
676 AT91_REG WDTC_WDCR; // Watchdog Control Register\r
677 AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
678 AT91_REG WDTC_WDSR; // Watchdog Status Register\r
679} AT91S_WDTC, *AT91PS_WDTC;\r
680#else\r
681#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register\r
682#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register\r
683#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register\r
684\r
685#endif\r
686// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------\r
687#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart\r
688#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password\r
689// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------\r
690#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart\r
691#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable\r
692#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable\r
693#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart\r
694#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable\r
695#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value\r
696#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt\r
697#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt\r
698// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------\r
699#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow\r
700#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error\r
701\r
702// *****************************************************************************\r
703// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
704// *****************************************************************************\r
705#ifndef __ASSEMBLY__\r
706typedef struct _AT91S_VREG {\r
707 AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
708} AT91S_VREG, *AT91PS_VREG;\r
709#else\r
710#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register\r
711\r
712#endif\r
713// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------\r
714#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
715\r
716// *****************************************************************************\r
717// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface\r
718// *****************************************************************************\r
719#ifndef __ASSEMBLY__\r
720typedef struct _AT91S_EFC {\r
721 AT91_REG EFC_FMR; // MC Flash Mode Register\r
722 AT91_REG EFC_FCR; // MC Flash Command Register\r
723 AT91_REG EFC_FSR; // MC Flash Status Register\r
724 AT91_REG EFC_VR; // MC Flash Version Register\r
725} AT91S_EFC, *AT91PS_EFC;\r
726#else\r
727#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register\r
728#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register\r
729#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register\r
730#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register\r
731\r
732#endif\r
733// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------\r
734#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready\r
735#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error\r
736#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error\r
737#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming\r
738#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State\r
739#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations\r
740#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations\r
741#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations\r
742#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations\r
743#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number\r
744// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------\r
745#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command\r
746#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN.\r
747#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
748#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.\r
749#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.\r
750#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.\r
751#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits.\r
752#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits.\r
753#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit.\r
754#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number\r
755#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key\r
756// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------\r
757#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status\r
758#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status\r
759#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status\r
760#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status\r
761#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status\r
762#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status\r
763#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status\r
764#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status\r
765#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status\r
766#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status\r
767#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status\r
768#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status\r
769#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status\r
770#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status\r
771#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status\r
772#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status\r
773#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status\r
774#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status\r
775#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status\r
776#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status\r
777#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status\r
778#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status\r
779#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status\r
780#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status\r
781#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status\r
782// -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------\r
783#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number\r
784#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN\r
785\r
786// *****************************************************************************\r
787// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
788// *****************************************************************************\r
789#ifndef __ASSEMBLY__\r
790typedef struct _AT91S_MC {\r
791 AT91_REG MC_RCR; // MC Remap Control Register\r
792 AT91_REG MC_ASR; // MC Abort Status Register\r
793 AT91_REG MC_AASR; // MC Abort Address Status Register\r
794 AT91_REG Reserved0[1]; //\r
795 AT91_REG MC_PUIA[16]; // MC Protection Unit Area\r
796 AT91_REG MC_PUP; // MC Protection Unit Peripherals\r
797 AT91_REG MC_PUER; // MC Protection Unit Enable Register\r
798 AT91_REG Reserved1[2]; //\r
799 AT91_REG MC0_FMR; // MC Flash Mode Register\r
800 AT91_REG MC0_FCR; // MC Flash Command Register\r
801 AT91_REG MC0_FSR; // MC Flash Status Register\r
802 AT91_REG MC0_VR; // MC Flash Version Register\r
803 AT91_REG MC1_FMR; // MC Flash Mode Register\r
804 AT91_REG MC1_FCR; // MC Flash Command Register\r
805 AT91_REG MC1_FSR; // MC Flash Status Register\r
806 AT91_REG MC1_VR; // MC Flash Version Register\r
807} AT91S_MC, *AT91PS_MC;\r
808#else\r
809#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register\r
810#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register\r
811#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register\r
812#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area\r
813#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals\r
814#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register\r
815\r
816#endif\r
817// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------\r
818#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit\r
819// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------\r
820#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status\r
821#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status\r
822#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status\r
823#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status\r
824#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte\r
825#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word\r
826#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word\r
827#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status\r
828#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read\r
829#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write\r
830#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch\r
831#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source\r
832#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source\r
833#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source\r
834#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source\r
835// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------\r
836#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection\r
837#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access\r
838#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access\r
839#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only\r
840#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write\r
841#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size\r
842#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte\r
843#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte\r
844#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte\r
845#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte\r
846#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte\r
847#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte\r
848#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte\r
849#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte\r
850#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte\r
851#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte\r
852#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte\r
853#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte\r
854#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte\r
855#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte\r
856#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte\r
857#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte\r
858#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address\r
859// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------\r
860// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------\r
861#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit\r
862\r
863// *****************************************************************************\r
864// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
865// *****************************************************************************\r
866#ifndef __ASSEMBLY__\r
867typedef struct _AT91S_SPI {\r
868 AT91_REG SPI_CR; // Control Register\r
869 AT91_REG SPI_MR; // Mode Register\r
870 AT91_REG SPI_RDR; // Receive Data Register\r
871 AT91_REG SPI_TDR; // Transmit Data Register\r
872 AT91_REG SPI_SR; // Status Register\r
873 AT91_REG SPI_IER; // Interrupt Enable Register\r
874 AT91_REG SPI_IDR; // Interrupt Disable Register\r
875 AT91_REG SPI_IMR; // Interrupt Mask Register\r
876 AT91_REG Reserved0[4]; //\r
877 AT91_REG SPI_CSR[4]; // Chip Select Register\r
878 AT91_REG Reserved1[48]; //\r
879 AT91_REG SPI_RPR; // Receive Pointer Register\r
880 AT91_REG SPI_RCR; // Receive Counter Register\r
881 AT91_REG SPI_TPR; // Transmit Pointer Register\r
882 AT91_REG SPI_TCR; // Transmit Counter Register\r
883 AT91_REG SPI_RNPR; // Receive Next Pointer Register\r
884 AT91_REG SPI_RNCR; // Receive Next Counter Register\r
885 AT91_REG SPI_TNPR; // Transmit Next Pointer Register\r
886 AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
887 AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
888 AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
889} AT91S_SPI, *AT91PS_SPI;\r
890#else\r
891#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register\r
892#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register\r
893#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register\r
894#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register\r
895#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register\r
896#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register\r
897#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register\r
898#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register\r
899#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register\r
900\r
901#endif\r
902// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------\r
903#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable\r
904#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable\r
905#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset\r
906#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer\r
907// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------\r
908#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode\r
909#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select\r
910#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select\r
911#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select\r
912#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode\r
913#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection\r
914#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection\r
915#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection\r
916#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select\r
917#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects\r
918// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------\r
919#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data\r
920#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
921// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------\r
922#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data\r
923#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status\r
924// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------\r
925#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full\r
926#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty\r
927#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error\r
928#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status\r
929#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer\r
930#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer\r
931#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt\r
932#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt\r
933#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt\r
934#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt\r
935#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status\r
936// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------\r
937// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------\r
938// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------\r
939// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------\r
940#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity\r
941#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase\r
942#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer\r
943#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer\r
944#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer\r
945#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer\r
946#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer\r
947#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer\r
948#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer\r
949#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer\r
950#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer\r
951#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer\r
952#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer\r
953#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate\r
954#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK\r
955#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\r
956\r
957// *****************************************************************************\r
958// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
959// *****************************************************************************\r
960#ifndef __ASSEMBLY__\r
961typedef struct _AT91S_ADC {\r
962 AT91_REG ADC_CR; // ADC Control Register\r
963 AT91_REG ADC_MR; // ADC Mode Register\r
964 AT91_REG Reserved0[2]; //\r
965 AT91_REG ADC_CHER; // ADC Channel Enable Register\r
966 AT91_REG ADC_CHDR; // ADC Channel Disable Register\r
967 AT91_REG ADC_CHSR; // ADC Channel Status Register\r
968 AT91_REG ADC_SR; // ADC Status Register\r
969 AT91_REG ADC_LCDR; // ADC Last Converted Data Register\r
970 AT91_REG ADC_IER; // ADC Interrupt Enable Register\r
971 AT91_REG ADC_IDR; // ADC Interrupt Disable Register\r
972 AT91_REG ADC_IMR; // ADC Interrupt Mask Register\r
973 AT91_REG ADC_CDR[8]; // ADC Channel Data Register\r
974 AT91_REG Reserved1[44]; //\r
975 AT91_REG ADC_RPR; // Receive Pointer Register\r
976 AT91_REG ADC_RCR; // Receive Counter Register\r
977 AT91_REG ADC_TPR; // Transmit Pointer Register\r
978 AT91_REG ADC_TCR; // Transmit Counter Register\r
979 AT91_REG ADC_RNPR; // Receive Next Pointer Register\r
980 AT91_REG ADC_RNCR; // Receive Next Counter Register\r
981 AT91_REG ADC_TNPR; // Transmit Next Pointer Register\r
982 AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
983 AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
984 AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
985} AT91S_ADC, *AT91PS_ADC;\r
986#else\r
987#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register\r
988#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register\r
989#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register\r
990#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register\r
991#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register\r
992#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register\r
993#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register\r
994#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register\r
995#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register\r
996#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register\r
997#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0\r
998#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1\r
999#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2\r
1000#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3\r
1001#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4\r
1002#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5\r
1003#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6\r
1004#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7\r
1005\r
1006#endif\r
1007// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------\r
1008#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset\r
1009#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion\r
1010// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------\r
1011#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable\r
1012#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software\r
1013#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.\r
1014#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection\r
1015#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0\r
1016#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1\r
1017#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2\r
1018#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3\r
1019#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4\r
1020#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5\r
1021#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger\r
1022#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.\r
1023#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution\r
1024#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution\r
1025#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode\r
1026#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode\r
1027#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode\r
1028#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection\r
1029#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time\r
1030#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time\r
1031// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------\r
1032#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0\r
1033#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1\r
1034#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2\r
1035#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3\r
1036#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4\r
1037#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5\r
1038#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6\r
1039#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7\r
1040// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------\r
1041// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------\r
1042// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------\r
1043#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion\r
1044#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion\r
1045#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion\r
1046#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion\r
1047#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion\r
1048#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion\r
1049#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion\r
1050#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion\r
1051#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error\r
1052#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error\r
1053#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error\r
1054#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error\r
1055#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error\r
1056#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error\r
1057#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error\r
1058#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error\r
1059#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready\r
1060#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun\r
1061#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer\r
1062#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt\r
1063// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------\r
1064#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted\r
1065// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------\r
1066// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------\r
1067// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------\r
1068// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------\r
1069#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data\r
1070// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------\r
1071// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------\r
1072// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------\r
1073// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------\r
1074// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------\r
1075// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------\r
1076// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------\r
1077\r
1078// *****************************************************************************\r
1079// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
1080// *****************************************************************************\r
1081#ifndef __ASSEMBLY__\r
1082typedef struct _AT91S_SSC {\r
1083 AT91_REG SSC_CR; // Control Register\r
1084 AT91_REG SSC_CMR; // Clock Mode Register\r
1085 AT91_REG Reserved0[2]; //\r
1086 AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
1087 AT91_REG SSC_RFMR; // Receive Frame Mode Register\r
1088 AT91_REG SSC_TCMR; // Transmit Clock Mode Register\r
1089 AT91_REG SSC_TFMR; // Transmit Frame Mode Register\r
1090 AT91_REG SSC_RHR; // Receive Holding Register\r
1091 AT91_REG SSC_THR; // Transmit Holding Register\r
1092 AT91_REG Reserved1[2]; //\r
1093 AT91_REG SSC_RSHR; // Receive Sync Holding Register\r
1094 AT91_REG SSC_TSHR; // Transmit Sync Holding Register\r
1095 AT91_REG Reserved2[2]; //\r
1096 AT91_REG SSC_SR; // Status Register\r
1097 AT91_REG SSC_IER; // Interrupt Enable Register\r
1098 AT91_REG SSC_IDR; // Interrupt Disable Register\r
1099 AT91_REG SSC_IMR; // Interrupt Mask Register\r
1100 AT91_REG Reserved3[44]; //\r
1101 AT91_REG SSC_RPR; // Receive Pointer Register\r
1102 AT91_REG SSC_RCR; // Receive Counter Register\r
1103 AT91_REG SSC_TPR; // Transmit Pointer Register\r
1104 AT91_REG SSC_TCR; // Transmit Counter Register\r
1105 AT91_REG SSC_RNPR; // Receive Next Pointer Register\r
1106 AT91_REG SSC_RNCR; // Receive Next Counter Register\r
1107 AT91_REG SSC_TNPR; // Transmit Next Pointer Register\r
1108 AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
1109 AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
1110 AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
1111} AT91S_SSC, *AT91PS_SSC;\r
1112#else\r
1113#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register\r
1114#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register\r
1115#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister\r
1116#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register\r
1117#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register\r
1118#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register\r
1119#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register\r
1120#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register\r
1121#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register\r
1122#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register\r
1123#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register\r
1124#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register\r
1125#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register\r
1126#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register\r
1127\r
1128#endif\r
1129// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------\r
1130#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable\r
1131#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable\r
1132#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable\r
1133#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable\r
1134#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset\r
1135// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------\r
1136#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection\r
1137#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock\r
1138#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal\r
1139#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin\r
1140#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection\r
1141#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\r
1142#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\r
1143#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\r
1144#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion\r
1145#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection\r
1146#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\r
1147#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start\r
1148#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input\r
1149#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input\r
1150#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input\r
1151#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input\r
1152#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input\r
1153#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input\r
1154#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0\r
1155#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay\r
1156#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\r
1157// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------\r
1158#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length\r
1159#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode\r
1160#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First\r
1161#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame\r
1162#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\r
1163#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\r
1164#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\r
1165#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\r
1166#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\r
1167#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\r
1168#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\r
1169#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\r
1170#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection\r
1171// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------\r
1172// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------\r
1173#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value\r
1174#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable\r
1175// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------\r
1176#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready\r
1177#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty\r
1178#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission\r
1179#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty\r
1180#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready\r
1181#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun\r
1182#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception\r
1183#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full\r
1184#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync\r
1185#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync\r
1186#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable\r
1187#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable\r
1188// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------\r
1189// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------\r
1190// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------\r
1191\r
1192// *****************************************************************************\r
1193// SOFTWARE API DEFINITION FOR Usart\r
1194// *****************************************************************************\r
1195#ifndef __ASSEMBLY__\r
1196typedef struct _AT91S_USART {\r
1197 AT91_REG US_CR; // Control Register\r
1198 AT91_REG US_MR; // Mode Register\r
1199 AT91_REG US_IER; // Interrupt Enable Register\r
1200 AT91_REG US_IDR; // Interrupt Disable Register\r
1201 AT91_REG US_IMR; // Interrupt Mask Register\r
1202 AT91_REG US_CSR; // Channel Status Register\r
1203 AT91_REG US_RHR; // Receiver Holding Register\r
1204 AT91_REG US_THR; // Transmitter Holding Register\r
1205 AT91_REG US_BRGR; // Baud Rate Generator Register\r
1206 AT91_REG US_RTOR; // Receiver Time-out Register\r
1207 AT91_REG US_TTGR; // Transmitter Time-guard Register\r
1208 AT91_REG Reserved0[5]; //\r
1209 AT91_REG US_FIDI; // FI_DI_Ratio Register\r
1210 AT91_REG US_NER; // Nb Errors Register\r
1211 AT91_REG Reserved1[1]; //\r
1212 AT91_REG US_IF; // IRDA_FILTER Register\r
1213 AT91_REG Reserved2[44]; //\r
1214 AT91_REG US_RPR; // Receive Pointer Register\r
1215 AT91_REG US_RCR; // Receive Counter Register\r
1216 AT91_REG US_TPR; // Transmit Pointer Register\r
1217 AT91_REG US_TCR; // Transmit Counter Register\r
1218 AT91_REG US_RNPR; // Receive Next Pointer Register\r
1219 AT91_REG US_RNCR; // Receive Next Counter Register\r
1220 AT91_REG US_TNPR; // Transmit Next Pointer Register\r
1221 AT91_REG US_TNCR; // Transmit Next Counter Register\r
1222 AT91_REG US_PTCR; // PDC Transfer Control Register\r
1223 AT91_REG US_PTSR; // PDC Transfer Status Register\r
1224} AT91S_USART, *AT91PS_USART;\r
1225#else\r
1226#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register\r
1227#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register\r
1228#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register\r
1229#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register\r
1230#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register\r
1231#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register\r
1232#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register\r
1233#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register\r
1234#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register\r
1235#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register\r
1236#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register\r
1237#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register\r
1238#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register\r
1239#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register\r
1240\r
1241#endif\r
1242// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------\r
1243#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break\r
1244#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break\r
1245#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out\r
1246#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address\r
1247#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations\r
1248#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge\r
1249#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out\r
1250#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable\r
1251#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable\r
1252#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable\r
1253#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable\r
1254// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------\r
1255#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode\r
1256#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal\r
1257#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485\r
1258#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking\r
1259#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem\r
1260#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0\r
1261#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1\r
1262#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA\r
1263#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking\r
1264#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock\r
1265#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock\r
1266#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1\r
1267#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)\r
1268#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)\r
1269#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock\r
1270#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits\r
1271#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits\r
1272#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits\r
1273#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits\r
1274#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select\r
1275#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits\r
1276#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit\r
1277#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\r
1278#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits\r
1279#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order\r
1280#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length\r
1281#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select\r
1282#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode\r
1283#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge\r
1284#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK\r
1285#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions\r
1286#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter\r
1287// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------\r
1288#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break\r
1289#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out\r
1290#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached\r
1291#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge\r
1292#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag\r
1293#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag\r
1294#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag\r
1295#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag\r
1296// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------\r
1297// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------\r
1298// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------\r
1299#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input\r
1300#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input\r
1301#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input\r
1302#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input\r
1303\r
1304// *****************************************************************************\r
1305// SOFTWARE API DEFINITION FOR Two-wire Interface\r
1306// *****************************************************************************\r
1307#ifndef __ASSEMBLY__\r
1308typedef struct _AT91S_TWI {\r
1309 AT91_REG TWI_CR; // Control Register\r
1310 AT91_REG TWI_MMR; // Master Mode Register\r
1311 AT91_REG Reserved0[1]; //\r
1312 AT91_REG TWI_IADR; // Internal Address Register\r
1313 AT91_REG TWI_CWGR; // Clock Waveform Generator Register\r
1314 AT91_REG Reserved1[3]; //\r
1315 AT91_REG TWI_SR; // Status Register\r
1316 AT91_REG TWI_IER; // Interrupt Enable Register\r
1317 AT91_REG TWI_IDR; // Interrupt Disable Register\r
1318 AT91_REG TWI_IMR; // Interrupt Mask Register\r
1319 AT91_REG TWI_RHR; // Receive Holding Register\r
1320 AT91_REG TWI_THR; // Transmit Holding Register\r
1321 AT91_REG Reserved2[50]; //\r
1322 AT91_REG TWI_RPR; // Receive Pointer Register\r
1323 AT91_REG TWI_RCR; // Receive Counter Register\r
1324 AT91_REG TWI_TPR; // Transmit Pointer Register\r
1325 AT91_REG TWI_TCR; // Transmit Counter Register\r
1326 AT91_REG TWI_RNPR; // Receive Next Pointer Register\r
1327 AT91_REG TWI_RNCR; // Receive Next Counter Register\r
1328 AT91_REG TWI_TNPR; // Transmit Next Pointer Register\r
1329 AT91_REG TWI_TNCR; // Transmit Next Counter Register\r
1330 AT91_REG TWI_PTCR; // PDC Transfer Control Register\r
1331 AT91_REG TWI_PTSR; // PDC Transfer Status Register\r
1332} AT91S_TWI, *AT91PS_TWI;\r
1333#else\r
1334#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register\r
1335#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register\r
1336#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register\r
1337#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register\r
1338#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register\r
1339#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register\r
1340#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register\r
1341#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register\r
1342#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register\r
1343#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register\r
1344\r
1345#endif\r
1346// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------\r
1347#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition\r
1348#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition\r
1349#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled\r
1350#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled\r
1351#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset\r
1352// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------\r
1353#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size\r
1354#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address\r
1355#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address\r
1356#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address\r
1357#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address\r
1358#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction\r
1359#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address\r
1360// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------\r
1361#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider\r
1362#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider\r
1363#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider\r
1364// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------\r
1365#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed\r
1366#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY\r
1367#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY\r
1368#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error\r
1369#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error\r
1370#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged\r
1371#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)\r
1372#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)\r
1373#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)\r
1374#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)\r
1375// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------\r
1376// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------\r
1377// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------\r
1378\r
1379// *****************************************************************************\r
1380// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
1381// *****************************************************************************\r
1382#ifndef __ASSEMBLY__\r
1383typedef struct _AT91S_TC {\r
1384 AT91_REG TC_CCR; // Channel Control Register\r
1385 AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
1386 AT91_REG Reserved0[2]; //\r
1387 AT91_REG TC_CV; // Counter Value\r
1388 AT91_REG TC_RA; // Register A\r
1389 AT91_REG TC_RB; // Register B\r
1390 AT91_REG TC_RC; // Register C\r
1391 AT91_REG TC_SR; // Status Register\r
1392 AT91_REG TC_IER; // Interrupt Enable Register\r
1393 AT91_REG TC_IDR; // Interrupt Disable Register\r
1394 AT91_REG TC_IMR; // Interrupt Mask Register\r
1395} AT91S_TC, *AT91PS_TC;\r
1396#else\r
1397#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register\r
1398#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)\r
1399#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value\r
1400#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A\r
1401#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B\r
1402#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C\r
1403#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register\r
1404#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register\r
1405#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register\r
1406#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register\r
1407\r
1408#endif\r
1409// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------\r
1410#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command\r
1411#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command\r
1412#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command\r
1413// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------\r
1414#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection\r
1415#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK\r
1416#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK\r
1417#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK\r
1418#define T91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK\r
1419#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK\r
1420#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0\r
1421#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1\r
1422#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2\r
1423#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert\r
1424#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection\r
1425#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal\r
1426#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock\r
1427#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock\r
1428#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock\r
1429#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare\r
1430#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading\r
1431#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare\r
1432#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading\r
1433#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection\r
1434#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None\r
1435#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
1436#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
1437#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
1438#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection\r
1439#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None\r
1440#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge\r
1441#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge\r
1442#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge\r
1443#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection\r
1444#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\r
1445#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\r
1446#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\r
1447#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\r
1448#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection\r
1449#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable\r
1450#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection\r
1451#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\r
1452#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\r
1453#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\r
1454#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\r
1455#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable\r
1456#define AT91C_TC_WAVE (0x1 << 15) // (TC)\r
1457#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA\r
1458#define T91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none\r
1459#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set\r
1460#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear\r
1461#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle\r
1462#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection\r
1463#define T91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None\r
1464#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA\r
1465#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA\r
1466#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA\r
1467#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA\r
1468#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none\r
1469#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set\r
1470#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear\r
1471#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle\r
1472#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection\r
1473#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None\r
1474#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA\r
1475#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA\r
1476#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA\r
1477#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA\r
1478#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none\r
1479#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set\r
1480#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear\r
1481#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle\r
1482#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA\r
1483#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none\r
1484#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set\r
1485#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear\r
1486#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle\r
1487#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB\r
1488#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none\r
1489#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set\r
1490#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear\r
1491#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle\r
1492#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB\r
1493#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none\r
1494#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set\r
1495#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear\r
1496#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle\r
1497#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB\r
1498#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none\r
1499#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set\r
1500#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear\r
1501#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle\r
1502#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB\r
1503#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none\r
1504#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set\r
1505#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear\r
1506#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle\r
1507// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------\r
1508#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow\r
1509#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun\r
1510#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare\r
1511#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare\r
1512#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare\r
1513#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading\r
1514#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading\r
1515#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger\r
1516#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling\r
1517#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror\r
1518#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror\r
1519// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------\r
1520// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------\r
1521// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------\r
1522\r
1523// *****************************************************************************\r
1524// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
1525// *****************************************************************************\r
1526#ifndef __ASSEMBLY__\r
1527typedef struct _AT91S_TCB {\r
1528 AT91S_TC TCB_TC0; // TC Channel 0\r
1529 AT91_REG Reserved0[4]; //\r
1530 AT91S_TC TCB_TC1; // TC Channel 1\r
1531 AT91_REG Reserved1[4]; //\r
1532 AT91S_TC TCB_TC2; // TC Channel 2\r
1533 AT91_REG Reserved2[4]; //\r
1534 AT91_REG TCB_BCR; // TC Block Control Register\r
1535 AT91_REG TCB_BMR; // TC Block Mode Register\r
1536} AT91S_TCB, *AT91PS_TCB;\r
1537#else\r
1538#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register\r
1539#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register\r
1540\r
1541#endif\r
1542// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------\r
1543#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command\r
1544// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------\r
1545#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection\r
1546#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0\r
1547#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0\r
1548#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0\r
1549#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0\r
1550#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection\r
1551#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1\r
1552#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1\r
1553#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1\r
1554#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1\r
1555#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection\r
1556#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2\r
1557#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2\r
1558#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2\r
1559#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2\r
1560\r
1561// *****************************************************************************\r
1562// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
1563// *****************************************************************************\r
1564#ifndef __ASSEMBLY__\r
1565typedef struct _AT91S_PWMC_CH {\r
1566 AT91_REG PWMC_CMR; // Channel Mode Register\r
1567 AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
1568 AT91_REG PWMC_CPRDR; // Channel Period Register\r
1569 AT91_REG PWMC_CCNTR; // Channel Counter Register\r
1570 AT91_REG PWMC_CUPDR; // Channel Update Register\r
1571 AT91_REG PWMC_Reserved[3]; // Reserved\r
1572} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
1573#else\r
1574#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register\r
1575#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register\r
1576#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register\r
1577#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register\r
1578#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register\r
1579#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved\r
1580\r
1581#endif\r
1582// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------\r
1583#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
1584#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)\r
1585#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)\r
1586#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)\r
1587#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment\r
1588#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity\r
1589#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period\r
1590// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------\r
1591#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle\r
1592// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------\r
1593#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period\r
1594// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------\r
1595#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter\r
1596// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------\r
1597#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update\r
1598\r
1599// *****************************************************************************\r
1600// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
1601// *****************************************************************************\r
1602#ifndef __ASSEMBLY__\r
1603typedef struct _AT91S_PWMC {\r
1604 AT91_REG PWMC_MR; // PWMC Mode Register\r
1605 AT91_REG PWMC_ENA; // PWMC Enable Register\r
1606 AT91_REG PWMC_DIS; // PWMC Disable Register\r
1607 AT91_REG PWMC_SR; // PWMC Status Register\r
1608 AT91_REG PWMC_IER; // PWMC Interrupt Enable Register\r
1609 AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register\r
1610 AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register\r
1611 AT91_REG PWMC_ISR; // PWMC Interrupt Status Register\r
1612 AT91_REG Reserved0[55]; //\r
1613 AT91_REG PWMC_VR; // PWMC Version Register\r
1614 AT91_REG Reserved1[64]; //\r
1615 AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel\r
1616} AT91S_PWMC, *AT91PS_PWMC;\r
1617#else\r
1618#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register\r
1619#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register\r
1620#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register\r
1621#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register\r
1622#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register\r
1623#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register\r
1624#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register\r
1625#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register\r
1626#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register\r
1627\r
1628#endif\r
1629// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------\r
1630#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.\r
1631#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
1632#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)\r
1633#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.\r
1634#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B\r
1635#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)\r
1636// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------\r
1637#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0\r
1638#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1\r
1639#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2\r
1640#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3\r
1641// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------\r
1642// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------\r
1643// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------\r
1644// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------\r
1645// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------\r
1646// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------\r
1647\r
1648// *****************************************************************************\r
1649// SOFTWARE API DEFINITION FOR USB Device Interface\r
1650// *****************************************************************************\r
1651#ifndef __ASSEMBLY__\r
1652typedef struct _AT91S_UDP {\r
1653 AT91_REG UDP_NUM; // Frame Number Register\r
1654 AT91_REG UDP_GLBSTATE; // Global State Register\r
1655 AT91_REG UDP_FADDR; // Function Address Register\r
1656 AT91_REG Reserved0[1]; //\r
1657 AT91_REG UDP_IER; // Interrupt Enable Register\r
1658 AT91_REG UDP_IDR; // Interrupt Disable Register\r
1659 AT91_REG UDP_IMR; // Interrupt Mask Register\r
1660 AT91_REG UDP_ISR; // Interrupt Status Register\r
1661 AT91_REG UDP_ICR; // Interrupt Clear Register\r
1662 AT91_REG Reserved1[1]; //\r
1663 AT91_REG UDP_RSTEP; // Reset Endpoint Register\r
1664 AT91_REG Reserved2[1]; //\r
1665 AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register\r
1666 AT91_REG Reserved3[4]; //\r
1667 AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register\r
1668 AT91_REG Reserved4[5]; //\r
1669 AT91_REG UDP_TXVC; // Transceiver Control Register\r
1670} AT91S_UDP, *AT91PS_UDP;\r
1671#else\r
1672#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register\r
1673#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register\r
1674#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register\r
1675#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register\r
1676#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register\r
1677#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register\r
1678#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register\r
1679#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register\r
1680#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register\r
1681#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register\r
1682#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register\r
1683#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register\r
1684\r
1685#endif\r
1686// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------\r
1687#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
1688#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error\r
1689#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK\r
1690// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------\r
1691#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable\r
1692#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured\r
1693#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume\r
1694#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host\r
1695#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable\r
1696// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------\r
1697#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value\r
1698#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable\r
1699// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------\r
1700#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt\r
1701#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt\r
1702#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt\r
1703#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt\r
1704#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt\r
1705#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt\r
1706#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt\r
1707#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt\r
1708#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt\r
1709// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------\r
1710// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------\r
1711// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------\r
1712#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\r
1713// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------\r
1714// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------\r
1715#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0\r
1716#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1\r
1717#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2\r
1718#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3\r
1719// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------\r
1720#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR\r
1721#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0\r
1722#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)\r
1723#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)\r
1724#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)\r
1725#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready\r
1726#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\r
1727#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\r
1728#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction\r
1729#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type\r
1730#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control\r
1731#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT\r
1732#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT\r
1733#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT\r
1734#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN\r
1735#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN\r
1736#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN\r
1737#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle\r
1738#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable\r
1739#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\r
1740// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------\r
1741#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)\r
1742\r
1743// *****************************************************************************\r
1744// REGISTER ADDRESS DEFINITION FOR AT91SAM7S512\r
1745// *****************************************************************************\r
1746// ========== Register definition for SYS peripheral ==========\r
1747// ========== Register definition for AIC peripheral ==========\r
1748#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register\r
1749#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register\r
1750#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register\r
1751#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)\r
1752#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register\r
1753#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register\r
1754#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register\r
1755#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register\r
1756#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register\r
1757#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register\r
1758#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register\r
1759#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register\r
1760#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register\r
1761#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register\r
1762#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register\r
1763#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register\r
1764#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register\r
1765#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register\r
1766// ========== Register definition for PDC_DBGU peripheral ==========\r
1767#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\r
1768#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\r
1769#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\r
1770#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\r
1771#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\r
1772#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register\r
1773#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\r
1774#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\r
1775#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\r
1776#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\r
1777// ========== Register definition for DBGU peripheral ==========\r
1778#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register\r
1779#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register\r
1780#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register\r
1781#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register\r
1782#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register\r
1783#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register\r
1784#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register\r
1785#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register\r
1786#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register\r
1787#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register\r
1788#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register\r
1789#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register\r
1790// ========== Register definition for PIOA peripheral ==========\r
1791#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr\r
1792#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register\r
1793#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register\r
1794#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register\r
1795#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register\r
1796#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register\r
1797#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register\r
1798#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register\r
1799#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register\r
1800#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register\r
1801#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register\r
1802#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register\r
1803#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register\r
1804#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register\r
1805#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register\r
1806#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register\r
1807#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register\r
1808#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register\r
1809#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register\r
1810#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register\r
1811#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register\r
1812#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register\r
1813#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register\r
1814#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register\r
1815#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register\r
1816#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register\r
1817#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register\r
1818#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register\r
1819#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register\r
1820// ========== Register definition for CKGR peripheral ==========\r
1821#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register\r
1822#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register\r
1823#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register\r
1824// ========== Register definition for PMC peripheral ==========\r
1825#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register\r
1826#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register\r
1827#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register\r
1828#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\r
1829#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register\r
1830#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register\r
1831#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register\r
1832#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\r
1833#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register\r
1834#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register\r
1835#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register\r
1836#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register\r
1837#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register\r
1838#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register\r
1839#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register\r
1840// ========== Register definition for RSTC peripheral ==========\r
1841#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register\r
1842#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register\r
1843#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register\r
1844// ========== Register definition for RTTC peripheral ==========\r
1845#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register\r
1846#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register\r
1847#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register\r
1848#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register\r
1849// ========== Register definition for PITC peripheral ==========\r
1850#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register\r
1851#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register\r
1852#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register\r
1853#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register\r
1854// ========== Register definition for WDTC peripheral ==========\r
1855#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register\r
1856#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register\r
1857#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register\r
1858// ========== Register definition for VREG peripheral ==========\r
1859#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register\r
1860// ========== Register definition for EFC0 peripheral ==========\r
1861#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register\r
1862#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register\r
1863#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register\r
1864#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register\r
1865// ========== Register definition for EFC1 peripheral ==========\r
1866#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register\r
1867#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register\r
1868#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register\r
1869#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register\r
1870// ========== Register definition for MC peripheral ==========\r
1871#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register\r
1872#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register\r
1873#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals\r
1874#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area\r
1875#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register\r
1876#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register\r
1877// ========== Register definition for PDC_SPI peripheral ==========\r
1878#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register\r
1879#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register\r
1880#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register\r
1881#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register\r
1882#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register\r
1883#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register\r
1884#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register\r
1885#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register\r
1886#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register\r
1887#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register\r
1888// ========== Register definition for SPI peripheral ==========\r
1889#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register\r
1890#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register\r
1891#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register\r
1892#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register\r
1893#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register\r
1894#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register\r
1895#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register\r
1896#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register\r
1897#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register\r
1898// ========== Register definition for PDC_ADC peripheral ==========\r
1899#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register\r
1900#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register\r
1901#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register\r
1902#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register\r
1903#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register\r
1904#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register\r
1905#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register\r
1906#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register\r
1907#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register\r
1908#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register\r
1909// ========== Register definition for ADC peripheral ==========\r
1910#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2\r
1911#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3\r
1912#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0\r
1913#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5\r
1914#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register\r
1915#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register\r
1916#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4\r
1917#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1\r
1918#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register\r
1919#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register\r
1920#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register\r
1921#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7\r
1922#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6\r
1923#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register\r
1924#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register\r
1925#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register\r
1926#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register\r
1927#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register\r
1928// ========== Register definition for PDC_SSC peripheral ==========\r
1929#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register\r
1930#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register\r
1931#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register\r
1932#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register\r
1933#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register\r
1934#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register\r
1935#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register\r
1936#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register\r
1937#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register\r
1938#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register\r
1939// ========== Register definition for SSC peripheral ==========\r
1940#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register\r
1941#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register\r
1942#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register\r
1943#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register\r
1944#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register\r
1945#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister\r
1946#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register\r
1947#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register\r
1948#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register\r
1949#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register\r
1950#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register\r
1951#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register\r
1952#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register\r
1953#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register\r
1954// ========== Register definition for PDC_US1 peripheral ==========\r
1955#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register\r
1956#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\r
1957#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register\r
1958#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\r
1959#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\r
1960#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register\r
1961#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\r
1962#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register\r
1963#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\r
1964#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register\r
1965// ========== Register definition for US1 peripheral ==========\r
1966#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register\r
1967#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register\r
1968#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register\r
1969#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register\r
1970#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register\r
1971#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register\r
1972#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register\r
1973#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register\r
1974#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register\r
1975#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register\r
1976#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register\r
1977#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register\r
1978#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register\r
1979#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register\r
1980// ========== Register definition for PDC_US0 peripheral ==========\r
1981#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\r
1982#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\r
1983#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register\r
1984#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\r
1985#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\r
1986#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\r
1987#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register\r
1988#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register\r
1989#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register\r
1990#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register\r
1991// ========== Register definition for US0 peripheral ==========\r
1992#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register\r
1993#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register\r
1994#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register\r
1995#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register\r
1996#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register\r
1997#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register\r
1998#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register\r
1999#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register\r
2000#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register\r
2001#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register\r
2002#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register\r
2003#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register\r
2004#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register\r
2005#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register\r
2006// ========== Register definition for TWI peripheral ==========\r
2007#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register\r
2008#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register\r
2009#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register\r
2010#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register\r
2011#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register\r
2012#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register\r
2013#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register\r
2014#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register\r
2015#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register\r
2016#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register\r
2017// ========== Register definition for TC0 peripheral ==========\r
2018#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register\r
2019#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C\r
2020#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B\r
2021#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register\r
2022#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
2023#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register\r
2024#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A\r
2025#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register\r
2026#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value\r
2027#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register\r
2028// ========== Register definition for TC1 peripheral ==========\r
2029#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B\r
2030#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register\r
2031#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register\r
2032#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register\r
2033#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register\r
2034#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
2035#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A\r
2036#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C\r
2037#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register\r
2038#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value\r
2039// ========== Register definition for TC2 peripheral ==========\r
2040#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
2041#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register\r
2042#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value\r
2043#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A\r
2044#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B\r
2045#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register\r
2046#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register\r
2047#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C\r
2048#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register\r
2049#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register\r
2050// ========== Register definition for TCB peripheral ==========\r
2051#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register\r
2052#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register\r
2053// ========== Register definition for PWMC_CH3 peripheral ==========\r
2054#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
2055#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved\r
2056#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
2057#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
2058#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
2059#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
2060// ========== Register definition for PWMC_CH2 peripheral ==========\r
2061#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved\r
2062#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
2063#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
2064#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register\r
2065#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
2066#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
2067// ========== Register definition for PWMC_CH1 peripheral ==========\r
2068#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved\r
2069#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
2070#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
2071#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register\r
2072#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
2073#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
2074// ========== Register definition for PWMC_CH0 peripheral ==========\r
2075#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved\r
2076#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
2077#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
2078#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register\r
2079#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
2080#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
2081// ========== Register definition for PWMC peripheral ==========\r
2082#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register\r
2083#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register\r
2084#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register\r
2085#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register\r
2086#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register\r
2087#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register\r
2088#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register\r
2089#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register\r
2090#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register\r
2091// ========== Register definition for UDP peripheral ==========\r
2092#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register\r
2093#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register\r
2094#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register\r
2095#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register\r
2096#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register\r
2097#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register\r
2098#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register\r
2099#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register\r
2100#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register\r
2101#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register\r
2102#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
2103#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register\r
2104\r
2105// *****************************************************************************\r
2106// PIO DEFINITIONS FOR AT91SAM7S512\r
2107// *****************************************************************************\r
2108#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0\r
2109#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0\r
2110#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A\r
2111#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1\r
2112#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1\r
2113#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B\r
2114#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2\r
2115#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2\r
2116#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock\r
2117#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3\r
2118#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data\r
2119#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3\r
2120#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4\r
2121#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock\r
2122#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input\r
2123#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5\r
2124#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data\r
2125#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3\r
2126#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6\r
2127#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data\r
2128#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0\r
2129#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7\r
2130#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send\r
2131#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3\r
2132#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8\r
2133#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send\r
2134#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger\r
2135#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9\r
2136#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data\r
2137#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1\r
2138#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10\r
2139#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data\r
2140#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2\r
2141#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11\r
2142#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0\r
2143#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0\r
2144#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12\r
2145#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave\r
2146#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1\r
2147#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13\r
2148#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave\r
2149#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2\r
2150#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14\r
2151#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock\r
2152#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3\r
2153#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15\r
2154#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync\r
2155#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A\r
2156#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16\r
2157#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock\r
2158#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B\r
2159#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17\r
2160#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data\r
2161#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1\r
2162#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18\r
2163#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data\r
2164#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2\r
2165#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19\r
2166#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock\r
2167#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input\r
2168#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20\r
2169#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync\r
2170#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0\r
2171#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21\r
2172#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data\r
2173#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1\r
2174#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22\r
2175#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data\r
2176#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3\r
2177#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23\r
2178#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock\r
2179#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0\r
2180#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24\r
2181#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send\r
2182#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1\r
2183#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25\r
2184#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send\r
2185#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2\r
2186#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26\r
2187#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect\r
2188#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A\r
2189#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27\r
2190#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready\r
2191#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B\r
2192#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28\r
2193#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready\r
2194#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input\r
2195#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29\r
2196#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator\r
2197#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input\r
2198#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30\r
2199#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1\r
2200#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2\r
2201#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31\r
2202#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1\r
2203#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2\r
2204\r
2205// *****************************************************************************\r
2206// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S512\r
2207// *****************************************************************************\r
2208#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)\r
2209#define AT91C_ID_SYS ( 1) // System Peripheral\r
2210#define AT91C_ID_PIOA ( 2) // Parallel IO Controller\r
2211#define AT91C_ID_3_Reserved ( 3) // Reserved\r
2212#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter\r
2213#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface\r
2214#define AT91C_ID_US0 ( 6) // USART 0\r
2215#define AT91C_ID_US1 ( 7) // USART 1\r
2216#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller\r
2217#define AT91C_ID_TWI ( 9) // Two-Wire Interface\r
2218#define AT91C_ID_PWMC (10) // PWM Controller\r
2219#define AT91C_ID_UDP (11) // USB Device Port\r
2220#define AT91C_ID_TC0 (12) // Timer Counter 0\r
2221#define AT91C_ID_TC1 (13) // Timer Counter 1\r
2222#define AT91C_ID_TC2 (14) // Timer Counter 2\r
2223#define AT91C_ID_15_Reserved (15) // Reserved\r
2224#define AT91C_ID_16_Reserved (16) // Reserved\r
2225#define AT91C_ID_17_Reserved (17) // Reserved\r
2226#define AT91C_ID_18_Reserved (18) // Reserved\r
2227#define AT91C_ID_19_Reserved (19) // Reserved\r
2228#define AT91C_ID_20_Reserved (20) // Reserved\r
2229#define AT91C_ID_21_Reserved (21) // Reserved\r
2230#define AT91C_ID_22_Reserved (22) // Reserved\r
2231#define AT91C_ID_23_Reserved (23) // Reserved\r
2232#define AT91C_ID_24_Reserved (24) // Reserved\r
2233#define AT91C_ID_25_Reserved (25) // Reserved\r
2234#define AT91C_ID_26_Reserved (26) // Reserved\r
2235#define AT91C_ID_27_Reserved (27) // Reserved\r
2236#define AT91C_ID_28_Reserved (28) // Reserved\r
2237#define AT91C_ID_29_Reserved (29) // Reserved\r
2238#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)\r
2239#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)\r
2240#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS\r
2241\r
2242// *****************************************************************************\r
2243// BASE ADDRESS DEFINITIONS FOR AT91SAM7S512\r
2244// *****************************************************************************\r
2245#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address\r
2246#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address\r
2247#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address\r
2248#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address\r
2249#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address\r
2250#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address\r
2251#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address\r
2252#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address\r
2253#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address\r
2254#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address\r
2255#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address\r
2256#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address\r
2257#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address\r
2258#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address\r
2259#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address\r
2260#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address\r
2261#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address\r
2262#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address\r
2263#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address\r
2264#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address\r
2265#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address\r
2266#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address\r
2267#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address\r
2268#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address\r
2269#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address\r
2270#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address\r
2271#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address\r
2272#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
2273#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
2274#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
2275#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address\r
2276#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address\r
2277#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address\r
2278#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address\r
2279#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
2280#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
2281\r
2282// *****************************************************************************\r
2283// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S512\r
2284// *****************************************************************************\r
2285// ISRAM\r
2286#define AT91C_ISRAM (0x00200000) // Internal SRAM base address\r
2287#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes)\r
2288// IFLASH\r
2289#define AT91C_IFLASH (0x00100000) // Internal FLASH base address\r
2290#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes)\r
2291#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes\r
2292#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes\r
2293#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes\r
2294#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes\r
2295\r
2296#endif\r
Proxmark3 GIT tracking
Impressum, Datenschutz