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1 | //----------------------------------------------------------------------------- | |
2 | // (c) 2009 Henryk Plötz <henryk@ploetzli.ch> | |
3 | // 2016 Iceman | |
4 | // | |
5 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, | |
6 | // at your option, any later version. See the LICENSE.txt file for the text of | |
7 | // the license. | |
8 | //----------------------------------------------------------------------------- | |
9 | // LEGIC RF simulation code | |
10 | //----------------------------------------------------------------------------- | |
11 | #include "legicrf.h" | |
12 | ||
13 | static struct legic_frame { | |
14 | uint8_t bits; | |
15 | uint32_t data; | |
16 | } current_frame; | |
17 | ||
18 | static enum { | |
19 | STATE_DISCON, | |
20 | STATE_IV, | |
21 | STATE_CON, | |
22 | } legic_state; | |
23 | ||
24 | static crc_t legic_crc; | |
25 | static int legic_read_count; | |
26 | static uint32_t legic_prng_bc; | |
27 | static uint32_t legic_prng_iv; | |
28 | ||
29 | static int legic_phase_drift; | |
30 | static int legic_frame_drift; | |
31 | static int legic_reqresp_drift; | |
32 | ||
33 | AT91PS_TC timer; | |
34 | AT91PS_TC prng_timer; | |
35 | ||
36 | /* | |
37 | static void setup_timer(void) { | |
38 | // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging | |
39 | // this it won't be terribly accurate but should be good enough. | |
40 | // | |
41 | AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1); | |
42 | timer = AT91C_BASE_TC1; | |
43 | timer->TC_CCR = AT91C_TC_CLKDIS; | |
44 | timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK; | |
45 | timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
46 | ||
47 | // | |
48 | // Set up Timer 2 to use for measuring time between frames in | |
49 | // tag simulation mode. Runs 4x faster as Timer 1 | |
50 | // | |
51 | AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2); | |
52 | prng_timer = AT91C_BASE_TC2; | |
53 | prng_timer->TC_CCR = AT91C_TC_CLKDIS; | |
54 | prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK; | |
55 | prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; | |
56 | } | |
57 | ||
58 | AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14); | |
59 | AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE; | |
60 | ||
61 | // fast clock | |
62 | AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable | |
63 | AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks | |
64 | AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR | | |
65 | AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET; | |
66 | AT91C_BASE_TC0->TC_RA = 1; | |
67 | AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000 | |
68 | ||
69 | */ | |
70 | ||
71 | // At TIMER_CLOCK3 (MCK/32) | |
72 | // testing calculating in (us) microseconds. | |
73 | #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks | |
74 | #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks | |
75 | #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */ | |
76 | #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks | |
77 | #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495 | |
78 | ||
79 | #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit | |
80 | ||
81 | #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */ | |
82 | #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */ | |
83 | ||
84 | #define OFFSET_LOG 1024 | |
85 | ||
86 | #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz))) | |
87 | ||
88 | #ifndef SHORT_COIL | |
89 | # define SHORT_COIL LOW(GPIO_SSC_DOUT); | |
90 | #endif | |
91 | #ifndef OPEN_COIL | |
92 | # define OPEN_COIL HIGH(GPIO_SSC_DOUT); | |
93 | #endif | |
94 | #ifndef LINE_IN | |
95 | # define LINE_IN \ | |
96 | do { \ | |
97 | AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN; \ | |
98 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN; \ | |
99 | } while (0); | |
100 | #endif | |
101 | // Pause pulse, off in 20us / 30ticks, | |
102 | // ONE / ZERO bit pulse, | |
103 | // one == 80us / 120ticks | |
104 | // zero == 40us / 60ticks | |
105 | #ifndef COIL_PULSE | |
106 | # define COIL_PULSE(x) \ | |
107 | do { \ | |
108 | SHORT_COIL; \ | |
109 | WaitTicks( (RWD_TIME_PAUSE) ); \ | |
110 | OPEN_COIL; \ | |
111 | WaitTicks((x)); \ | |
112 | } while (0); | |
113 | #endif | |
114 | ||
115 | // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces. | |
116 | // Historically it used to be FREE_BUFFER_SIZE, which was 2744. | |
117 | #define LEGIC_CARD_MEMSIZE 1024 | |
118 | static uint8_t* cardmem; | |
119 | ||
120 | static void frame_append_bit(struct legic_frame * const f, uint8_t bit) { | |
121 | // Overflow, won't happen | |
122 | if (f->bits >= 31) return; | |
123 | ||
124 | f->data |= (bit << f->bits); | |
125 | f->bits++; | |
126 | } | |
127 | ||
128 | static void frame_clean(struct legic_frame * const f) { | |
129 | f->data = 0; | |
130 | f->bits = 0; | |
131 | } | |
132 | ||
133 | // Prng works when waiting in 99.1us cycles. | |
134 | // and while sending/receiving in bit frames (100, 60) | |
135 | /*static void CalibratePrng( uint32_t time){ | |
136 | // Calculate Cycles based on timer 100us | |
137 | uint32_t i = (time - sendFrameStop) / 100 ; | |
138 | ||
139 | // substract cycles of finished frames | |
140 | int k = i - legic_prng_count()+1; | |
141 | ||
142 | // substract current frame length, rewind to beginning | |
143 | if ( k > 0 ) | |
144 | legic_prng_forward(k); | |
145 | } | |
146 | */ | |
147 | ||
148 | /* Generate Keystream */ | |
149 | uint32_t get_key_stream(int skip, int count) { | |
150 | ||
151 | int i; | |
152 | ||
153 | // Use int to enlarge timer tc to 32bit | |
154 | legic_prng_bc += prng_timer->TC_CV; | |
155 | ||
156 | // reset the prng timer. | |
157 | ||
158 | /* If skip == -1, forward prng time based */ | |
159 | if(skip == -1) { | |
160 | i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */ | |
161 | i -= legic_prng_count(); /* substract cycles of finished frames */ | |
162 | i -= count; /* substract current frame length, rewind to beginning */ | |
163 | legic_prng_forward(i); | |
164 | } else { | |
165 | legic_prng_forward(skip); | |
166 | } | |
167 | ||
168 | i = (count == 6) ? -1 : legic_read_count; | |
169 | ||
170 | /* Generate KeyStream */ | |
171 | return legic_prng_get_bits(count); | |
172 | } | |
173 | ||
174 | /* Send a frame in tag mode, the FPGA must have been set up by | |
175 | * LegicRfSimulate | |
176 | */ | |
177 | void frame_send_tag(uint16_t response, uint8_t bits) { | |
178 | ||
179 | uint16_t mask = 1; | |
180 | ||
181 | /* Bitbang the response */ | |
182 | SHORT_COIL; | |
183 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
184 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
185 | ||
186 | /* TAG_FRAME_WAIT -> shift by 2 */ | |
187 | legic_prng_forward(2); | |
188 | response ^= legic_prng_get_bits(bits); | |
189 | ||
190 | /* Wait for the frame start */ | |
191 | WaitTicks( TAG_FRAME_WAIT ); | |
192 | ||
193 | for (; mask < BITMASK(bits); mask <<= 1) { | |
194 | if (response & mask) | |
195 | OPEN_COIL | |
196 | else | |
197 | SHORT_COIL | |
198 | WaitTicks(TAG_BIT_PERIOD); | |
199 | } | |
200 | SHORT_COIL; | |
201 | } | |
202 | ||
203 | /* Send a frame in reader mode, the FPGA must have been set up by | |
204 | * LegicRfReader | |
205 | */ | |
206 | void frame_sendAsReader(uint32_t data, uint8_t bits){ | |
207 | ||
208 | uint32_t starttime = GET_TICKS, send = 0; | |
209 | uint16_t mask = 1; | |
210 | ||
211 | // xor lsfr onto data. | |
212 | send = data ^ legic_prng_get_bits(bits); | |
213 | ||
214 | for (; mask < BITMASK(bits); mask <<= 1) { | |
215 | if (send & mask) | |
216 | COIL_PULSE(RWD_TIME_1) | |
217 | else | |
218 | COIL_PULSE(RWD_TIME_0) | |
219 | } | |
220 | ||
221 | // Final pause to mark the end of the frame | |
222 | COIL_PULSE(0); | |
223 | ||
224 | // log | |
225 | uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1), BYTEx(send, 0), BYTEx(send, 1)}; | |
226 | LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE); | |
227 | } | |
228 | ||
229 | /* Receive a frame from the card in reader emulation mode, the FPGA and | |
230 | * timer must have been set up by LegicRfReader and frame_sendAsReader. | |
231 | * | |
232 | * The LEGIC RF protocol from card to reader does not include explicit | |
233 | * frame start/stop information or length information. The reader must | |
234 | * know beforehand how many bits it wants to receive. (Notably: a card | |
235 | * sending a stream of 0-bits is indistinguishable from no card present.) | |
236 | * | |
237 | * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but | |
238 | * I'm not smart enough to use it. Instead I have patched hi_read_tx to output | |
239 | * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look | |
240 | * for edges. Count the edges in each bit interval. If they are approximately | |
241 | * 0 this was a 0-bit, if they are approximately equal to the number of edges | |
242 | * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the | |
243 | * timer that's still running from frame_sendAsReader in order to get a synchronization | |
244 | * with the frame that we just sent. | |
245 | * | |
246 | * FIXME: Because we're relying on the hysteresis to just do the right thing | |
247 | * the range is severely reduced (and you'll probably also need a good antenna). | |
248 | * So this should be fixed some time in the future for a proper receiver. | |
249 | */ | |
250 | static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) { | |
251 | ||
252 | if ( bits > 32 ) return; | |
253 | ||
254 | uint8_t i = bits, edges = 0; | |
255 | uint32_t the_bit = 1, next_bit_at = 0, data = 0; | |
256 | uint32_t old_level = 0; | |
257 | volatile uint32_t level = 0; | |
258 | ||
259 | frame_clean(f); | |
260 | ||
261 | /* Bitbang the receiver */ | |
262 | LINE_IN; | |
263 | ||
264 | // calibrate the prng. | |
265 | legic_prng_forward(2); | |
266 | data = legic_prng_get_bits(bits); | |
267 | ||
268 | //FIXED time between sending frame and now listening frame. 330us | |
269 | uint32_t starttime = GET_TICKS; | |
270 | // its about 9+9 ticks delay from end-send to here. | |
271 | WaitTicks( 477 ); | |
272 | ||
273 | next_bit_at = GET_TICKS + TAG_BIT_PERIOD; | |
274 | ||
275 | while ( i-- ){ | |
276 | edges = 0; | |
277 | while ( GET_TICKS < next_bit_at) { | |
278 | ||
279 | level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); | |
280 | ||
281 | if (level != old_level) | |
282 | ++edges; | |
283 | ||
284 | old_level = level; | |
285 | } | |
286 | ||
287 | next_bit_at += TAG_BIT_PERIOD; | |
288 | ||
289 | // We expect 42 edges (ONE) | |
290 | if ( edges > 20 ) | |
291 | data ^= the_bit; | |
292 | ||
293 | the_bit <<= 1; | |
294 | } | |
295 | ||
296 | // output | |
297 | f->data = data; | |
298 | f->bits = bits; | |
299 | ||
300 | // log | |
301 | uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)}; | |
302 | LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE); | |
303 | } | |
304 | ||
305 | // Setup pm3 as a Legic Reader | |
306 | static uint32_t setup_phase_reader(uint8_t iv) { | |
307 | ||
308 | // Switch on carrier and let the tag charge for 1ms | |
309 | HIGH(GPIO_SSC_DOUT); | |
310 | WaitUS(5000); | |
311 | ||
312 | ResetTicks(); | |
313 | ||
314 | // no keystream yet | |
315 | legic_prng_init(0); | |
316 | ||
317 | // send IV handshake | |
318 | frame_sendAsReader(iv, 7); | |
319 | ||
320 | // Now both tag and reader has same IV. Prng can start. | |
321 | legic_prng_init(iv); | |
322 | ||
323 | frame_receiveAsReader(¤t_frame, 6); | |
324 | ||
325 | // 292us (438t) - fixed delay before sending ack. | |
326 | // minus log and stuff 100tick? | |
327 | WaitTicks(338); | |
328 | legic_prng_forward(3); | |
329 | ||
330 | // Send obsfuscated acknowledgment frame. | |
331 | // 0x19 = 0x18 MIM22, 0x01 LSB READCMD | |
332 | // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD | |
333 | switch ( current_frame.data ) { | |
334 | case 0x0D: frame_sendAsReader(0x19, 6); break; | |
335 | case 0x1D: | |
336 | case 0x3D: frame_sendAsReader(0x39, 6); break; | |
337 | default: break; | |
338 | } | |
339 | ||
340 | legic_prng_forward(2); | |
341 | return current_frame.data; | |
342 | } | |
343 | ||
344 | static void LegicCommonInit(void) { | |
345 | ||
346 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); | |
347 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX); | |
348 | SetAdcMuxFor(GPIO_MUXSEL_HIPKD); | |
349 | ||
350 | /* Bitbang the transmitter */ | |
351 | LOW(GPIO_SSC_DOUT); | |
352 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; | |
353 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; | |
354 | ||
355 | // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier. | |
356 | cardmem = BigBuf_get_EM_addr(); | |
357 | memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE); | |
358 | ||
359 | clear_trace(); | |
360 | set_tracing(TRUE); | |
361 | crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); | |
362 | ||
363 | StartTicks(); | |
364 | } | |
365 | ||
366 | // Switch off carrier, make sure tag is reset | |
367 | static void switch_off_tag_rwd(void) { | |
368 | LOW(GPIO_SSC_DOUT); | |
369 | WaitUS(20); | |
370 | WDT_HIT(); | |
371 | } | |
372 | ||
373 | // calculate crc4 for a legic READ command | |
374 | static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) { | |
375 | crc_clear(&legic_crc); | |
376 | uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd; | |
377 | crc_update(&legic_crc, temp, cmd_sz + 8 ); | |
378 | return crc_finish(&legic_crc); | |
379 | } | |
380 | ||
381 | int legic_read_byte( uint16_t index, uint8_t cmd_sz) { | |
382 | ||
383 | uint8_t byte, crc, calcCrc = 0; | |
384 | uint32_t cmd = (index << 1) | LEGIC_READ; | |
385 | ||
386 | // 90ticks = 60us (should be 100us but crc calc takes time.) | |
387 | //WaitTicks(330); // 330ticks prng(4) - works | |
388 | WaitTicks(240); // 240ticks prng(3) - works | |
389 | ||
390 | frame_sendAsReader(cmd, cmd_sz); | |
391 | frame_receiveAsReader(¤t_frame, 12); | |
392 | ||
393 | // CRC check. | |
394 | byte = BYTEx(current_frame.data, 0); | |
395 | crc = BYTEx(current_frame.data, 1); | |
396 | calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz); | |
397 | ||
398 | if( calcCrc != crc ) { | |
399 | Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc); | |
400 | return -1; | |
401 | } | |
402 | ||
403 | legic_prng_forward(3); | |
404 | return byte; | |
405 | } | |
406 | ||
407 | /* | |
408 | * - assemble a write_cmd_frame with crc and send it | |
409 | * - wait until the tag sends back an ACK ('1' bit unencrypted) | |
410 | * - forward the prng based on the timing | |
411 | */ | |
412 | int legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) { | |
413 | ||
414 | // crc | |
415 | crc_clear(&legic_crc); | |
416 | crc_update(&legic_crc, 0, 1); /* CMD_WRITE */ | |
417 | crc_update(&legic_crc, index, addr_sz); | |
418 | crc_update(&legic_crc, byte, 8); | |
419 | uint32_t crc = crc_finish(&legic_crc); | |
420 | uint32_t crc2 = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1); | |
421 | if ( crc != crc2 ) { | |
422 | Dbprintf("crc is missmatch"); | |
423 | return 1; | |
424 | } | |
425 | // send write command | |
426 | uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC | |
427 | |(byte <<(addr_sz+1)) //Data | |
428 | |(index <<1) //index | |
429 | | LEGIC_WRITE); //CMD = Write | |
430 | ||
431 | uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd | |
432 | ||
433 | legic_prng_forward(2); | |
434 | ||
435 | WaitTicks(330); | |
436 | ||
437 | frame_sendAsReader(cmd, cmd_sz); | |
438 | ||
439 | /* Bitbang the receiver */ | |
440 | LINE_IN; | |
441 | ||
442 | int t, old_level = 0, edges = 0; | |
443 | int next_bit_at = 0; | |
444 | ||
445 | // ACK 3.6ms = 3600us * 1.5 = 5400ticks. | |
446 | WaitTicks(5360); | |
447 | ||
448 | for( t = 0; t < 80; ++t) { | |
449 | edges = 0; | |
450 | next_bit_at += TAG_BIT_PERIOD; | |
451 | while(timer->TC_CV < next_bit_at) { | |
452 | volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); | |
453 | if(level != old_level) | |
454 | edges++; | |
455 | ||
456 | old_level = level; | |
457 | } | |
458 | /* expected are 42 edges (ONE) */ | |
459 | if(edges > 20 ) { | |
460 | int t = timer->TC_CV; | |
461 | int c = t / TAG_BIT_PERIOD; | |
462 | ||
463 | ResetTimer(timer); | |
464 | legic_prng_forward(c); | |
465 | return 0; | |
466 | } | |
467 | } | |
468 | ||
469 | return -1; | |
470 | } | |
471 | ||
472 | int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) { | |
473 | ||
474 | uint16_t i = 0; | |
475 | uint8_t isOK = 1; | |
476 | legic_card_select_t card; | |
477 | ||
478 | LegicCommonInit(); | |
479 | ||
480 | if ( legic_select_card_iv(&card, iv) ) { | |
481 | isOK = 0; | |
482 | goto OUT; | |
483 | } | |
484 | ||
485 | switch_off_tag_rwd(); | |
486 | ||
487 | if (len + offset >= card.cardsize) | |
488 | len = card.cardsize - offset; | |
489 | ||
490 | setup_phase_reader(iv); | |
491 | ||
492 | LED_B_ON(); | |
493 | while (i < len) { | |
494 | int r = legic_read_byte(offset + i, card.cmdsize); | |
495 | ||
496 | if (r == -1 || BUTTON_PRESS()) { | |
497 | if ( MF_DBGLEVEL >= 2) DbpString("operation aborted"); | |
498 | isOK = 0; | |
499 | goto OUT; | |
500 | } | |
501 | cardmem[i++] = r; | |
502 | WDT_HIT(); | |
503 | } | |
504 | ||
505 | OUT: | |
506 | WDT_HIT(); | |
507 | switch_off_tag_rwd(); | |
508 | LEDsoff(); | |
509 | cmd_send(CMD_ACK, isOK, len, 0, cardmem, len); | |
510 | return 0; | |
511 | } | |
512 | ||
513 | void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) { | |
514 | ||
515 | uint8_t isOK = 1; | |
516 | ||
517 | // UID not is writeable. | |
518 | if ( offset <= 4 ) { | |
519 | isOK = 0; | |
520 | goto OUT; | |
521 | } | |
522 | ||
523 | legic_card_select_t card; | |
524 | ||
525 | LegicCommonInit(); | |
526 | ||
527 | if ( legic_select_card_iv(&card, iv) ) { | |
528 | isOK = 0; | |
529 | goto OUT; | |
530 | } | |
531 | ||
532 | if (len + offset >= card.cardsize) | |
533 | len = card.cardsize - offset; | |
534 | ||
535 | setup_phase_reader(iv); | |
536 | ||
537 | LED_B_ON(); | |
538 | int r = 0; | |
539 | // how about we write backwards instead. no need for this extra DCF check. | |
540 | // index = len - cardsize | |
541 | // stops uid 01234, | |
542 | /* | |
543 | len = 20 | |
544 | offset = 5 | |
545 | ||
546 | index = 20+5 = 25 | |
547 | if ( index > cardsize ) return -1; | |
548 | ||
549 | loop | |
550 | write( data[index], index , card.addrsize); | |
551 | --index; | |
552 | end loop | |
553 | */ | |
554 | uint16_t index = len; | |
555 | while(index > 4) { | |
556 | ||
557 | r = legic_write_byte( index, data[ index ], card.addrsize); | |
558 | ||
559 | if ( r ) { | |
560 | Dbprintf("operation aborted @ 0x%03.3x", index); | |
561 | isOK = 0; | |
562 | goto OUT; | |
563 | } | |
564 | --index; | |
565 | WDT_HIT(); | |
566 | } | |
567 | ||
568 | OUT: | |
569 | cmd_send(CMD_ACK, isOK, 0,0,0,0); | |
570 | switch_off_tag_rwd(); | |
571 | LEDsoff(); | |
572 | } | |
573 | ||
574 | int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){ | |
575 | ||
576 | if ( p_card == NULL ) return 1; | |
577 | ||
578 | p_card->tagtype = setup_phase_reader(iv); | |
579 | ||
580 | switch(p_card->tagtype) { | |
581 | case 0x0d: | |
582 | p_card->cmdsize = 6; | |
583 | p_card->addrsize = 5; | |
584 | p_card->cardsize = 22; | |
585 | break; | |
586 | case 0x1d: | |
587 | p_card->cmdsize = 9; | |
588 | p_card->addrsize = 8; | |
589 | p_card->cardsize = 256; | |
590 | break; | |
591 | case 0x3d: | |
592 | p_card->cmdsize = 11; | |
593 | p_card->addrsize = 10; | |
594 | p_card->cardsize = 1024; | |
595 | break; | |
596 | default: | |
597 | p_card->cmdsize = 0; | |
598 | p_card->addrsize = 0; | |
599 | p_card->cardsize = 0; | |
600 | return 2; | |
601 | } | |
602 | return 0; | |
603 | } | |
604 | int legic_select_card(legic_card_select_t *p_card){ | |
605 | return legic_select_card_iv(p_card, 0x01); | |
606 | } | |
607 | ||
608 | //----------------------------------------------------------------------------- | |
609 | // Work with emulator memory | |
610 | // | |
611 | // Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not | |
612 | // involved in dealing with emulator memory. But if it is called later, it might | |
613 | // destroy the Emulator Memory. | |
614 | //----------------------------------------------------------------------------- | |
615 | // arg0 = offset | |
616 | // arg1 = num of bytes | |
617 | void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) { | |
618 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); | |
619 | legic_emlset_mem(data, arg0, arg1); | |
620 | } | |
621 | // arg0 = offset | |
622 | // arg1 = num of bytes | |
623 | void LegicEMemGet(uint32_t arg0, uint32_t arg1) { | |
624 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); | |
625 | uint8_t buf[USB_CMD_DATA_SIZE] = {0x00}; | |
626 | legic_emlget_mem(buf, arg0, arg1); | |
627 | LED_B_ON(); | |
628 | cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE); | |
629 | LED_B_OFF(); | |
630 | } | |
631 | void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) { | |
632 | cardmem = BigBuf_get_EM_addr(); | |
633 | memcpy(cardmem + offset, data, numofbytes); | |
634 | } | |
635 | void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) { | |
636 | cardmem = BigBuf_get_EM_addr(); | |
637 | memcpy(data, cardmem + offset, numofbytes); | |
638 | } | |
639 | ||
640 | void LegicRfInfo(void){ | |
641 | ||
642 | int r; | |
643 | ||
644 | uint8_t buf[sizeof(legic_card_select_t)] = {0x00}; | |
645 | legic_card_select_t *card = (legic_card_select_t*) buf; | |
646 | ||
647 | LegicCommonInit(); | |
648 | ||
649 | if ( legic_select_card(card) ) { | |
650 | cmd_send(CMD_ACK,0,0,0,0,0); | |
651 | goto OUT; | |
652 | } | |
653 | ||
654 | // read UID bytes | |
655 | for ( uint8_t i = 0; i < sizeof(card->uid); ++i) { | |
656 | r = legic_read_byte(i, card->cmdsize); | |
657 | if ( r == -1 ) { | |
658 | cmd_send(CMD_ACK,0,0,0,0,0); | |
659 | goto OUT; | |
660 | } | |
661 | card->uid[i] = r & 0xFF; | |
662 | } | |
663 | ||
664 | // MCC byte. | |
665 | r = legic_read_byte(4, card->cmdsize); | |
666 | uint32_t calc_mcc = CRC8Legic(card->uid, 4);; | |
667 | if ( r != calc_mcc) { | |
668 | cmd_send(CMD_ACK,0,0,0,0,0); | |
669 | goto OUT; | |
670 | } | |
671 | ||
672 | // OK | |
673 | cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t)); | |
674 | ||
675 | OUT: | |
676 | switch_off_tag_rwd(); | |
677 | LEDsoff(); | |
678 | } | |
679 | ||
680 | /* Handle (whether to respond) a frame in tag mode | |
681 | * Only called when simulating a tag. | |
682 | */ | |
683 | static void frame_handle_tag(struct legic_frame const * const f) | |
684 | { | |
685 | // log | |
686 | //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)}; | |
687 | //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE); | |
688 | ||
689 | cardmem = BigBuf_get_EM_addr(); | |
690 | ||
691 | /* First Part of Handshake (IV) */ | |
692 | if(f->bits == 7) { | |
693 | ||
694 | LED_C_ON(); | |
695 | ||
696 | // Reset prng timer | |
697 | ResetTimer(prng_timer); | |
698 | ||
699 | // IV from reader. | |
700 | legic_prng_init(f->data); | |
701 | ||
702 | // We should have three tagtypes with three different answers. | |
703 | frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */ | |
704 | ||
705 | legic_state = STATE_IV; | |
706 | legic_read_count = 0; | |
707 | legic_prng_bc = 0; | |
708 | legic_prng_iv = f->data; | |
709 | ||
710 | ||
711 | ResetTimer(timer); | |
712 | WaitUS(280); | |
713 | return; | |
714 | } | |
715 | ||
716 | /* 0x19==??? */ | |
717 | if(legic_state == STATE_IV) { | |
718 | uint32_t local_key = get_key_stream(3, 6); | |
719 | int xored = 0x39 ^ local_key; | |
720 | if((f->bits == 6) && (f->data == xored)) { | |
721 | legic_state = STATE_CON; | |
722 | ||
723 | ResetTimer(timer); | |
724 | WaitUS(200); | |
725 | return; | |
726 | ||
727 | } else { | |
728 | legic_state = STATE_DISCON; | |
729 | LED_C_OFF(); | |
730 | Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored); | |
731 | return; | |
732 | } | |
733 | } | |
734 | ||
735 | /* Read */ | |
736 | if(f->bits == 11) { | |
737 | if(legic_state == STATE_CON) { | |
738 | uint32_t key = get_key_stream(2, 11); //legic_phase_drift, 11); | |
739 | uint16_t addr = f->data ^ key; | |
740 | addr >>= 1; | |
741 | uint8_t data = cardmem[addr]; | |
742 | int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8; | |
743 | ||
744 | legic_read_count++; | |
745 | legic_prng_forward(legic_reqresp_drift); | |
746 | ||
747 | frame_send_tag(hash | data, 12); | |
748 | ResetTimer(timer); | |
749 | legic_prng_forward(2); | |
750 | WaitTicks(330); | |
751 | return; | |
752 | } | |
753 | } | |
754 | ||
755 | /* Write */ | |
756 | if(f->bits == 23) { | |
757 | uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23); | |
758 | uint16_t addr = f->data ^ key; | |
759 | addr >>= 1; | |
760 | addr &= 0x3ff; | |
761 | uint32_t data = f->data ^ key; | |
762 | data >>= 11; | |
763 | data &= 0xff; | |
764 | ||
765 | cardmem[addr] = data; | |
766 | /* write command */ | |
767 | legic_state = STATE_DISCON; | |
768 | LED_C_OFF(); | |
769 | Dbprintf("write - addr: %x, data: %x", addr, data); | |
770 | // should send a ACK within 3.5ms too | |
771 | return; | |
772 | } | |
773 | ||
774 | if(legic_state != STATE_DISCON) { | |
775 | Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count); | |
776 | Dbprintf("IV: %03.3x", legic_prng_iv); | |
777 | } | |
778 | ||
779 | legic_state = STATE_DISCON; | |
780 | legic_read_count = 0; | |
781 | SpinDelay(10); | |
782 | LED_C_OFF(); | |
783 | return; | |
784 | } | |
785 | ||
786 | /* Read bit by bit untill full frame is received | |
787 | * Call to process frame end answer | |
788 | */ | |
789 | static void emit(int bit) { | |
790 | ||
791 | switch (bit) { | |
792 | case 1: | |
793 | frame_append_bit(¤t_frame, 1); | |
794 | break; | |
795 | case 0: | |
796 | frame_append_bit(¤t_frame, 0); | |
797 | break; | |
798 | default: | |
799 | if(current_frame.bits <= 4) { | |
800 | frame_clean(¤t_frame); | |
801 | } else { | |
802 | frame_handle_tag(¤t_frame); | |
803 | frame_clean(¤t_frame); | |
804 | } | |
805 | WDT_HIT(); | |
806 | break; | |
807 | } | |
808 | } | |
809 | ||
810 | void LegicRfSimulate(int phase, int frame, int reqresp) | |
811 | { | |
812 | /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode, | |
813 | * modulation mode set to 212kHz subcarrier. We are getting the incoming raw | |
814 | * envelope waveform on DIN and should send our response on DOUT. | |
815 | * | |
816 | * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll | |
817 | * measure the time between two rising edges on DIN, and no encoding on the | |
818 | * subcarrier from card to reader, so we'll just shift out our verbatim data | |
819 | * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear, | |
820 | * seems to be 300us-ish. | |
821 | */ | |
822 | ||
823 | int old_level = 0, active = 0; | |
824 | legic_state = STATE_DISCON; | |
825 | ||
826 | legic_phase_drift = phase; | |
827 | legic_frame_drift = frame; | |
828 | legic_reqresp_drift = reqresp; | |
829 | ||
830 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); | |
831 | SetAdcMuxFor(GPIO_MUXSEL_HIPKD); | |
832 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K); | |
833 | ||
834 | /* Bitbang the receiver */ | |
835 | LINE_IN; | |
836 | ||
837 | // need a way to determine which tagtype we are simulating | |
838 | ||
839 | // hook up emulator memory | |
840 | cardmem = BigBuf_get_EM_addr(); | |
841 | ||
842 | clear_trace(); | |
843 | set_tracing(TRUE); | |
844 | ||
845 | crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); | |
846 | ||
847 | StartTicks(); | |
848 | ||
849 | LED_B_ON(); | |
850 | DbpString("Starting Legic emulator, press button to end"); | |
851 | ||
852 | while(!BUTTON_PRESS() && !usb_poll_validate_length()) { | |
853 | volatile uint32_t level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN); | |
854 | ||
855 | uint32_t time = GET_TICKS; | |
856 | ||
857 | if (level != old_level) { | |
858 | ||
859 | if (level) { | |
860 | ||
861 | ResetTicks(); | |
862 | ||
863 | if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) { | |
864 | /* 1 bit */ | |
865 | emit(1); | |
866 | active = 1; | |
867 | LED_A_ON(); | |
868 | } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) { | |
869 | /* 0 bit */ | |
870 | emit(0); | |
871 | active = 1; | |
872 | LED_A_ON(); | |
873 | } else if (active) { | |
874 | /* invalid */ | |
875 | emit(-1); | |
876 | active = 0; | |
877 | LED_A_OFF(); | |
878 | } | |
879 | } | |
880 | } | |
881 | ||
882 | /* Frame end */ | |
883 | if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) { | |
884 | emit(-1); | |
885 | active = 0; | |
886 | LED_A_OFF(); | |
887 | } | |
888 | ||
889 | /* | |
890 | * Disable the counter, Then wait for the clock to acknowledge the | |
891 | * shutdown in its status register. Reading the SR has the | |
892 | * side-effect of clearing any pending state in there. | |
893 | */ | |
894 | if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) | |
895 | StopTicks(); | |
896 | ||
897 | old_level = level; | |
898 | WDT_HIT(); | |
899 | } | |
900 | ||
901 | WDT_HIT(); | |
902 | switch_off_tag_rwd(); | |
903 | LEDsoff(); | |
904 | cmd_send(CMD_ACK, 1, 0, 0, 0, 0); | |
905 | } | |
906 | ||
907 | //----------------------------------------------------------------------------- | |
908 | // Code up a string of octets at layer 2 (including CRC, we don't generate | |
909 | // that here) so that they can be transmitted to the reader. Doesn't transmit | |
910 | // them yet, just leaves them ready to send in ToSend[]. | |
911 | //----------------------------------------------------------------------------- | |
912 | // static void CodeLegicAsTag(const uint8_t *cmd, int len) | |
913 | // { | |
914 | // int i; | |
915 | ||
916 | // ToSendReset(); | |
917 | ||
918 | // // Transmit a burst of ones, as the initial thing that lets the | |
919 | // // reader get phase sync. This (TR1) must be > 80/fs, per spec, | |
920 | // // but tag that I've tried (a Paypass) exceeds that by a fair bit, | |
921 | // // so I will too. | |
922 | // for(i = 0; i < 20; i++) { | |
923 | // ToSendStuffBit(1); | |
924 | // ToSendStuffBit(1); | |
925 | // ToSendStuffBit(1); | |
926 | // ToSendStuffBit(1); | |
927 | // } | |
928 | ||
929 | // // Send SOF. | |
930 | // for(i = 0; i < 10; i++) { | |
931 | // ToSendStuffBit(0); | |
932 | // ToSendStuffBit(0); | |
933 | // ToSendStuffBit(0); | |
934 | // ToSendStuffBit(0); | |
935 | // } | |
936 | // for(i = 0; i < 2; i++) { | |
937 | // ToSendStuffBit(1); | |
938 | // ToSendStuffBit(1); | |
939 | // ToSendStuffBit(1); | |
940 | // ToSendStuffBit(1); | |
941 | // } | |
942 | ||
943 | // for(i = 0; i < len; i++) { | |
944 | // int j; | |
945 | // uint8_t b = cmd[i]; | |
946 | ||
947 | // // Start bit | |
948 | // ToSendStuffBit(0); | |
949 | // ToSendStuffBit(0); | |
950 | // ToSendStuffBit(0); | |
951 | // ToSendStuffBit(0); | |
952 | ||
953 | // // Data bits | |
954 | // for(j = 0; j < 8; j++) { | |
955 | // if(b & 1) { | |
956 | // ToSendStuffBit(1); | |
957 | // ToSendStuffBit(1); | |
958 | // ToSendStuffBit(1); | |
959 | // ToSendStuffBit(1); | |
960 | // } else { | |
961 | // ToSendStuffBit(0); | |
962 | // ToSendStuffBit(0); | |
963 | // ToSendStuffBit(0); | |
964 | // ToSendStuffBit(0); | |
965 | // } | |
966 | // b >>= 1; | |
967 | // } | |
968 | ||
969 | // // Stop bit | |
970 | // ToSendStuffBit(1); | |
971 | // ToSendStuffBit(1); | |
972 | // ToSendStuffBit(1); | |
973 | // ToSendStuffBit(1); | |
974 | // } | |
975 | ||
976 | // // Send EOF. | |
977 | // for(i = 0; i < 10; i++) { | |
978 | // ToSendStuffBit(0); | |
979 | // ToSendStuffBit(0); | |
980 | // ToSendStuffBit(0); | |
981 | // ToSendStuffBit(0); | |
982 | // } | |
983 | // for(i = 0; i < 2; i++) { | |
984 | // ToSendStuffBit(1); | |
985 | // ToSendStuffBit(1); | |
986 | // ToSendStuffBit(1); | |
987 | // ToSendStuffBit(1); | |
988 | // } | |
989 | ||
990 | // // Convert from last byte pos to length | |
991 | // ToSendMax++; | |
992 | // } | |
993 | ||
994 | //----------------------------------------------------------------------------- | |
995 | // The software UART that receives commands from the reader, and its state | |
996 | // variables. | |
997 | //----------------------------------------------------------------------------- | |
998 | /* | |
999 | static struct { | |
1000 | enum { | |
1001 | STATE_UNSYNCD, | |
1002 | STATE_GOT_FALLING_EDGE_OF_SOF, | |
1003 | STATE_AWAITING_START_BIT, | |
1004 | STATE_RECEIVING_DATA | |
1005 | } state; | |
1006 | uint16_t shiftReg; | |
1007 | int bitCnt; | |
1008 | int byteCnt; | |
1009 | int byteCntMax; | |
1010 | int posCnt; | |
1011 | uint8_t *output; | |
1012 | } Uart; | |
1013 | */ | |
1014 | /* Receive & handle a bit coming from the reader. | |
1015 | * | |
1016 | * This function is called 4 times per bit (every 2 subcarrier cycles). | |
1017 | * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us | |
1018 | * | |
1019 | * LED handling: | |
1020 | * LED A -> ON once we have received the SOF and are expecting the rest. | |
1021 | * LED A -> OFF once we have received EOF or are in error state or unsynced | |
1022 | * | |
1023 | * Returns: true if we received a EOF | |
1024 | * false if we are still waiting for some more | |
1025 | */ | |
1026 | // static RAMFUNC int HandleLegicUartBit(uint8_t bit) | |
1027 | // { | |
1028 | // switch(Uart.state) { | |
1029 | // case STATE_UNSYNCD: | |
1030 | // if(!bit) { | |
1031 | // // we went low, so this could be the beginning of an SOF | |
1032 | // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF; | |
1033 | // Uart.posCnt = 0; | |
1034 | // Uart.bitCnt = 0; | |
1035 | // } | |
1036 | // break; | |
1037 | ||
1038 | // case STATE_GOT_FALLING_EDGE_OF_SOF: | |
1039 | // Uart.posCnt++; | |
1040 | // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit | |
1041 | // if(bit) { | |
1042 | // if(Uart.bitCnt > 9) { | |
1043 | // // we've seen enough consecutive | |
1044 | // // zeros that it's a valid SOF | |
1045 | // Uart.posCnt = 0; | |
1046 | // Uart.byteCnt = 0; | |
1047 | // Uart.state = STATE_AWAITING_START_BIT; | |
1048 | // LED_A_ON(); // Indicate we got a valid SOF | |
1049 | // } else { | |
1050 | // // didn't stay down long enough | |
1051 | // // before going high, error | |
1052 | // Uart.state = STATE_UNSYNCD; | |
1053 | // } | |
1054 | // } else { | |
1055 | // // do nothing, keep waiting | |
1056 | // } | |
1057 | // Uart.bitCnt++; | |
1058 | // } | |
1059 | // if(Uart.posCnt >= 4) Uart.posCnt = 0; | |
1060 | // if(Uart.bitCnt > 12) { | |
1061 | // // Give up if we see too many zeros without | |
1062 | // // a one, too. | |
1063 | // LED_A_OFF(); | |
1064 | // Uart.state = STATE_UNSYNCD; | |
1065 | // } | |
1066 | // break; | |
1067 | ||
1068 | // case STATE_AWAITING_START_BIT: | |
1069 | // Uart.posCnt++; | |
1070 | // if(bit) { | |
1071 | // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs | |
1072 | // // stayed high for too long between | |
1073 | // // characters, error | |
1074 | // Uart.state = STATE_UNSYNCD; | |
1075 | // } | |
1076 | // } else { | |
1077 | // // falling edge, this starts the data byte | |
1078 | // Uart.posCnt = 0; | |
1079 | // Uart.bitCnt = 0; | |
1080 | // Uart.shiftReg = 0; | |
1081 | // Uart.state = STATE_RECEIVING_DATA; | |
1082 | // } | |
1083 | // break; | |
1084 | ||
1085 | // case STATE_RECEIVING_DATA: | |
1086 | // Uart.posCnt++; | |
1087 | // if(Uart.posCnt == 2) { | |
1088 | // // time to sample a bit | |
1089 | // Uart.shiftReg >>= 1; | |
1090 | // if(bit) { | |
1091 | // Uart.shiftReg |= 0x200; | |
1092 | // } | |
1093 | // Uart.bitCnt++; | |
1094 | // } | |
1095 | // if(Uart.posCnt >= 4) { | |
1096 | // Uart.posCnt = 0; | |
1097 | // } | |
1098 | // if(Uart.bitCnt == 10) { | |
1099 | // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001)) | |
1100 | // { | |
1101 | // // this is a data byte, with correct | |
1102 | // // start and stop bits | |
1103 | // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff; | |
1104 | // Uart.byteCnt++; | |
1105 | ||
1106 | // if(Uart.byteCnt >= Uart.byteCntMax) { | |
1107 | // // Buffer overflowed, give up | |
1108 | // LED_A_OFF(); | |
1109 | // Uart.state = STATE_UNSYNCD; | |
1110 | // } else { | |
1111 | // // so get the next byte now | |
1112 | // Uart.posCnt = 0; | |
1113 | // Uart.state = STATE_AWAITING_START_BIT; | |
1114 | // } | |
1115 | // } else if (Uart.shiftReg == 0x000) { | |
1116 | // // this is an EOF byte | |
1117 | // LED_A_OFF(); // Finished receiving | |
1118 | // Uart.state = STATE_UNSYNCD; | |
1119 | // if (Uart.byteCnt != 0) { | |
1120 | // return TRUE; | |
1121 | // } | |
1122 | // } else { | |
1123 | // // this is an error | |
1124 | // LED_A_OFF(); | |
1125 | // Uart.state = STATE_UNSYNCD; | |
1126 | // } | |
1127 | // } | |
1128 | // break; | |
1129 | ||
1130 | // default: | |
1131 | // LED_A_OFF(); | |
1132 | // Uart.state = STATE_UNSYNCD; | |
1133 | // break; | |
1134 | // } | |
1135 | ||
1136 | // return FALSE; | |
1137 | // } | |
1138 | /* | |
1139 | ||
1140 | static void UartReset() { | |
1141 | Uart.byteCntMax = 3; | |
1142 | Uart.state = STATE_UNSYNCD; | |
1143 | Uart.byteCnt = 0; | |
1144 | Uart.bitCnt = 0; | |
1145 | Uart.posCnt = 0; | |
1146 | memset(Uart.output, 0x00, 3); | |
1147 | } | |
1148 | */ | |
1149 | // static void UartInit(uint8_t *data) { | |
1150 | // Uart.output = data; | |
1151 | // UartReset(); | |
1152 | // } | |
1153 | ||
1154 | //============================================================================= | |
1155 | // An LEGIC reader. We take layer two commands, code them | |
1156 | // appropriately, and then send them to the tag. We then listen for the | |
1157 | // tag's response, which we leave in the buffer to be demodulated on the | |
1158 | // PC side. | |
1159 | //============================================================================= | |
1160 | /* | |
1161 | static struct { | |
1162 | enum { | |
1163 | DEMOD_UNSYNCD, | |
1164 | DEMOD_PHASE_REF_TRAINING, | |
1165 | DEMOD_AWAITING_FALLING_EDGE_OF_SOF, | |
1166 | DEMOD_GOT_FALLING_EDGE_OF_SOF, | |
1167 | DEMOD_AWAITING_START_BIT, | |
1168 | DEMOD_RECEIVING_DATA | |
1169 | } state; | |
1170 | int bitCount; | |
1171 | int posCount; | |
1172 | int thisBit; | |
1173 | uint16_t shiftReg; | |
1174 | uint8_t *output; | |
1175 | int len; | |
1176 | int sumI; | |
1177 | int sumQ; | |
1178 | } Demod; | |
1179 | */ | |
1180 | /* | |
1181 | * Handles reception of a bit from the tag | |
1182 | * | |
1183 | * This function is called 2 times per bit (every 4 subcarrier cycles). | |
1184 | * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us | |
1185 | * | |
1186 | * LED handling: | |
1187 | * LED C -> ON once we have received the SOF and are expecting the rest. | |
1188 | * LED C -> OFF once we have received EOF or are unsynced | |
1189 | * | |
1190 | * Returns: true if we received a EOF | |
1191 | * false if we are still waiting for some more | |
1192 | * | |
1193 | */ | |
1194 | ||
1195 | /* | |
1196 | static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq) | |
1197 | { | |
1198 | int v = 0; | |
1199 | int ai = ABS(ci); | |
1200 | int aq = ABS(cq); | |
1201 | int halfci = (ai >> 1); | |
1202 | int halfcq = (aq >> 1); | |
1203 | ||
1204 | switch(Demod.state) { | |
1205 | case DEMOD_UNSYNCD: | |
1206 | ||
1207 | CHECK_FOR_SUBCARRIER() | |
1208 | ||
1209 | if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected | |
1210 | Demod.state = DEMOD_PHASE_REF_TRAINING; | |
1211 | Demod.sumI = ci; | |
1212 | Demod.sumQ = cq; | |
1213 | Demod.posCount = 1; | |
1214 | } | |
1215 | break; | |
1216 | ||
1217 | case DEMOD_PHASE_REF_TRAINING: | |
1218 | if(Demod.posCount < 8) { | |
1219 | ||
1220 | CHECK_FOR_SUBCARRIER() | |
1221 | ||
1222 | if (v > SUBCARRIER_DETECT_THRESHOLD) { | |
1223 | // set the reference phase (will code a logic '1') by averaging over 32 1/fs. | |
1224 | // note: synchronization time > 80 1/fs | |
1225 | Demod.sumI += ci; | |
1226 | Demod.sumQ += cq; | |
1227 | ++Demod.posCount; | |
1228 | } else { | |
1229 | // subcarrier lost | |
1230 | Demod.state = DEMOD_UNSYNCD; | |
1231 | } | |
1232 | } else { | |
1233 | Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF; | |
1234 | } | |
1235 | break; | |
1236 | ||
1237 | case DEMOD_AWAITING_FALLING_EDGE_OF_SOF: | |
1238 | ||
1239 | MAKE_SOFT_DECISION() | |
1240 | ||
1241 | //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq ); | |
1242 | // logic '0' detected | |
1243 | if (v <= 0) { | |
1244 | ||
1245 | Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF; | |
1246 | ||
1247 | // start of SOF sequence | |
1248 | Demod.posCount = 0; | |
1249 | } else { | |
1250 | // maximum length of TR1 = 200 1/fs | |
1251 | if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD; | |
1252 | } | |
1253 | ++Demod.posCount; | |
1254 | break; | |
1255 | ||
1256 | case DEMOD_GOT_FALLING_EDGE_OF_SOF: | |
1257 | ++Demod.posCount; | |
1258 | ||
1259 | MAKE_SOFT_DECISION() | |
1260 | ||
1261 | if(v > 0) { | |
1262 | // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges | |
1263 | if(Demod.posCount < 10*2) { | |
1264 | Demod.state = DEMOD_UNSYNCD; | |
1265 | } else { | |
1266 | LED_C_ON(); // Got SOF | |
1267 | Demod.state = DEMOD_AWAITING_START_BIT; | |
1268 | Demod.posCount = 0; | |
1269 | Demod.len = 0; | |
1270 | } | |
1271 | } else { | |
1272 | // low phase of SOF too long (> 12 etu) | |
1273 | if(Demod.posCount > 13*2) { | |
1274 | Demod.state = DEMOD_UNSYNCD; | |
1275 | LED_C_OFF(); | |
1276 | } | |
1277 | } | |
1278 | break; | |
1279 | ||
1280 | case DEMOD_AWAITING_START_BIT: | |
1281 | ++Demod.posCount; | |
1282 | ||
1283 | MAKE_SOFT_DECISION() | |
1284 | ||
1285 | if(v > 0) { | |
1286 | // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs | |
1287 | if(Demod.posCount > 3*2) { | |
1288 | Demod.state = DEMOD_UNSYNCD; | |
1289 | LED_C_OFF(); | |
1290 | } | |
1291 | } else { | |
1292 | // start bit detected | |
1293 | Demod.bitCount = 0; | |
1294 | Demod.posCount = 1; // this was the first half | |
1295 | Demod.thisBit = v; | |
1296 | Demod.shiftReg = 0; | |
1297 | Demod.state = DEMOD_RECEIVING_DATA; | |
1298 | } | |
1299 | break; | |
1300 | ||
1301 | case DEMOD_RECEIVING_DATA: | |
1302 | ||
1303 | MAKE_SOFT_DECISION() | |
1304 | ||
1305 | if(Demod.posCount == 0) { | |
1306 | // first half of bit | |
1307 | Demod.thisBit = v; | |
1308 | Demod.posCount = 1; | |
1309 | } else { | |
1310 | // second half of bit | |
1311 | Demod.thisBit += v; | |
1312 | Demod.shiftReg >>= 1; | |
1313 | // logic '1' | |
1314 | if(Demod.thisBit > 0) | |
1315 | Demod.shiftReg |= 0x200; | |
1316 | ||
1317 | ++Demod.bitCount; | |
1318 | ||
1319 | if(Demod.bitCount == 10) { | |
1320 | ||
1321 | uint16_t s = Demod.shiftReg; | |
1322 | ||
1323 | if((s & 0x200) && !(s & 0x001)) { | |
1324 | // stop bit == '1', start bit == '0' | |
1325 | uint8_t b = (s >> 1); | |
1326 | Demod.output[Demod.len] = b; | |
1327 | ++Demod.len; | |
1328 | Demod.state = DEMOD_AWAITING_START_BIT; | |
1329 | } else { | |
1330 | Demod.state = DEMOD_UNSYNCD; | |
1331 | LED_C_OFF(); | |
1332 | ||
1333 | if(s == 0x000) { | |
1334 | // This is EOF (start, stop and all data bits == '0' | |
1335 | return TRUE; | |
1336 | } | |
1337 | } | |
1338 | } | |
1339 | Demod.posCount = 0; | |
1340 | } | |
1341 | break; | |
1342 | ||
1343 | default: | |
1344 | Demod.state = DEMOD_UNSYNCD; | |
1345 | LED_C_OFF(); | |
1346 | break; | |
1347 | } | |
1348 | return FALSE; | |
1349 | } | |
1350 | */ | |
1351 | /* | |
1352 | // Clear out the state of the "UART" that receives from the tag. | |
1353 | static void DemodReset() { | |
1354 | Demod.len = 0; | |
1355 | Demod.state = DEMOD_UNSYNCD; | |
1356 | Demod.posCount = 0; | |
1357 | Demod.sumI = 0; | |
1358 | Demod.sumQ = 0; | |
1359 | Demod.bitCount = 0; | |
1360 | Demod.thisBit = 0; | |
1361 | Demod.shiftReg = 0; | |
1362 | memset(Demod.output, 0x00, 3); | |
1363 | } | |
1364 | ||
1365 | static void DemodInit(uint8_t *data) { | |
1366 | Demod.output = data; | |
1367 | DemodReset(); | |
1368 | } | |
1369 | */ | |
1370 | ||
1371 | /* | |
1372 | * Demodulate the samples we received from the tag, also log to tracebuffer | |
1373 | * quiet: set to 'TRUE' to disable debug output | |
1374 | */ | |
1375 | ||
1376 | /* | |
1377 | #define LEGIC_DMA_BUFFER_SIZE 256 | |
1378 | ||
1379 | static void GetSamplesForLegicDemod(int n, bool quiet) | |
1380 | { | |
1381 | int max = 0; | |
1382 | bool gotFrame = FALSE; | |
1383 | int lastRxCounter = LEGIC_DMA_BUFFER_SIZE; | |
1384 | int ci, cq, samples = 0; | |
1385 | ||
1386 | BigBuf_free(); | |
1387 | ||
1388 | // And put the FPGA in the appropriate mode | |
1389 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ); | |
1390 | ||
1391 | // The response (tag -> reader) that we're receiving. | |
1392 | // Set up the demodulator for tag -> reader responses. | |
1393 | DemodInit(BigBuf_malloc(MAX_FRAME_SIZE)); | |
1394 | ||
1395 | // The DMA buffer, used to stream samples from the FPGA | |
1396 | int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE); | |
1397 | int8_t *upTo = dmaBuf; | |
1398 | ||
1399 | // Setup and start DMA. | |
1400 | if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){ | |
1401 | if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting"); | |
1402 | return; | |
1403 | } | |
1404 | ||
1405 | // Signal field is ON with the appropriate LED: | |
1406 | LED_D_ON(); | |
1407 | for(;;) { | |
1408 | int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR; | |
1409 | if(behindBy > max) max = behindBy; | |
1410 | ||
1411 | while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) { | |
1412 | ci = upTo[0]; | |
1413 | cq = upTo[1]; | |
1414 | upTo += 2; | |
1415 | if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) { | |
1416 | upTo = dmaBuf; | |
1417 | AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo; | |
1418 | AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE; | |
1419 | } | |
1420 | lastRxCounter -= 2; | |
1421 | if(lastRxCounter <= 0) | |
1422 | lastRxCounter = LEGIC_DMA_BUFFER_SIZE; | |
1423 | ||
1424 | samples += 2; | |
1425 | ||
1426 | gotFrame = HandleLegicSamplesDemod(ci , cq ); | |
1427 | if ( gotFrame ) | |
1428 | break; | |
1429 | } | |
1430 | ||
1431 | if(samples > n || gotFrame) | |
1432 | break; | |
1433 | } | |
1434 | ||
1435 | FpgaDisableSscDma(); | |
1436 | ||
1437 | if (!quiet && Demod.len == 0) { | |
1438 | Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", | |
1439 | max, | |
1440 | samples, | |
1441 | gotFrame, | |
1442 | Demod.len, | |
1443 | Demod.sumI, | |
1444 | Demod.sumQ | |
1445 | ); | |
1446 | } | |
1447 | ||
1448 | //Tracing | |
1449 | if (Demod.len > 0) { | |
1450 | uint8_t parity[MAX_PARITY_SIZE] = {0x00}; | |
1451 | LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE); | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | */ | |
1456 | ||
1457 | //----------------------------------------------------------------------------- | |
1458 | // Transmit the command (to the tag) that was placed in ToSend[]. | |
1459 | //----------------------------------------------------------------------------- | |
1460 | /* | |
1461 | static void TransmitForLegic(void) | |
1462 | { | |
1463 | int c; | |
1464 | ||
1465 | FpgaSetupSsc(); | |
1466 | ||
1467 | while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) | |
1468 | AT91C_BASE_SSC->SSC_THR = 0xff; | |
1469 | ||
1470 | // Signal field is ON with the appropriate Red LED | |
1471 | LED_D_ON(); | |
1472 | ||
1473 | // Signal we are transmitting with the Green LED | |
1474 | LED_B_ON(); | |
1475 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD); | |
1476 | ||
1477 | for(c = 0; c < 10;) { | |
1478 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { | |
1479 | AT91C_BASE_SSC->SSC_THR = 0xff; | |
1480 | c++; | |
1481 | } | |
1482 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { | |
1483 | volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; | |
1484 | (void)r; | |
1485 | } | |
1486 | WDT_HIT(); | |
1487 | } | |
1488 | ||
1489 | c = 0; | |
1490 | for(;;) { | |
1491 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { | |
1492 | AT91C_BASE_SSC->SSC_THR = ToSend[c]; | |
1493 | legic_prng_forward(1); // forward the lfsr | |
1494 | c++; | |
1495 | if(c >= ToSendMax) { | |
1496 | break; | |
1497 | } | |
1498 | } | |
1499 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { | |
1500 | volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR; | |
1501 | (void)r; | |
1502 | } | |
1503 | WDT_HIT(); | |
1504 | } | |
1505 | LED_B_OFF(); | |
1506 | } | |
1507 | */ | |
1508 | ||
1509 | //----------------------------------------------------------------------------- | |
1510 | // Code a layer 2 command (string of octets, including CRC) into ToSend[], | |
1511 | // so that it is ready to transmit to the tag using TransmitForLegic(). | |
1512 | //----------------------------------------------------------------------------- | |
1513 | /* | |
1514 | static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits) | |
1515 | { | |
1516 | int i, j; | |
1517 | uint8_t b; | |
1518 | ||
1519 | ToSendReset(); | |
1520 | ||
1521 | // Send SOF | |
1522 | for(i = 0; i < 7; i++) | |
1523 | ToSendStuffBit(1); | |
1524 | ||
1525 | ||
1526 | for(i = 0; i < cmdlen; i++) { | |
1527 | // Start bit | |
1528 | ToSendStuffBit(0); | |
1529 | ||
1530 | // Data bits | |
1531 | b = cmd[i]; | |
1532 | for(j = 0; j < bits; j++) { | |
1533 | if(b & 1) { | |
1534 | ToSendStuffBit(1); | |
1535 | } else { | |
1536 | ToSendStuffBit(0); | |
1537 | } | |
1538 | b >>= 1; | |
1539 | } | |
1540 | } | |
1541 | ||
1542 | // Convert from last character reference to length | |
1543 | ++ToSendMax; | |
1544 | } | |
1545 | */ | |
1546 | /** | |
1547 | Convenience function to encode, transmit and trace Legic comms | |
1548 | **/ | |
1549 | /* | |
1550 | static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits) | |
1551 | { | |
1552 | CodeLegicBitsAsReader(cmd, cmdlen, bits); | |
1553 | TransmitForLegic(); | |
1554 | if (tracing) { | |
1555 | uint8_t parity[1] = {0x00}; | |
1556 | LogTrace(cmd, cmdlen, 0, 0, parity, TRUE); | |
1557 | } | |
1558 | } | |
1559 | ||
1560 | */ | |
1561 | // Set up LEGIC communication | |
1562 | /* | |
1563 | void ice_legic_setup() { | |
1564 | ||
1565 | // standard things. | |
1566 | FpgaDownloadAndGo(FPGA_BITSTREAM_HF); | |
1567 | BigBuf_free(); BigBuf_Clear_ext(false); | |
1568 | clear_trace(); | |
1569 | set_tracing(TRUE); | |
1570 | DemodReset(); | |
1571 | UartReset(); | |
1572 | ||
1573 | // Set up the synchronous serial port | |
1574 | FpgaSetupSsc(); | |
1575 | ||
1576 | // connect Demodulated Signal to ADC: | |
1577 | SetAdcMuxFor(GPIO_MUXSEL_HIPKD); | |
1578 | ||
1579 | // Signal field is on with the appropriate LED | |
1580 | LED_D_ON(); | |
1581 | FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD); | |
1582 | SpinDelay(20); | |
1583 | // Start the timer | |
1584 | //StartCountSspClk(); | |
1585 | ||
1586 | // initalize CRC | |
1587 | crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0); | |
1588 | ||
1589 | // initalize prng | |
1590 | legic_prng_init(0); | |
1591 | } | |
1592 | */ |