| 1 | //----------------------------------------------------------------------------- |
| 2 | // This code is licensed to you under the terms of the GNU GPL, version 2 or, |
| 3 | // at your option, any later version. See the LICENSE.txt file for the text of |
| 4 | // the license. |
| 5 | //----------------------------------------------------------------------------- |
| 6 | // Miscellaneous routines for low frequency tag operations. |
| 7 | // Tags supported here so far are Texas Instruments (TI), HID |
| 8 | // Also routines for raw mode reading/simulating of LF waveform |
| 9 | //----------------------------------------------------------------------------- |
| 10 | |
| 11 | #include "proxmark3.h" |
| 12 | #include "apps.h" |
| 13 | #include "util.h" |
| 14 | #include "hitag2.h" |
| 15 | #include "crc16.h" |
| 16 | #include "string.h" |
| 17 | |
| 18 | void AcquireRawAdcSamples125k(int at134khz) |
| 19 | { |
| 20 | if (at134khz) |
| 21 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz |
| 22 | else |
| 23 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 24 | |
| 25 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 26 | |
| 27 | // Connect the A/D to the peak-detected low-frequency path. |
| 28 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); |
| 29 | |
| 30 | // Give it a bit of time for the resonant antenna to settle. |
| 31 | SpinDelay(50); |
| 32 | |
| 33 | // Now set up the SSC to get the ADC samples that are now streaming at us. |
| 34 | FpgaSetupSsc(); |
| 35 | |
| 36 | // Now call the acquisition routine |
| 37 | DoAcquisition125k(); |
| 38 | } |
| 39 | |
| 40 | // split into two routines so we can avoid timing issues after sending commands // |
| 41 | void DoAcquisition125k(void) |
| 42 | { |
| 43 | uint8_t *dest = (uint8_t *)BigBuf; |
| 44 | int n = sizeof(BigBuf); |
| 45 | int i; |
| 46 | |
| 47 | memset(dest, 0, n); |
| 48 | i = 0; |
| 49 | for(;;) { |
| 50 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { |
| 51 | AT91C_BASE_SSC->SSC_THR = 0x43; |
| 52 | LED_D_ON(); |
| 53 | } |
| 54 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { |
| 55 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; |
| 56 | i++; |
| 57 | LED_D_OFF(); |
| 58 | if (i >= n) break; |
| 59 | } |
| 60 | } |
| 61 | Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...", |
| 62 | dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]); |
| 63 | } |
| 64 | |
| 65 | void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command) |
| 66 | { |
| 67 | int at134khz; |
| 68 | |
| 69 | /* Make sure the tag is reset */ |
| 70 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 71 | SpinDelay(2500); |
| 72 | |
| 73 | // see if 'h' was specified |
| 74 | if (command[strlen((char *) command) - 1] == 'h') |
| 75 | at134khz = TRUE; |
| 76 | else |
| 77 | at134khz = FALSE; |
| 78 | |
| 79 | if (at134khz) |
| 80 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz |
| 81 | else |
| 82 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 83 | |
| 84 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 85 | |
| 86 | // Give it a bit of time for the resonant antenna to settle. |
| 87 | SpinDelay(50); |
| 88 | // And a little more time for the tag to fully power up |
| 89 | SpinDelay(2000); |
| 90 | |
| 91 | // Now set up the SSC to get the ADC samples that are now streaming at us. |
| 92 | FpgaSetupSsc(); |
| 93 | |
| 94 | // now modulate the reader field |
| 95 | while(*command != '\0' && *command != ' ') { |
| 96 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 97 | LED_D_OFF(); |
| 98 | SpinDelayUs(delay_off); |
| 99 | if (at134khz) |
| 100 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz |
| 101 | else |
| 102 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 103 | |
| 104 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 105 | LED_D_ON(); |
| 106 | if(*(command++) == '0') |
| 107 | SpinDelayUs(period_0); |
| 108 | else |
| 109 | SpinDelayUs(period_1); |
| 110 | } |
| 111 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 112 | LED_D_OFF(); |
| 113 | SpinDelayUs(delay_off); |
| 114 | if (at134khz) |
| 115 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz |
| 116 | else |
| 117 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 118 | |
| 119 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 120 | |
| 121 | // now do the read |
| 122 | DoAcquisition125k(); |
| 123 | } |
| 124 | |
| 125 | /* blank r/w tag data stream |
| 126 | ...0000000000000000 01111111 |
| 127 | 1010101010101010101010101010101010101010101010101010101010101010 |
| 128 | 0011010010100001 |
| 129 | 01111111 |
| 130 | 101010101010101[0]000... |
| 131 | |
| 132 | [5555fe852c5555555555555555fe0000] |
| 133 | */ |
| 134 | void ReadTItag(void) |
| 135 | { |
| 136 | // some hardcoded initial params |
| 137 | // when we read a TI tag we sample the zerocross line at 2Mhz |
| 138 | // TI tags modulate a 1 as 16 cycles of 123.2Khz |
| 139 | // TI tags modulate a 0 as 16 cycles of 134.2Khz |
| 140 | #define FSAMPLE 2000000 |
| 141 | #define FREQLO 123200 |
| 142 | #define FREQHI 134200 |
| 143 | |
| 144 | signed char *dest = (signed char *)BigBuf; |
| 145 | int n = sizeof(BigBuf); |
| 146 | // int *dest = GraphBuffer; |
| 147 | // int n = GraphTraceLen; |
| 148 | |
| 149 | // 128 bit shift register [shift3:shift2:shift1:shift0] |
| 150 | uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0; |
| 151 | |
| 152 | int i, cycles=0, samples=0; |
| 153 | // how many sample points fit in 16 cycles of each frequency |
| 154 | uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI; |
| 155 | // when to tell if we're close enough to one freq or another |
| 156 | uint32_t threshold = (sampleslo - sampleshi + 1)>>1; |
| 157 | |
| 158 | // TI tags charge at 134.2Khz |
| 159 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz |
| 160 | |
| 161 | // Place FPGA in passthrough mode, in this mode the CROSS_LO line |
| 162 | // connects to SSP_DIN and the SSP_DOUT logic level controls |
| 163 | // whether we're modulating the antenna (high) |
| 164 | // or listening to the antenna (low) |
| 165 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); |
| 166 | |
| 167 | // get TI tag data into the buffer |
| 168 | AcquireTiType(); |
| 169 | |
| 170 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 171 | |
| 172 | for (i=0; i<n-1; i++) { |
| 173 | // count cycles by looking for lo to hi zero crossings |
| 174 | if ( (dest[i]<0) && (dest[i+1]>0) ) { |
| 175 | cycles++; |
| 176 | // after 16 cycles, measure the frequency |
| 177 | if (cycles>15) { |
| 178 | cycles=0; |
| 179 | samples=i-samples; // number of samples in these 16 cycles |
| 180 | |
| 181 | // TI bits are coming to us lsb first so shift them |
| 182 | // right through our 128 bit right shift register |
| 183 | shift0 = (shift0>>1) | (shift1 << 31); |
| 184 | shift1 = (shift1>>1) | (shift2 << 31); |
| 185 | shift2 = (shift2>>1) | (shift3 << 31); |
| 186 | shift3 >>= 1; |
| 187 | |
| 188 | // check if the cycles fall close to the number |
| 189 | // expected for either the low or high frequency |
| 190 | if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) { |
| 191 | // low frequency represents a 1 |
| 192 | shift3 |= (1<<31); |
| 193 | } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) { |
| 194 | // high frequency represents a 0 |
| 195 | } else { |
| 196 | // probably detected a gay waveform or noise |
| 197 | // use this as gaydar or discard shift register and start again |
| 198 | shift3 = shift2 = shift1 = shift0 = 0; |
| 199 | } |
| 200 | samples = i; |
| 201 | |
| 202 | // for each bit we receive, test if we've detected a valid tag |
| 203 | |
| 204 | // if we see 17 zeroes followed by 6 ones, we might have a tag |
| 205 | // remember the bits are backwards |
| 206 | if ( ((shift0 & 0x7fffff) == 0x7e0000) ) { |
| 207 | // if start and end bytes match, we have a tag so break out of the loop |
| 208 | if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) { |
| 209 | cycles = 0xF0B; //use this as a flag (ugly but whatever) |
| 210 | break; |
| 211 | } |
| 212 | } |
| 213 | } |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | // if flag is set we have a tag |
| 218 | if (cycles!=0xF0B) { |
| 219 | DbpString("Info: No valid tag detected."); |
| 220 | } else { |
| 221 | // put 64 bit data into shift1 and shift0 |
| 222 | shift0 = (shift0>>24) | (shift1 << 8); |
| 223 | shift1 = (shift1>>24) | (shift2 << 8); |
| 224 | |
| 225 | // align 16 bit crc into lower half of shift2 |
| 226 | shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff; |
| 227 | |
| 228 | // if r/w tag, check ident match |
| 229 | if ( shift3&(1<<15) ) { |
| 230 | DbpString("Info: TI tag is rewriteable"); |
| 231 | // only 15 bits compare, last bit of ident is not valid |
| 232 | if ( ((shift3>>16)^shift0)&0x7fff ) { |
| 233 | DbpString("Error: Ident mismatch!"); |
| 234 | } else { |
| 235 | DbpString("Info: TI tag ident is valid"); |
| 236 | } |
| 237 | } else { |
| 238 | DbpString("Info: TI tag is readonly"); |
| 239 | } |
| 240 | |
| 241 | // WARNING the order of the bytes in which we calc crc below needs checking |
| 242 | // i'm 99% sure the crc algorithm is correct, but it may need to eat the |
| 243 | // bytes in reverse or something |
| 244 | // calculate CRC |
| 245 | uint32_t crc=0; |
| 246 | |
| 247 | crc = update_crc16(crc, (shift0)&0xff); |
| 248 | crc = update_crc16(crc, (shift0>>8)&0xff); |
| 249 | crc = update_crc16(crc, (shift0>>16)&0xff); |
| 250 | crc = update_crc16(crc, (shift0>>24)&0xff); |
| 251 | crc = update_crc16(crc, (shift1)&0xff); |
| 252 | crc = update_crc16(crc, (shift1>>8)&0xff); |
| 253 | crc = update_crc16(crc, (shift1>>16)&0xff); |
| 254 | crc = update_crc16(crc, (shift1>>24)&0xff); |
| 255 | |
| 256 | Dbprintf("Info: Tag data: %x%08x, crc=%x", |
| 257 | (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF); |
| 258 | if (crc != (shift2&0xffff)) { |
| 259 | Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc); |
| 260 | } else { |
| 261 | DbpString("Info: CRC is good"); |
| 262 | } |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | void WriteTIbyte(uint8_t b) |
| 267 | { |
| 268 | int i = 0; |
| 269 | |
| 270 | // modulate 8 bits out to the antenna |
| 271 | for (i=0; i<8; i++) |
| 272 | { |
| 273 | if (b&(1<<i)) { |
| 274 | // stop modulating antenna |
| 275 | LOW(GPIO_SSC_DOUT); |
| 276 | SpinDelayUs(1000); |
| 277 | // modulate antenna |
| 278 | HIGH(GPIO_SSC_DOUT); |
| 279 | SpinDelayUs(1000); |
| 280 | } else { |
| 281 | // stop modulating antenna |
| 282 | LOW(GPIO_SSC_DOUT); |
| 283 | SpinDelayUs(300); |
| 284 | // modulate antenna |
| 285 | HIGH(GPIO_SSC_DOUT); |
| 286 | SpinDelayUs(1700); |
| 287 | } |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | void AcquireTiType(void) |
| 292 | { |
| 293 | int i, j, n; |
| 294 | // tag transmission is <20ms, sampling at 2M gives us 40K samples max |
| 295 | // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t |
| 296 | #define TIBUFLEN 1250 |
| 297 | |
| 298 | // clear buffer |
| 299 | memset(BigBuf,0,sizeof(BigBuf)); |
| 300 | |
| 301 | // Set up the synchronous serial port |
| 302 | AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN; |
| 303 | AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN; |
| 304 | |
| 305 | // steal this pin from the SSP and use it to control the modulation |
| 306 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; |
| 307 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; |
| 308 | |
| 309 | AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST; |
| 310 | AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN; |
| 311 | |
| 312 | // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long |
| 313 | // 48/2 = 24 MHz clock must be divided by 12 |
| 314 | AT91C_BASE_SSC->SSC_CMR = 12; |
| 315 | |
| 316 | AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0); |
| 317 | AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF; |
| 318 | AT91C_BASE_SSC->SSC_TCMR = 0; |
| 319 | AT91C_BASE_SSC->SSC_TFMR = 0; |
| 320 | |
| 321 | LED_D_ON(); |
| 322 | |
| 323 | // modulate antenna |
| 324 | HIGH(GPIO_SSC_DOUT); |
| 325 | |
| 326 | // Charge TI tag for 50ms. |
| 327 | SpinDelay(50); |
| 328 | |
| 329 | // stop modulating antenna and listen |
| 330 | LOW(GPIO_SSC_DOUT); |
| 331 | |
| 332 | LED_D_OFF(); |
| 333 | |
| 334 | i = 0; |
| 335 | for(;;) { |
| 336 | if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { |
| 337 | BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer |
| 338 | i++; if(i >= TIBUFLEN) break; |
| 339 | } |
| 340 | WDT_HIT(); |
| 341 | } |
| 342 | |
| 343 | // return stolen pin to SSP |
| 344 | AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT; |
| 345 | AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT; |
| 346 | |
| 347 | char *dest = (char *)BigBuf; |
| 348 | n = TIBUFLEN*32; |
| 349 | // unpack buffer |
| 350 | for (i=TIBUFLEN-1; i>=0; i--) { |
| 351 | for (j=0; j<32; j++) { |
| 352 | if(BigBuf[i] & (1 << j)) { |
| 353 | dest[--n] = 1; |
| 354 | } else { |
| 355 | dest[--n] = -1; |
| 356 | } |
| 357 | } |
| 358 | } |
| 359 | } |
| 360 | |
| 361 | // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc |
| 362 | // if crc provided, it will be written with the data verbatim (even if bogus) |
| 363 | // if not provided a valid crc will be computed from the data and written. |
| 364 | void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc) |
| 365 | { |
| 366 | if(crc == 0) { |
| 367 | crc = update_crc16(crc, (idlo)&0xff); |
| 368 | crc = update_crc16(crc, (idlo>>8)&0xff); |
| 369 | crc = update_crc16(crc, (idlo>>16)&0xff); |
| 370 | crc = update_crc16(crc, (idlo>>24)&0xff); |
| 371 | crc = update_crc16(crc, (idhi)&0xff); |
| 372 | crc = update_crc16(crc, (idhi>>8)&0xff); |
| 373 | crc = update_crc16(crc, (idhi>>16)&0xff); |
| 374 | crc = update_crc16(crc, (idhi>>24)&0xff); |
| 375 | } |
| 376 | Dbprintf("Writing to tag: %x%08x, crc=%x", |
| 377 | (unsigned int) idhi, (unsigned int) idlo, crc); |
| 378 | |
| 379 | // TI tags charge at 134.2Khz |
| 380 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz |
| 381 | // Place FPGA in passthrough mode, in this mode the CROSS_LO line |
| 382 | // connects to SSP_DIN and the SSP_DOUT logic level controls |
| 383 | // whether we're modulating the antenna (high) |
| 384 | // or listening to the antenna (low) |
| 385 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU); |
| 386 | LED_A_ON(); |
| 387 | |
| 388 | // steal this pin from the SSP and use it to control the modulation |
| 389 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; |
| 390 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; |
| 391 | |
| 392 | // writing algorithm: |
| 393 | // a high bit consists of a field off for 1ms and field on for 1ms |
| 394 | // a low bit consists of a field off for 0.3ms and field on for 1.7ms |
| 395 | // initiate a charge time of 50ms (field on) then immediately start writing bits |
| 396 | // start by writing 0xBB (keyword) and 0xEB (password) |
| 397 | // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer) |
| 398 | // finally end with 0x0300 (write frame) |
| 399 | // all data is sent lsb firts |
| 400 | // finish with 15ms programming time |
| 401 | |
| 402 | // modulate antenna |
| 403 | HIGH(GPIO_SSC_DOUT); |
| 404 | SpinDelay(50); // charge time |
| 405 | |
| 406 | WriteTIbyte(0xbb); // keyword |
| 407 | WriteTIbyte(0xeb); // password |
| 408 | WriteTIbyte( (idlo )&0xff ); |
| 409 | WriteTIbyte( (idlo>>8 )&0xff ); |
| 410 | WriteTIbyte( (idlo>>16)&0xff ); |
| 411 | WriteTIbyte( (idlo>>24)&0xff ); |
| 412 | WriteTIbyte( (idhi )&0xff ); |
| 413 | WriteTIbyte( (idhi>>8 )&0xff ); |
| 414 | WriteTIbyte( (idhi>>16)&0xff ); |
| 415 | WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo |
| 416 | WriteTIbyte( (crc )&0xff ); // crc lo |
| 417 | WriteTIbyte( (crc>>8 )&0xff ); // crc hi |
| 418 | WriteTIbyte(0x00); // write frame lo |
| 419 | WriteTIbyte(0x03); // write frame hi |
| 420 | HIGH(GPIO_SSC_DOUT); |
| 421 | SpinDelay(50); // programming time |
| 422 | |
| 423 | LED_A_OFF(); |
| 424 | |
| 425 | // get TI tag data into the buffer |
| 426 | AcquireTiType(); |
| 427 | |
| 428 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 429 | DbpString("Now use tiread to check"); |
| 430 | } |
| 431 | |
| 432 | void SimulateTagLowFrequency(int period, int gap, int ledcontrol) |
| 433 | { |
| 434 | int i; |
| 435 | uint8_t *tab = (uint8_t *)BigBuf; |
| 436 | |
| 437 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT); |
| 438 | |
| 439 | AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; |
| 440 | |
| 441 | AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; |
| 442 | AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; |
| 443 | |
| 444 | #define SHORT_COIL() LOW(GPIO_SSC_DOUT) |
| 445 | #define OPEN_COIL() HIGH(GPIO_SSC_DOUT) |
| 446 | |
| 447 | i = 0; |
| 448 | for(;;) { |
| 449 | while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { |
| 450 | if(BUTTON_PRESS()) { |
| 451 | DbpString("Stopped"); |
| 452 | return; |
| 453 | } |
| 454 | WDT_HIT(); |
| 455 | } |
| 456 | |
| 457 | if (ledcontrol) |
| 458 | LED_D_ON(); |
| 459 | |
| 460 | if(tab[i]) |
| 461 | OPEN_COIL(); |
| 462 | else |
| 463 | SHORT_COIL(); |
| 464 | |
| 465 | if (ledcontrol) |
| 466 | LED_D_OFF(); |
| 467 | |
| 468 | while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { |
| 469 | if(BUTTON_PRESS()) { |
| 470 | DbpString("Stopped"); |
| 471 | return; |
| 472 | } |
| 473 | WDT_HIT(); |
| 474 | } |
| 475 | |
| 476 | i++; |
| 477 | if(i == period) { |
| 478 | i = 0; |
| 479 | if (gap) { |
| 480 | SHORT_COIL(); |
| 481 | SpinDelayUs(gap); |
| 482 | } |
| 483 | } |
| 484 | } |
| 485 | } |
| 486 | |
| 487 | #define DEBUG_FRAME_CONTENTS 1 |
| 488 | void SimulateTagLowFrequencyBidir(int divisor, int t0) |
| 489 | { |
| 490 | } |
| 491 | |
| 492 | // compose fc/8 fc/10 waveform |
| 493 | static void fc(int c, int *n) { |
| 494 | uint8_t *dest = (uint8_t *)BigBuf; |
| 495 | int idx; |
| 496 | |
| 497 | // for when we want an fc8 pattern every 4 logical bits |
| 498 | if(c==0) { |
| 499 | dest[((*n)++)]=1; |
| 500 | dest[((*n)++)]=1; |
| 501 | dest[((*n)++)]=0; |
| 502 | dest[((*n)++)]=0; |
| 503 | dest[((*n)++)]=0; |
| 504 | dest[((*n)++)]=0; |
| 505 | dest[((*n)++)]=0; |
| 506 | dest[((*n)++)]=0; |
| 507 | } |
| 508 | // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples |
| 509 | if(c==8) { |
| 510 | for (idx=0; idx<6; idx++) { |
| 511 | dest[((*n)++)]=1; |
| 512 | dest[((*n)++)]=1; |
| 513 | dest[((*n)++)]=0; |
| 514 | dest[((*n)++)]=0; |
| 515 | dest[((*n)++)]=0; |
| 516 | dest[((*n)++)]=0; |
| 517 | dest[((*n)++)]=0; |
| 518 | dest[((*n)++)]=0; |
| 519 | } |
| 520 | } |
| 521 | |
| 522 | // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples |
| 523 | if(c==10) { |
| 524 | for (idx=0; idx<5; idx++) { |
| 525 | dest[((*n)++)]=1; |
| 526 | dest[((*n)++)]=1; |
| 527 | dest[((*n)++)]=1; |
| 528 | dest[((*n)++)]=0; |
| 529 | dest[((*n)++)]=0; |
| 530 | dest[((*n)++)]=0; |
| 531 | dest[((*n)++)]=0; |
| 532 | dest[((*n)++)]=0; |
| 533 | dest[((*n)++)]=0; |
| 534 | dest[((*n)++)]=0; |
| 535 | } |
| 536 | } |
| 537 | } |
| 538 | |
| 539 | // prepare a waveform pattern in the buffer based on the ID given then |
| 540 | // simulate a HID tag until the button is pressed |
| 541 | void CmdHIDsimTAG(int hi, int lo, int ledcontrol) |
| 542 | { |
| 543 | int n=0, i=0; |
| 544 | /* |
| 545 | HID tag bitstream format |
| 546 | The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits |
| 547 | A 1 bit is represented as 6 fc8 and 5 fc10 patterns |
| 548 | A 0 bit is represented as 5 fc10 and 6 fc8 patterns |
| 549 | A fc8 is inserted before every 4 bits |
| 550 | A special start of frame pattern is used consisting a0b0 where a and b are neither 0 |
| 551 | nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10) |
| 552 | */ |
| 553 | |
| 554 | if (hi>0xFFF) { |
| 555 | DbpString("Tags can only have 44 bits."); |
| 556 | return; |
| 557 | } |
| 558 | fc(0,&n); |
| 559 | // special start of frame marker containing invalid bit sequences |
| 560 | fc(8, &n); fc(8, &n); // invalid |
| 561 | fc(8, &n); fc(10, &n); // logical 0 |
| 562 | fc(10, &n); fc(10, &n); // invalid |
| 563 | fc(8, &n); fc(10, &n); // logical 0 |
| 564 | |
| 565 | WDT_HIT(); |
| 566 | // manchester encode bits 43 to 32 |
| 567 | for (i=11; i>=0; i--) { |
| 568 | if ((i%4)==3) fc(0,&n); |
| 569 | if ((hi>>i)&1) { |
| 570 | fc(10, &n); fc(8, &n); // low-high transition |
| 571 | } else { |
| 572 | fc(8, &n); fc(10, &n); // high-low transition |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | WDT_HIT(); |
| 577 | // manchester encode bits 31 to 0 |
| 578 | for (i=31; i>=0; i--) { |
| 579 | if ((i%4)==3) fc(0,&n); |
| 580 | if ((lo>>i)&1) { |
| 581 | fc(10, &n); fc(8, &n); // low-high transition |
| 582 | } else { |
| 583 | fc(8, &n); fc(10, &n); // high-low transition |
| 584 | } |
| 585 | } |
| 586 | |
| 587 | if (ledcontrol) |
| 588 | LED_A_ON(); |
| 589 | SimulateTagLowFrequency(n, 0, ledcontrol); |
| 590 | |
| 591 | if (ledcontrol) |
| 592 | LED_A_OFF(); |
| 593 | } |
| 594 | |
| 595 | |
| 596 | // loop to capture raw HID waveform then FSK demodulate the TAG ID from it |
| 597 | void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol) |
| 598 | { |
| 599 | uint8_t *dest = (uint8_t *)BigBuf; |
| 600 | int m=0, n=0, i=0, idx=0, found=0, lastval=0; |
| 601 | uint32_t hi2=0, hi=0, lo=0; |
| 602 | |
| 603 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 604 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 605 | |
| 606 | // Connect the A/D to the peak-detected low-frequency path. |
| 607 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); |
| 608 | |
| 609 | // Give it a bit of time for the resonant antenna to settle. |
| 610 | SpinDelay(50); |
| 611 | |
| 612 | // Now set up the SSC to get the ADC samples that are now streaming at us. |
| 613 | FpgaSetupSsc(); |
| 614 | |
| 615 | for(;;) { |
| 616 | WDT_HIT(); |
| 617 | if (ledcontrol) |
| 618 | LED_A_ON(); |
| 619 | if(BUTTON_PRESS()) { |
| 620 | DbpString("Stopped"); |
| 621 | if (ledcontrol) |
| 622 | LED_A_OFF(); |
| 623 | return; |
| 624 | } |
| 625 | |
| 626 | i = 0; |
| 627 | m = sizeof(BigBuf); |
| 628 | memset(dest,128,m); |
| 629 | for(;;) { |
| 630 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) { |
| 631 | AT91C_BASE_SSC->SSC_THR = 0x43; |
| 632 | if (ledcontrol) |
| 633 | LED_D_ON(); |
| 634 | } |
| 635 | if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) { |
| 636 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; |
| 637 | // we don't care about actual value, only if it's more or less than a |
| 638 | // threshold essentially we capture zero crossings for later analysis |
| 639 | if(dest[i] < 127) dest[i] = 0; else dest[i] = 1; |
| 640 | i++; |
| 641 | if (ledcontrol) |
| 642 | LED_D_OFF(); |
| 643 | if(i >= m) { |
| 644 | break; |
| 645 | } |
| 646 | } |
| 647 | } |
| 648 | |
| 649 | // FSK demodulator |
| 650 | |
| 651 | // sync to first lo-hi transition |
| 652 | for( idx=1; idx<m; idx++) { |
| 653 | if (dest[idx-1]<dest[idx]) |
| 654 | lastval=idx; |
| 655 | break; |
| 656 | } |
| 657 | WDT_HIT(); |
| 658 | |
| 659 | // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8) |
| 660 | // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere |
| 661 | // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10 |
| 662 | for( i=0; idx<m; idx++) { |
| 663 | if (dest[idx-1]<dest[idx]) { |
| 664 | dest[i]=idx-lastval; |
| 665 | if (dest[i] <= 8) { |
| 666 | dest[i]=1; |
| 667 | } else { |
| 668 | dest[i]=0; |
| 669 | } |
| 670 | |
| 671 | lastval=idx; |
| 672 | i++; |
| 673 | } |
| 674 | } |
| 675 | m=i; |
| 676 | WDT_HIT(); |
| 677 | |
| 678 | // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns |
| 679 | lastval=dest[0]; |
| 680 | idx=0; |
| 681 | i=0; |
| 682 | n=0; |
| 683 | for( idx=0; idx<m; idx++) { |
| 684 | if (dest[idx]==lastval) { |
| 685 | n++; |
| 686 | } else { |
| 687 | // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents, |
| 688 | // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets |
| 689 | // swallowed up by rounding |
| 690 | // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding |
| 691 | // special start of frame markers use invalid manchester states (no transitions) by using sequences |
| 692 | // like 111000 |
| 693 | if (dest[idx-1]) { |
| 694 | n=(n+1)/6; // fc/8 in sets of 6 |
| 695 | } else { |
| 696 | n=(n+1)/5; // fc/10 in sets of 5 |
| 697 | } |
| 698 | switch (n) { // stuff appropriate bits in buffer |
| 699 | case 0: |
| 700 | case 1: // one bit |
| 701 | dest[i++]=dest[idx-1]; |
| 702 | break; |
| 703 | case 2: // two bits |
| 704 | dest[i++]=dest[idx-1]; |
| 705 | dest[i++]=dest[idx-1]; |
| 706 | break; |
| 707 | case 3: // 3 bit start of frame markers |
| 708 | dest[i++]=dest[idx-1]; |
| 709 | dest[i++]=dest[idx-1]; |
| 710 | dest[i++]=dest[idx-1]; |
| 711 | break; |
| 712 | // When a logic 0 is immediately followed by the start of the next transmisson |
| 713 | // (special pattern) a pattern of 4 bit duration lengths is created. |
| 714 | case 4: |
| 715 | dest[i++]=dest[idx-1]; |
| 716 | dest[i++]=dest[idx-1]; |
| 717 | dest[i++]=dest[idx-1]; |
| 718 | dest[i++]=dest[idx-1]; |
| 719 | break; |
| 720 | default: // this shouldn't happen, don't stuff any bits |
| 721 | break; |
| 722 | } |
| 723 | n=0; |
| 724 | lastval=dest[idx]; |
| 725 | } |
| 726 | } |
| 727 | m=i; |
| 728 | WDT_HIT(); |
| 729 | |
| 730 | // final loop, go over previously decoded manchester data and decode into usable tag ID |
| 731 | // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0 |
| 732 | for( idx=0; idx<m-6; idx++) { |
| 733 | // search for a start of frame marker |
| 734 | if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) ) |
| 735 | { |
| 736 | found=1; |
| 737 | idx+=6; |
| 738 | if (found && (hi2|hi|lo)) { |
| 739 | if (hi2 != 0){ |
| 740 | Dbprintf("TAG ID: %x%08x%08x (%d)", |
| 741 | (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); |
| 742 | } |
| 743 | else { |
| 744 | Dbprintf("TAG ID: %x%08x (%d)", |
| 745 | (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); |
| 746 | } |
| 747 | /* if we're only looking for one tag */ |
| 748 | if (findone) |
| 749 | { |
| 750 | *high = hi; |
| 751 | *low = lo; |
| 752 | return; |
| 753 | } |
| 754 | hi2=0; |
| 755 | hi=0; |
| 756 | lo=0; |
| 757 | found=0; |
| 758 | } |
| 759 | } |
| 760 | if (found) { |
| 761 | if (dest[idx] && (!dest[idx+1]) ) { |
| 762 | hi2=(hi2<<1)|(hi>>31); |
| 763 | hi=(hi<<1)|(lo>>31); |
| 764 | lo=(lo<<1)|0; |
| 765 | } else if ( (!dest[idx]) && dest[idx+1]) { |
| 766 | hi2=(hi2<<1)|(hi>>31); |
| 767 | hi=(hi<<1)|(lo>>31); |
| 768 | lo=(lo<<1)|1; |
| 769 | } else { |
| 770 | found=0; |
| 771 | hi2=0; |
| 772 | hi=0; |
| 773 | lo=0; |
| 774 | } |
| 775 | idx++; |
| 776 | } |
| 777 | if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) ) |
| 778 | { |
| 779 | found=1; |
| 780 | idx+=6; |
| 781 | if (found && (hi|lo)) { |
| 782 | if (hi2 != 0){ |
| 783 | Dbprintf("TAG ID: %x%08x%08x (%d)", |
| 784 | (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); |
| 785 | } |
| 786 | else { |
| 787 | Dbprintf("TAG ID: %x%08x (%d)", |
| 788 | (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); |
| 789 | } |
| 790 | /* if we're only looking for one tag */ |
| 791 | if (findone) |
| 792 | { |
| 793 | *high = hi; |
| 794 | *low = lo; |
| 795 | return; |
| 796 | } |
| 797 | hi2=0; |
| 798 | hi=0; |
| 799 | lo=0; |
| 800 | found=0; |
| 801 | } |
| 802 | } |
| 803 | } |
| 804 | WDT_HIT(); |
| 805 | } |
| 806 | } |
| 807 | |
| 808 | /*------------------------------ |
| 809 | * T5555/T5557/T5567 routines |
| 810 | *------------------------------ |
| 811 | */ |
| 812 | |
| 813 | /* T55x7 configuration register definitions */ |
| 814 | #define T55x7_POR_DELAY 0x00000001 |
| 815 | #define T55x7_ST_TERMINATOR 0x00000008 |
| 816 | #define T55x7_PWD 0x00000010 |
| 817 | #define T55x7_MAXBLOCK_SHIFT 5 |
| 818 | #define T55x7_AOR 0x00000200 |
| 819 | #define T55x7_PSKCF_RF_2 0 |
| 820 | #define T55x7_PSKCF_RF_4 0x00000400 |
| 821 | #define T55x7_PSKCF_RF_8 0x00000800 |
| 822 | #define T55x7_MODULATION_DIRECT 0 |
| 823 | #define T55x7_MODULATION_PSK1 0x00001000 |
| 824 | #define T55x7_MODULATION_PSK2 0x00002000 |
| 825 | #define T55x7_MODULATION_PSK3 0x00003000 |
| 826 | #define T55x7_MODULATION_FSK1 0x00004000 |
| 827 | #define T55x7_MODULATION_FSK2 0x00005000 |
| 828 | #define T55x7_MODULATION_FSK1a 0x00006000 |
| 829 | #define T55x7_MODULATION_FSK2a 0x00007000 |
| 830 | #define T55x7_MODULATION_MANCHESTER 0x00008000 |
| 831 | #define T55x7_MODULATION_BIPHASE 0x00010000 |
| 832 | #define T55x7_BITRATE_RF_8 0 |
| 833 | #define T55x7_BITRATE_RF_16 0x00040000 |
| 834 | #define T55x7_BITRATE_RF_32 0x00080000 |
| 835 | #define T55x7_BITRATE_RF_40 0x000C0000 |
| 836 | #define T55x7_BITRATE_RF_50 0x00100000 |
| 837 | #define T55x7_BITRATE_RF_64 0x00140000 |
| 838 | #define T55x7_BITRATE_RF_100 0x00180000 |
| 839 | #define T55x7_BITRATE_RF_128 0x001C0000 |
| 840 | |
| 841 | /* T5555 (Q5) configuration register definitions */ |
| 842 | #define T5555_ST_TERMINATOR 0x00000001 |
| 843 | #define T5555_MAXBLOCK_SHIFT 0x00000001 |
| 844 | #define T5555_MODULATION_MANCHESTER 0 |
| 845 | #define T5555_MODULATION_PSK1 0x00000010 |
| 846 | #define T5555_MODULATION_PSK2 0x00000020 |
| 847 | #define T5555_MODULATION_PSK3 0x00000030 |
| 848 | #define T5555_MODULATION_FSK1 0x00000040 |
| 849 | #define T5555_MODULATION_FSK2 0x00000050 |
| 850 | #define T5555_MODULATION_BIPHASE 0x00000060 |
| 851 | #define T5555_MODULATION_DIRECT 0x00000070 |
| 852 | #define T5555_INVERT_OUTPUT 0x00000080 |
| 853 | #define T5555_PSK_RF_2 0 |
| 854 | #define T5555_PSK_RF_4 0x00000100 |
| 855 | #define T5555_PSK_RF_8 0x00000200 |
| 856 | #define T5555_USE_PWD 0x00000400 |
| 857 | #define T5555_USE_AOR 0x00000800 |
| 858 | #define T5555_BITRATE_SHIFT 12 |
| 859 | #define T5555_FAST_WRITE 0x00004000 |
| 860 | #define T5555_PAGE_SELECT 0x00008000 |
| 861 | |
| 862 | /* |
| 863 | * Relevant times in microsecond |
| 864 | * To compensate antenna falling times shorten the write times |
| 865 | * and enlarge the gap ones. |
| 866 | */ |
| 867 | #define START_GAP 250 |
| 868 | #define WRITE_GAP 160 |
| 869 | #define WRITE_0 144 // 192 |
| 870 | #define WRITE_1 400 // 432 for T55x7; 448 for E5550 |
| 871 | |
| 872 | // Write one bit to card |
| 873 | void T55xxWriteBit(int bit) |
| 874 | { |
| 875 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 876 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 877 | if (bit == 0) |
| 878 | SpinDelayUs(WRITE_0); |
| 879 | else |
| 880 | SpinDelayUs(WRITE_1); |
| 881 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 882 | SpinDelayUs(WRITE_GAP); |
| 883 | } |
| 884 | |
| 885 | // Write one card block in page 0, no lock |
| 886 | void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode) |
| 887 | { |
| 888 | unsigned int i; |
| 889 | |
| 890 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 891 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 892 | |
| 893 | // Give it a bit of time for the resonant antenna to settle. |
| 894 | // And for the tag to fully power up |
| 895 | SpinDelay(150); |
| 896 | |
| 897 | // Now start writting |
| 898 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 899 | SpinDelayUs(START_GAP); |
| 900 | |
| 901 | // Opcode |
| 902 | T55xxWriteBit(1); |
| 903 | T55xxWriteBit(0); //Page 0 |
| 904 | if (PwdMode == 1){ |
| 905 | // Pwd |
| 906 | for (i = 0x80000000; i != 0; i >>= 1) |
| 907 | T55xxWriteBit(Pwd & i); |
| 908 | } |
| 909 | // Lock bit |
| 910 | T55xxWriteBit(0); |
| 911 | |
| 912 | // Data |
| 913 | for (i = 0x80000000; i != 0; i >>= 1) |
| 914 | T55xxWriteBit(Data & i); |
| 915 | |
| 916 | // Block |
| 917 | for (i = 0x04; i != 0; i >>= 1) |
| 918 | T55xxWriteBit(Block & i); |
| 919 | |
| 920 | // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550, |
| 921 | // so wait a little more) |
| 922 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 923 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 924 | SpinDelay(20); |
| 925 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 926 | } |
| 927 | |
| 928 | // Read one card block in page 0 |
| 929 | void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode) |
| 930 | { |
| 931 | uint8_t *dest = (uint8_t *)BigBuf; |
| 932 | int m=0, i=0; |
| 933 | |
| 934 | m = sizeof(BigBuf); |
| 935 | // Clear destination buffer before sending the command |
| 936 | memset(dest, 128, m); |
| 937 | // Connect the A/D to the peak-detected low-frequency path. |
| 938 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); |
| 939 | // Now set up the SSC to get the ADC samples that are now streaming at us. |
| 940 | FpgaSetupSsc(); |
| 941 | |
| 942 | LED_D_ON(); |
| 943 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 944 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 945 | |
| 946 | // Give it a bit of time for the resonant antenna to settle. |
| 947 | // And for the tag to fully power up |
| 948 | SpinDelay(150); |
| 949 | |
| 950 | // Now start writting |
| 951 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 952 | SpinDelayUs(START_GAP); |
| 953 | |
| 954 | // Opcode |
| 955 | T55xxWriteBit(1); |
| 956 | T55xxWriteBit(0); //Page 0 |
| 957 | if (PwdMode == 1){ |
| 958 | // Pwd |
| 959 | for (i = 0x80000000; i != 0; i >>= 1) |
| 960 | T55xxWriteBit(Pwd & i); |
| 961 | } |
| 962 | // Lock bit |
| 963 | T55xxWriteBit(0); |
| 964 | // Block |
| 965 | for (i = 0x04; i != 0; i >>= 1) |
| 966 | T55xxWriteBit(Block & i); |
| 967 | |
| 968 | // Turn field on to read the response |
| 969 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 970 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 971 | |
| 972 | // Now do the acquisition |
| 973 | i = 0; |
| 974 | for(;;) { |
| 975 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { |
| 976 | AT91C_BASE_SSC->SSC_THR = 0x43; |
| 977 | } |
| 978 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { |
| 979 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; |
| 980 | // we don't care about actual value, only if it's more or less than a |
| 981 | // threshold essentially we capture zero crossings for later analysis |
| 982 | // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1; |
| 983 | i++; |
| 984 | if (i >= m) break; |
| 985 | } |
| 986 | } |
| 987 | |
| 988 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off |
| 989 | LED_D_OFF(); |
| 990 | DbpString("DONE!"); |
| 991 | } |
| 992 | |
| 993 | // Read card traceability data (page 1) |
| 994 | void T55xxReadTrace(void){ |
| 995 | uint8_t *dest = (uint8_t *)BigBuf; |
| 996 | int m=0, i=0; |
| 997 | |
| 998 | m = sizeof(BigBuf); |
| 999 | // Clear destination buffer before sending the command |
| 1000 | memset(dest, 128, m); |
| 1001 | // Connect the A/D to the peak-detected low-frequency path. |
| 1002 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); |
| 1003 | // Now set up the SSC to get the ADC samples that are now streaming at us. |
| 1004 | FpgaSetupSsc(); |
| 1005 | |
| 1006 | LED_D_ON(); |
| 1007 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 1008 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 1009 | |
| 1010 | // Give it a bit of time for the resonant antenna to settle. |
| 1011 | // And for the tag to fully power up |
| 1012 | SpinDelay(150); |
| 1013 | |
| 1014 | // Now start writting |
| 1015 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); |
| 1016 | SpinDelayUs(START_GAP); |
| 1017 | |
| 1018 | // Opcode |
| 1019 | T55xxWriteBit(1); |
| 1020 | T55xxWriteBit(1); //Page 1 |
| 1021 | |
| 1022 | // Turn field on to read the response |
| 1023 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 1024 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 1025 | |
| 1026 | // Now do the acquisition |
| 1027 | i = 0; |
| 1028 | for(;;) { |
| 1029 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { |
| 1030 | AT91C_BASE_SSC->SSC_THR = 0x43; |
| 1031 | } |
| 1032 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { |
| 1033 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; |
| 1034 | i++; |
| 1035 | if (i >= m) break; |
| 1036 | } |
| 1037 | } |
| 1038 | |
| 1039 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off |
| 1040 | LED_D_OFF(); |
| 1041 | DbpString("DONE!"); |
| 1042 | } |
| 1043 | |
| 1044 | /*-------------- Cloning routines -----------*/ |
| 1045 | // Copy HID id to card and setup block 0 config |
| 1046 | void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) |
| 1047 | { |
| 1048 | int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format |
| 1049 | int last_block = 0; |
| 1050 | |
| 1051 | if (longFMT){ |
| 1052 | // Ensure no more than 84 bits supplied |
| 1053 | if (hi2>0xFFFFF) { |
| 1054 | DbpString("Tags can only have 84 bits."); |
| 1055 | return; |
| 1056 | } |
| 1057 | // Build the 6 data blocks for supplied 84bit ID |
| 1058 | last_block = 6; |
| 1059 | data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded) |
| 1060 | for (int i=0;i<4;i++) { |
| 1061 | if (hi2 & (1<<(19-i))) |
| 1062 | data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10 |
| 1063 | else |
| 1064 | data1 |= (1<<((3-i)*2)); // 0 -> 01 |
| 1065 | } |
| 1066 | |
| 1067 | data2 = 0; |
| 1068 | for (int i=0;i<16;i++) { |
| 1069 | if (hi2 & (1<<(15-i))) |
| 1070 | data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 |
| 1071 | else |
| 1072 | data2 |= (1<<((15-i)*2)); // 0 -> 01 |
| 1073 | } |
| 1074 | |
| 1075 | data3 = 0; |
| 1076 | for (int i=0;i<16;i++) { |
| 1077 | if (hi & (1<<(31-i))) |
| 1078 | data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 |
| 1079 | else |
| 1080 | data3 |= (1<<((15-i)*2)); // 0 -> 01 |
| 1081 | } |
| 1082 | |
| 1083 | data4 = 0; |
| 1084 | for (int i=0;i<16;i++) { |
| 1085 | if (hi & (1<<(15-i))) |
| 1086 | data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10 |
| 1087 | else |
| 1088 | data4 |= (1<<((15-i)*2)); // 0 -> 01 |
| 1089 | } |
| 1090 | |
| 1091 | data5 = 0; |
| 1092 | for (int i=0;i<16;i++) { |
| 1093 | if (lo & (1<<(31-i))) |
| 1094 | data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10 |
| 1095 | else |
| 1096 | data5 |= (1<<((15-i)*2)); // 0 -> 01 |
| 1097 | } |
| 1098 | |
| 1099 | data6 = 0; |
| 1100 | for (int i=0;i<16;i++) { |
| 1101 | if (lo & (1<<(15-i))) |
| 1102 | data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10 |
| 1103 | else |
| 1104 | data6 |= (1<<((15-i)*2)); // 0 -> 01 |
| 1105 | } |
| 1106 | } |
| 1107 | else { |
| 1108 | // Ensure no more than 44 bits supplied |
| 1109 | if (hi>0xFFF) { |
| 1110 | DbpString("Tags can only have 44 bits."); |
| 1111 | return; |
| 1112 | } |
| 1113 | |
| 1114 | // Build the 3 data blocks for supplied 44bit ID |
| 1115 | last_block = 3; |
| 1116 | |
| 1117 | data1 = 0x1D000000; // load preamble |
| 1118 | |
| 1119 | for (int i=0;i<12;i++) { |
| 1120 | if (hi & (1<<(11-i))) |
| 1121 | data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10 |
| 1122 | else |
| 1123 | data1 |= (1<<((11-i)*2)); // 0 -> 01 |
| 1124 | } |
| 1125 | |
| 1126 | data2 = 0; |
| 1127 | for (int i=0;i<16;i++) { |
| 1128 | if (lo & (1<<(31-i))) |
| 1129 | data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10 |
| 1130 | else |
| 1131 | data2 |= (1<<((15-i)*2)); // 0 -> 01 |
| 1132 | } |
| 1133 | |
| 1134 | data3 = 0; |
| 1135 | for (int i=0;i<16;i++) { |
| 1136 | if (lo & (1<<(15-i))) |
| 1137 | data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10 |
| 1138 | else |
| 1139 | data3 |= (1<<((15-i)*2)); // 0 -> 01 |
| 1140 | } |
| 1141 | } |
| 1142 | |
| 1143 | LED_D_ON(); |
| 1144 | // Program the data blocks for supplied ID |
| 1145 | // and the block 0 for HID format |
| 1146 | T55xxWriteBlock(data1,1,0,0); |
| 1147 | T55xxWriteBlock(data2,2,0,0); |
| 1148 | T55xxWriteBlock(data3,3,0,0); |
| 1149 | |
| 1150 | if (longFMT) { // if long format there are 6 blocks |
| 1151 | T55xxWriteBlock(data4,4,0,0); |
| 1152 | T55xxWriteBlock(data5,5,0,0); |
| 1153 | T55xxWriteBlock(data6,6,0,0); |
| 1154 | } |
| 1155 | |
| 1156 | // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long) |
| 1157 | T55xxWriteBlock(T55x7_BITRATE_RF_50 | |
| 1158 | T55x7_MODULATION_FSK2a | |
| 1159 | last_block << T55x7_MAXBLOCK_SHIFT, |
| 1160 | 0,0,0); |
| 1161 | |
| 1162 | LED_D_OFF(); |
| 1163 | |
| 1164 | DbpString("DONE!"); |
| 1165 | } |
| 1166 | |
| 1167 | // Define 9bit header for EM410x tags |
| 1168 | #define EM410X_HEADER 0x1FF |
| 1169 | #define EM410X_ID_LENGTH 40 |
| 1170 | |
| 1171 | void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) |
| 1172 | { |
| 1173 | int i, id_bit; |
| 1174 | uint64_t id = EM410X_HEADER; |
| 1175 | uint64_t rev_id = 0; // reversed ID |
| 1176 | int c_parity[4]; // column parity |
| 1177 | int r_parity = 0; // row parity |
| 1178 | uint32_t clock = 0; |
| 1179 | |
| 1180 | // Reverse ID bits given as parameter (for simpler operations) |
| 1181 | for (i = 0; i < EM410X_ID_LENGTH; ++i) { |
| 1182 | if (i < 32) { |
| 1183 | rev_id = (rev_id << 1) | (id_lo & 1); |
| 1184 | id_lo >>= 1; |
| 1185 | } else { |
| 1186 | rev_id = (rev_id << 1) | (id_hi & 1); |
| 1187 | id_hi >>= 1; |
| 1188 | } |
| 1189 | } |
| 1190 | |
| 1191 | for (i = 0; i < EM410X_ID_LENGTH; ++i) { |
| 1192 | id_bit = rev_id & 1; |
| 1193 | |
| 1194 | if (i % 4 == 0) { |
| 1195 | // Don't write row parity bit at start of parsing |
| 1196 | if (i) |
| 1197 | id = (id << 1) | r_parity; |
| 1198 | // Start counting parity for new row |
| 1199 | r_parity = id_bit; |
| 1200 | } else { |
| 1201 | // Count row parity |
| 1202 | r_parity ^= id_bit; |
| 1203 | } |
| 1204 | |
| 1205 | // First elements in column? |
| 1206 | if (i < 4) |
| 1207 | // Fill out first elements |
| 1208 | c_parity[i] = id_bit; |
| 1209 | else |
| 1210 | // Count column parity |
| 1211 | c_parity[i % 4] ^= id_bit; |
| 1212 | |
| 1213 | // Insert ID bit |
| 1214 | id = (id << 1) | id_bit; |
| 1215 | rev_id >>= 1; |
| 1216 | } |
| 1217 | |
| 1218 | // Insert parity bit of last row |
| 1219 | id = (id << 1) | r_parity; |
| 1220 | |
| 1221 | // Fill out column parity at the end of tag |
| 1222 | for (i = 0; i < 4; ++i) |
| 1223 | id = (id << 1) | c_parity[i]; |
| 1224 | |
| 1225 | // Add stop bit |
| 1226 | id <<= 1; |
| 1227 | |
| 1228 | Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555"); |
| 1229 | LED_D_ON(); |
| 1230 | |
| 1231 | // Write EM410x ID |
| 1232 | T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0); |
| 1233 | T55xxWriteBlock((uint32_t)id, 2, 0, 0); |
| 1234 | |
| 1235 | // Config for EM410x (RF/64, Manchester, Maxblock=2) |
| 1236 | if (card) { |
| 1237 | // Clock rate is stored in bits 8-15 of the card value |
| 1238 | clock = (card & 0xFF00) >> 8; |
| 1239 | Dbprintf("Clock rate: %d", clock); |
| 1240 | switch (clock) |
| 1241 | { |
| 1242 | case 32: |
| 1243 | clock = T55x7_BITRATE_RF_32; |
| 1244 | break; |
| 1245 | case 16: |
| 1246 | clock = T55x7_BITRATE_RF_16; |
| 1247 | break; |
| 1248 | case 0: |
| 1249 | // A value of 0 is assumed to be 64 for backwards-compatibility |
| 1250 | // Fall through... |
| 1251 | case 64: |
| 1252 | clock = T55x7_BITRATE_RF_64; |
| 1253 | break; |
| 1254 | default: |
| 1255 | Dbprintf("Invalid clock rate: %d", clock); |
| 1256 | return; |
| 1257 | } |
| 1258 | |
| 1259 | // Writing configuration for T55x7 tag |
| 1260 | T55xxWriteBlock(clock | |
| 1261 | T55x7_MODULATION_MANCHESTER | |
| 1262 | 2 << T55x7_MAXBLOCK_SHIFT, |
| 1263 | 0, 0, 0); |
| 1264 | } |
| 1265 | else |
| 1266 | // Writing configuration for T5555(Q5) tag |
| 1267 | T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT | |
| 1268 | T5555_MODULATION_MANCHESTER | |
| 1269 | 2 << T5555_MAXBLOCK_SHIFT, |
| 1270 | 0, 0, 0); |
| 1271 | |
| 1272 | LED_D_OFF(); |
| 1273 | Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555", |
| 1274 | (uint32_t)(id >> 32), (uint32_t)id); |
| 1275 | } |
| 1276 | |
| 1277 | // Clone Indala 64-bit tag by UID to T55x7 |
| 1278 | void CopyIndala64toT55x7(int hi, int lo) |
| 1279 | { |
| 1280 | |
| 1281 | //Program the 2 data blocks for supplied 64bit UID |
| 1282 | // and the block 0 for Indala64 format |
| 1283 | T55xxWriteBlock(hi,1,0,0); |
| 1284 | T55xxWriteBlock(lo,2,0,0); |
| 1285 | //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2) |
| 1286 | T55xxWriteBlock(T55x7_BITRATE_RF_32 | |
| 1287 | T55x7_MODULATION_PSK1 | |
| 1288 | 2 << T55x7_MAXBLOCK_SHIFT, |
| 1289 | 0, 0, 0); |
| 1290 | //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data) |
| 1291 | // T5567WriteBlock(0x603E1042,0); |
| 1292 | |
| 1293 | DbpString("DONE!"); |
| 1294 | |
| 1295 | } |
| 1296 | |
| 1297 | void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7) |
| 1298 | { |
| 1299 | |
| 1300 | //Program the 7 data blocks for supplied 224bit UID |
| 1301 | // and the block 0 for Indala224 format |
| 1302 | T55xxWriteBlock(uid1,1,0,0); |
| 1303 | T55xxWriteBlock(uid2,2,0,0); |
| 1304 | T55xxWriteBlock(uid3,3,0,0); |
| 1305 | T55xxWriteBlock(uid4,4,0,0); |
| 1306 | T55xxWriteBlock(uid5,5,0,0); |
| 1307 | T55xxWriteBlock(uid6,6,0,0); |
| 1308 | T55xxWriteBlock(uid7,7,0,0); |
| 1309 | //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7) |
| 1310 | T55xxWriteBlock(T55x7_BITRATE_RF_32 | |
| 1311 | T55x7_MODULATION_PSK1 | |
| 1312 | 7 << T55x7_MAXBLOCK_SHIFT, |
| 1313 | 0,0,0); |
| 1314 | //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data) |
| 1315 | // T5567WriteBlock(0x603E10E2,0); |
| 1316 | |
| 1317 | DbpString("DONE!"); |
| 1318 | |
| 1319 | } |
| 1320 | |
| 1321 | |
| 1322 | #define abs(x) ( ((x)<0) ? -(x) : (x) ) |
| 1323 | #define max(x,y) ( x<y ? y:x) |
| 1324 | |
| 1325 | int DemodPCF7931(uint8_t **outBlocks) { |
| 1326 | uint8_t BitStream[256]; |
| 1327 | uint8_t Blocks[8][16]; |
| 1328 | uint8_t *GraphBuffer = (uint8_t *)BigBuf; |
| 1329 | int GraphTraceLen = sizeof(BigBuf); |
| 1330 | int i, j, lastval, bitidx, half_switch; |
| 1331 | int clock = 64; |
| 1332 | int tolerance = clock / 8; |
| 1333 | int pmc, block_done; |
| 1334 | int lc, warnings = 0; |
| 1335 | int num_blocks = 0; |
| 1336 | int lmin=128, lmax=128; |
| 1337 | uint8_t dir; |
| 1338 | |
| 1339 | AcquireRawAdcSamples125k(0); |
| 1340 | |
| 1341 | lmin = 64; |
| 1342 | lmax = 192; |
| 1343 | |
| 1344 | i = 2; |
| 1345 | |
| 1346 | /* Find first local max/min */ |
| 1347 | if(GraphBuffer[1] > GraphBuffer[0]) { |
| 1348 | while(i < GraphTraceLen) { |
| 1349 | if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax) |
| 1350 | break; |
| 1351 | i++; |
| 1352 | } |
| 1353 | dir = 0; |
| 1354 | } |
| 1355 | else { |
| 1356 | while(i < GraphTraceLen) { |
| 1357 | if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin) |
| 1358 | break; |
| 1359 | i++; |
| 1360 | } |
| 1361 | dir = 1; |
| 1362 | } |
| 1363 | |
| 1364 | lastval = i++; |
| 1365 | half_switch = 0; |
| 1366 | pmc = 0; |
| 1367 | block_done = 0; |
| 1368 | |
| 1369 | for (bitidx = 0; i < GraphTraceLen; i++) |
| 1370 | { |
| 1371 | if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin)) |
| 1372 | { |
| 1373 | lc = i - lastval; |
| 1374 | lastval = i; |
| 1375 | |
| 1376 | // Switch depending on lc length: |
| 1377 | // Tolerance is 1/8 of clock rate (arbitrary) |
| 1378 | if (abs(lc-clock/4) < tolerance) { |
| 1379 | // 16T0 |
| 1380 | if((i - pmc) == lc) { /* 16T0 was previous one */ |
| 1381 | /* It's a PMC ! */ |
| 1382 | i += (128+127+16+32+33+16)-1; |
| 1383 | lastval = i; |
| 1384 | pmc = 0; |
| 1385 | block_done = 1; |
| 1386 | } |
| 1387 | else { |
| 1388 | pmc = i; |
| 1389 | } |
| 1390 | } else if (abs(lc-clock/2) < tolerance) { |
| 1391 | // 32TO |
| 1392 | if((i - pmc) == lc) { /* 16T0 was previous one */ |
| 1393 | /* It's a PMC ! */ |
| 1394 | i += (128+127+16+32+33)-1; |
| 1395 | lastval = i; |
| 1396 | pmc = 0; |
| 1397 | block_done = 1; |
| 1398 | } |
| 1399 | else if(half_switch == 1) { |
| 1400 | BitStream[bitidx++] = 0; |
| 1401 | half_switch = 0; |
| 1402 | } |
| 1403 | else |
| 1404 | half_switch++; |
| 1405 | } else if (abs(lc-clock) < tolerance) { |
| 1406 | // 64TO |
| 1407 | BitStream[bitidx++] = 1; |
| 1408 | } else { |
| 1409 | // Error |
| 1410 | warnings++; |
| 1411 | if (warnings > 10) |
| 1412 | { |
| 1413 | Dbprintf("Error: too many detection errors, aborting."); |
| 1414 | return 0; |
| 1415 | } |
| 1416 | } |
| 1417 | |
| 1418 | if(block_done == 1) { |
| 1419 | if(bitidx == 128) { |
| 1420 | for(j=0; j<16; j++) { |
| 1421 | Blocks[num_blocks][j] = 128*BitStream[j*8+7]+ |
| 1422 | 64*BitStream[j*8+6]+ |
| 1423 | 32*BitStream[j*8+5]+ |
| 1424 | 16*BitStream[j*8+4]+ |
| 1425 | 8*BitStream[j*8+3]+ |
| 1426 | 4*BitStream[j*8+2]+ |
| 1427 | 2*BitStream[j*8+1]+ |
| 1428 | BitStream[j*8]; |
| 1429 | } |
| 1430 | num_blocks++; |
| 1431 | } |
| 1432 | bitidx = 0; |
| 1433 | block_done = 0; |
| 1434 | half_switch = 0; |
| 1435 | } |
| 1436 | if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0; |
| 1437 | else dir = 1; |
| 1438 | } |
| 1439 | if(bitidx==255) |
| 1440 | bitidx=0; |
| 1441 | warnings = 0; |
| 1442 | if(num_blocks == 4) break; |
| 1443 | } |
| 1444 | memcpy(outBlocks, Blocks, 16*num_blocks); |
| 1445 | return num_blocks; |
| 1446 | } |
| 1447 | |
| 1448 | int IsBlock0PCF7931(uint8_t *Block) { |
| 1449 | // Assume RFU means 0 :) |
| 1450 | if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled |
| 1451 | return 1; |
| 1452 | if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ? |
| 1453 | return 1; |
| 1454 | return 0; |
| 1455 | } |
| 1456 | |
| 1457 | int IsBlock1PCF7931(uint8_t *Block) { |
| 1458 | // Assume RFU means 0 :) |
| 1459 | if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0) |
| 1460 | if((Block[14] & 0x7f) <= 9 && Block[15] <= 9) |
| 1461 | return 1; |
| 1462 | |
| 1463 | return 0; |
| 1464 | } |
| 1465 | |
| 1466 | #define ALLOC 16 |
| 1467 | |
| 1468 | void ReadPCF7931() { |
| 1469 | uint8_t Blocks[8][17]; |
| 1470 | uint8_t tmpBlocks[4][16]; |
| 1471 | int i, j, ind, ind2, n; |
| 1472 | int num_blocks = 0; |
| 1473 | int max_blocks = 8; |
| 1474 | int ident = 0; |
| 1475 | int error = 0; |
| 1476 | int tries = 0; |
| 1477 | |
| 1478 | memset(Blocks, 0, 8*17*sizeof(uint8_t)); |
| 1479 | |
| 1480 | do { |
| 1481 | memset(tmpBlocks, 0, 4*16*sizeof(uint8_t)); |
| 1482 | n = DemodPCF7931((uint8_t**)tmpBlocks); |
| 1483 | if(!n) |
| 1484 | error++; |
| 1485 | if(error==10 && num_blocks == 0) { |
| 1486 | Dbprintf("Error, no tag or bad tag"); |
| 1487 | return; |
| 1488 | } |
| 1489 | else if (tries==20 || error==10) { |
| 1490 | Dbprintf("Error reading the tag"); |
| 1491 | Dbprintf("Here is the partial content"); |
| 1492 | goto end; |
| 1493 | } |
| 1494 | |
| 1495 | for(i=0; i<n; i++) |
| 1496 | Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", |
| 1497 | tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7], |
| 1498 | tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]); |
| 1499 | if(!ident) { |
| 1500 | for(i=0; i<n; i++) { |
| 1501 | if(IsBlock0PCF7931(tmpBlocks[i])) { |
| 1502 | // Found block 0 ? |
| 1503 | if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) { |
| 1504 | // Found block 1! |
| 1505 | // \o/ |
| 1506 | ident = 1; |
| 1507 | memcpy(Blocks[0], tmpBlocks[i], 16); |
| 1508 | Blocks[0][ALLOC] = 1; |
| 1509 | memcpy(Blocks[1], tmpBlocks[i+1], 16); |
| 1510 | Blocks[1][ALLOC] = 1; |
| 1511 | max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1; |
| 1512 | // Debug print |
| 1513 | Dbprintf("(dbg) Max blocks: %d", max_blocks); |
| 1514 | num_blocks = 2; |
| 1515 | // Handle following blocks |
| 1516 | for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) { |
| 1517 | if(j==n) j=0; |
| 1518 | if(j==i) break; |
| 1519 | memcpy(Blocks[ind2], tmpBlocks[j], 16); |
| 1520 | Blocks[ind2][ALLOC] = 1; |
| 1521 | } |
| 1522 | break; |
| 1523 | } |
| 1524 | } |
| 1525 | } |
| 1526 | } |
| 1527 | else { |
| 1528 | for(i=0; i<n; i++) { // Look for identical block in known blocks |
| 1529 | if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00 |
| 1530 | for(j=0; j<max_blocks; j++) { |
| 1531 | if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) { |
| 1532 | // Found an identical block |
| 1533 | for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) { |
| 1534 | if(ind2 < 0) |
| 1535 | ind2 = max_blocks; |
| 1536 | if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found |
| 1537 | // Dbprintf("Tmp %d -> Block %d", ind, ind2); |
| 1538 | memcpy(Blocks[ind2], tmpBlocks[ind], 16); |
| 1539 | Blocks[ind2][ALLOC] = 1; |
| 1540 | num_blocks++; |
| 1541 | if(num_blocks == max_blocks) goto end; |
| 1542 | } |
| 1543 | } |
| 1544 | for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) { |
| 1545 | if(ind2 > max_blocks) |
| 1546 | ind2 = 0; |
| 1547 | if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found |
| 1548 | // Dbprintf("Tmp %d -> Block %d", ind, ind2); |
| 1549 | memcpy(Blocks[ind2], tmpBlocks[ind], 16); |
| 1550 | Blocks[ind2][ALLOC] = 1; |
| 1551 | num_blocks++; |
| 1552 | if(num_blocks == max_blocks) goto end; |
| 1553 | } |
| 1554 | } |
| 1555 | } |
| 1556 | } |
| 1557 | } |
| 1558 | } |
| 1559 | } |
| 1560 | tries++; |
| 1561 | if (BUTTON_PRESS()) return; |
| 1562 | } while (num_blocks != max_blocks); |
| 1563 | end: |
| 1564 | Dbprintf("-----------------------------------------"); |
| 1565 | Dbprintf("Memory content:"); |
| 1566 | Dbprintf("-----------------------------------------"); |
| 1567 | for(i=0; i<max_blocks; i++) { |
| 1568 | if(Blocks[i][ALLOC]==1) |
| 1569 | Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", |
| 1570 | Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7], |
| 1571 | Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]); |
| 1572 | else |
| 1573 | Dbprintf("<missing block %d>", i); |
| 1574 | } |
| 1575 | Dbprintf("-----------------------------------------"); |
| 1576 | |
| 1577 | return ; |
| 1578 | } |
| 1579 | |
| 1580 | |
| 1581 | //----------------------------------- |
| 1582 | // EM4469 / EM4305 routines |
| 1583 | //----------------------------------- |
| 1584 | #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored |
| 1585 | #define FWD_CMD_WRITE 0xA |
| 1586 | #define FWD_CMD_READ 0x9 |
| 1587 | #define FWD_CMD_DISABLE 0x5 |
| 1588 | |
| 1589 | |
| 1590 | uint8_t forwardLink_data[64]; //array of forwarded bits |
| 1591 | uint8_t * forward_ptr; //ptr for forward message preparation |
| 1592 | uint8_t fwd_bit_sz; //forwardlink bit counter |
| 1593 | uint8_t * fwd_write_ptr; //forwardlink bit pointer |
| 1594 | |
| 1595 | //==================================================================== |
| 1596 | // prepares command bits |
| 1597 | // see EM4469 spec |
| 1598 | //==================================================================== |
| 1599 | //-------------------------------------------------------------------- |
| 1600 | uint8_t Prepare_Cmd( uint8_t cmd ) { |
| 1601 | //-------------------------------------------------------------------- |
| 1602 | |
| 1603 | *forward_ptr++ = 0; //start bit |
| 1604 | *forward_ptr++ = 0; //second pause for 4050 code |
| 1605 | |
| 1606 | *forward_ptr++ = cmd; |
| 1607 | cmd >>= 1; |
| 1608 | *forward_ptr++ = cmd; |
| 1609 | cmd >>= 1; |
| 1610 | *forward_ptr++ = cmd; |
| 1611 | cmd >>= 1; |
| 1612 | *forward_ptr++ = cmd; |
| 1613 | |
| 1614 | return 6; //return number of emited bits |
| 1615 | } |
| 1616 | |
| 1617 | //==================================================================== |
| 1618 | // prepares address bits |
| 1619 | // see EM4469 spec |
| 1620 | //==================================================================== |
| 1621 | |
| 1622 | //-------------------------------------------------------------------- |
| 1623 | uint8_t Prepare_Addr( uint8_t addr ) { |
| 1624 | //-------------------------------------------------------------------- |
| 1625 | |
| 1626 | register uint8_t line_parity; |
| 1627 | |
| 1628 | uint8_t i; |
| 1629 | line_parity = 0; |
| 1630 | for(i=0;i<6;i++) { |
| 1631 | *forward_ptr++ = addr; |
| 1632 | line_parity ^= addr; |
| 1633 | addr >>= 1; |
| 1634 | } |
| 1635 | |
| 1636 | *forward_ptr++ = (line_parity & 1); |
| 1637 | |
| 1638 | return 7; //return number of emited bits |
| 1639 | } |
| 1640 | |
| 1641 | //==================================================================== |
| 1642 | // prepares data bits intreleaved with parity bits |
| 1643 | // see EM4469 spec |
| 1644 | //==================================================================== |
| 1645 | |
| 1646 | //-------------------------------------------------------------------- |
| 1647 | uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) { |
| 1648 | //-------------------------------------------------------------------- |
| 1649 | |
| 1650 | register uint8_t line_parity; |
| 1651 | register uint8_t column_parity; |
| 1652 | register uint8_t i, j; |
| 1653 | register uint16_t data; |
| 1654 | |
| 1655 | data = data_low; |
| 1656 | column_parity = 0; |
| 1657 | |
| 1658 | for(i=0; i<4; i++) { |
| 1659 | line_parity = 0; |
| 1660 | for(j=0; j<8; j++) { |
| 1661 | line_parity ^= data; |
| 1662 | column_parity ^= (data & 1) << j; |
| 1663 | *forward_ptr++ = data; |
| 1664 | data >>= 1; |
| 1665 | } |
| 1666 | *forward_ptr++ = line_parity; |
| 1667 | if(i == 1) |
| 1668 | data = data_hi; |
| 1669 | } |
| 1670 | |
| 1671 | for(j=0; j<8; j++) { |
| 1672 | *forward_ptr++ = column_parity; |
| 1673 | column_parity >>= 1; |
| 1674 | } |
| 1675 | *forward_ptr = 0; |
| 1676 | |
| 1677 | return 45; //return number of emited bits |
| 1678 | } |
| 1679 | |
| 1680 | //==================================================================== |
| 1681 | // Forward Link send function |
| 1682 | // Requires: forwarLink_data filled with valid bits (1 bit per byte) |
| 1683 | // fwd_bit_count set with number of bits to be sent |
| 1684 | //==================================================================== |
| 1685 | void SendForward(uint8_t fwd_bit_count) { |
| 1686 | |
| 1687 | fwd_write_ptr = forwardLink_data; |
| 1688 | fwd_bit_sz = fwd_bit_count; |
| 1689 | |
| 1690 | LED_D_ON(); |
| 1691 | |
| 1692 | //Field on |
| 1693 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 1694 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER); |
| 1695 | |
| 1696 | // Give it a bit of time for the resonant antenna to settle. |
| 1697 | // And for the tag to fully power up |
| 1698 | SpinDelay(150); |
| 1699 | |
| 1700 | // force 1st mod pulse (start gap must be longer for 4305) |
| 1701 | fwd_bit_sz--; //prepare next bit modulation |
| 1702 | fwd_write_ptr++; |
| 1703 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off |
| 1704 | SpinDelayUs(55*8); //55 cycles off (8us each)for 4305 |
| 1705 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 1706 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on |
| 1707 | SpinDelayUs(16*8); //16 cycles on (8us each) |
| 1708 | |
| 1709 | // now start writting |
| 1710 | while(fwd_bit_sz-- > 0) { //prepare next bit modulation |
| 1711 | if(((*fwd_write_ptr++) & 1) == 1) |
| 1712 | SpinDelayUs(32*8); //32 cycles at 125Khz (8us each) |
| 1713 | else { |
| 1714 | //These timings work for 4469/4269/4305 (with the 55*8 above) |
| 1715 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off |
| 1716 | SpinDelayUs(23*8); //16-4 cycles off (8us each) |
| 1717 | FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz |
| 1718 | FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on |
| 1719 | SpinDelayUs(9*8); //16 cycles on (8us each) |
| 1720 | } |
| 1721 | } |
| 1722 | } |
| 1723 | |
| 1724 | void EM4xLogin(uint32_t Password) { |
| 1725 | |
| 1726 | uint8_t fwd_bit_count; |
| 1727 | |
| 1728 | forward_ptr = forwardLink_data; |
| 1729 | fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN ); |
| 1730 | fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 ); |
| 1731 | |
| 1732 | SendForward(fwd_bit_count); |
| 1733 | |
| 1734 | //Wait for command to complete |
| 1735 | SpinDelay(20); |
| 1736 | |
| 1737 | } |
| 1738 | |
| 1739 | void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { |
| 1740 | |
| 1741 | uint8_t fwd_bit_count; |
| 1742 | uint8_t *dest = (uint8_t *)BigBuf; |
| 1743 | int m=0, i=0; |
| 1744 | |
| 1745 | //If password mode do login |
| 1746 | if (PwdMode == 1) EM4xLogin(Pwd); |
| 1747 | |
| 1748 | forward_ptr = forwardLink_data; |
| 1749 | fwd_bit_count = Prepare_Cmd( FWD_CMD_READ ); |
| 1750 | fwd_bit_count += Prepare_Addr( Address ); |
| 1751 | |
| 1752 | m = sizeof(BigBuf); |
| 1753 | // Clear destination buffer before sending the command |
| 1754 | memset(dest, 128, m); |
| 1755 | // Connect the A/D to the peak-detected low-frequency path. |
| 1756 | SetAdcMuxFor(GPIO_MUXSEL_LOPKD); |
| 1757 | // Now set up the SSC to get the ADC samples that are now streaming at us. |
| 1758 | FpgaSetupSsc(); |
| 1759 | |
| 1760 | SendForward(fwd_bit_count); |
| 1761 | |
| 1762 | // Now do the acquisition |
| 1763 | i = 0; |
| 1764 | for(;;) { |
| 1765 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) { |
| 1766 | AT91C_BASE_SSC->SSC_THR = 0x43; |
| 1767 | } |
| 1768 | if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) { |
| 1769 | dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; |
| 1770 | i++; |
| 1771 | if (i >= m) break; |
| 1772 | } |
| 1773 | } |
| 1774 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off |
| 1775 | LED_D_OFF(); |
| 1776 | } |
| 1777 | |
| 1778 | void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) { |
| 1779 | |
| 1780 | uint8_t fwd_bit_count; |
| 1781 | |
| 1782 | //If password mode do login |
| 1783 | if (PwdMode == 1) EM4xLogin(Pwd); |
| 1784 | |
| 1785 | forward_ptr = forwardLink_data; |
| 1786 | fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE ); |
| 1787 | fwd_bit_count += Prepare_Addr( Address ); |
| 1788 | fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 ); |
| 1789 | |
| 1790 | SendForward(fwd_bit_count); |
| 1791 | |
| 1792 | //Wait for write to complete |
| 1793 | SpinDelay(20); |
| 1794 | FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off |
| 1795 | LED_D_OFF(); |
| 1796 | } |