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1//-----------------------------------------------------------------------------
2// Jonathan Westhues, April 2006
3// iZsh <izsh at fail0verflow.com>, 2014
4//
5// This code is licensed to you under the terms of the GNU GPL, version 2 or,
6// at your option, any later version. See the LICENSE.txt file for the text of
7// the license.
8//-----------------------------------------------------------------------------
9// Routines to load the FPGA image, and then to configure the FPGA's major
10// mode once it is configured.
11//-----------------------------------------------------------------------------
12
13#include <stdint.h>
14#include <stddef.h>
15#include <stdbool.h>
16#include "fpgaloader.h"
17#include "proxmark3.h"
18#include "util.h"
19#include "string.h"
20#include "BigBuf.h"
21#include "zlib.h"
22
23extern void Dbprintf(const char *fmt, ...);
24
25// remember which version of the bitstream we have already downloaded to the FPGA
26static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
27
28// this is where the bitstreams are located in memory:
29extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
30
31static uint8_t *fpga_image_ptr = NULL;
32static uint32_t uncompressed_bytes_cnt;
33
34static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
35#define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(_bitparse_fixed_header)
36#define OUTPUT_BUFFER_LEN 80
37#define FPGA_INTERLEAVE_SIZE 288
38
39//-----------------------------------------------------------------------------
40// Set up the Serial Peripheral Interface as master
41// Used to write the FPGA config word
42// May also be used to write to other SPI attached devices like an LCD
43//-----------------------------------------------------------------------------
44void SetupSpi(int mode)
45{
46 // PA10 -> SPI_NCS2 chip select (LCD)
47 // PA11 -> SPI_NCS0 chip select (FPGA)
48 // PA12 -> SPI_MISO Master-In Slave-Out
49 // PA13 -> SPI_MOSI Master-Out Slave-In
50 // PA14 -> SPI_SPCK Serial Clock
51
52 // Disable PIO control of the following pins, allows use by the SPI peripheral
53 AT91C_BASE_PIOA->PIO_PDR =
54 GPIO_NCS0 |
55 GPIO_NCS2 |
56 GPIO_MISO |
57 GPIO_MOSI |
58 GPIO_SPCK;
59
60 AT91C_BASE_PIOA->PIO_ASR =
61 GPIO_NCS0 |
62 GPIO_MISO |
63 GPIO_MOSI |
64 GPIO_SPCK;
65
66 AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
67
68 //enable the SPI Peripheral clock
69 AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
70 // Enable SPI
71 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
72
73 switch (mode) {
74 case SPI_FPGA_MODE:
75 AT91C_BASE_SPI->SPI_MR =
76 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
77 (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
78 ( 0 << 7) | // Local Loopback Disabled
79 ( 1 << 4) | // Mode Fault Detection disabled
80 ( 0 << 2) | // Chip selects connected directly to peripheral
81 ( 0 << 1) | // Fixed Peripheral Select
82 ( 1 << 0); // Master Mode
83 AT91C_BASE_SPI->SPI_CSR[0] =
84 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
85 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
86 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
87 ( 8 << 4) | // Bits per Transfer (16 bits)
88 ( 0 << 3) | // Chip Select inactive after transfer
89 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
90 ( 0 << 0); // Clock Polarity inactive state is logic 0
91 break;
92 case SPI_LCD_MODE:
93 AT91C_BASE_SPI->SPI_MR =
94 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
95 (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
96 ( 0 << 7) | // Local Loopback Disabled
97 ( 1 << 4) | // Mode Fault Detection disabled
98 ( 0 << 2) | // Chip selects connected directly to peripheral
99 ( 0 << 1) | // Fixed Peripheral Select
100 ( 1 << 0); // Master Mode
101 AT91C_BASE_SPI->SPI_CSR[2] =
102 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
103 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
104 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
105 ( 1 << 4) | // Bits per Transfer (9 bits)
106 ( 0 << 3) | // Chip Select inactive after transfer
107 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
108 ( 0 << 0); // Clock Polarity inactive state is logic 0
109 break;
110 default: // Disable SPI
111 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
112 break;
113 }
114}
115
116//-----------------------------------------------------------------------------
117// Set up the synchronous serial port, with the one set of options that we
118// always use when we are talking to the FPGA. Both RX and TX are enabled.
119//-----------------------------------------------------------------------------
120void FpgaSetupSscExt(uint8_t clearPCER) {
121 // First configure the GPIOs, and get ourselves a clock.
122 AT91C_BASE_PIOA->PIO_ASR =
123 GPIO_SSC_FRAME |
124 GPIO_SSC_DIN |
125 GPIO_SSC_DOUT |
126 GPIO_SSC_CLK;
127 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
128
129 if ( clearPCER )
130 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
131 else
132 AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_SSC);
133
134 // Now set up the SSC proper, starting from a known state.
135 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
136
137 // RX clock comes from TX clock, RX starts when TX starts, data changes
138 // on RX clock rising edge, sampled on falling edge
139 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
140
141 // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
142 // pulse, no output sync
143 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
144
145 // clock comes from TK pin, no clock output, outputs change on falling
146 // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
147 AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
148
149 // tx framing is the same as the rx framing
150 AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
151
152 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
153}
154void FpgaSetupSsc(void) {
155 FpgaSetupSscExt(TRUE);
156}
157//-----------------------------------------------------------------------------
158// Set up DMA to receive samples from the FPGA. We will use the PDC, with
159// a single buffer as a circular buffer (so that we just chain back to
160// ourselves, not to another buffer). The stuff to manipulate those buffers
161// is in apps.h, because it should be inlined, for speed.
162//-----------------------------------------------------------------------------
163bool FpgaSetupSscDma(uint8_t *buf, int len) {
164 if (buf == NULL) return false;
165
166 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
167 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
168 AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
169 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
170 AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
171 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
172 return true;
173}
174
175
176//----------------------------------------------------------------------------
177// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
178// each call.
179//----------------------------------------------------------------------------
180static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
181{
182 if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
183 compressed_fpga_stream->next_out = output_buffer;
184 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
185 fpga_image_ptr = output_buffer;
186 int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
187
188 if (res != Z_OK)
189 Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
190
191 if (res < 0)
192 return res;
193 }
194
195 ++uncompressed_bytes_cnt;
196
197 return *fpga_image_ptr++;
198}
199
200//----------------------------------------------------------------------------
201// Undo the interleaving of several FPGA config files. FPGA config files
202// are combined into one big file:
203// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
204//----------------------------------------------------------------------------
205static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
206{
207 while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
208 // skip undesired data belonging to other bitstream_versions
209 get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
210 }
211
212 return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
213}
214
215
216static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
217{
218 return BigBuf_malloc(items*size);
219}
220
221
222static void fpga_inflate_free(voidpf opaque, voidpf address)
223{
224 // free eventually allocated BigBuf memory
225 BigBuf_free(); BigBuf_Clear_ext(false);
226}
227
228
229//----------------------------------------------------------------------------
230// Initialize decompression of the respective (HF or LF) FPGA stream
231//----------------------------------------------------------------------------
232static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
233{
234 uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
235
236 uncompressed_bytes_cnt = 0;
237
238 // initialize z_stream structure for inflate:
239 compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
240 compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
241 compressed_fpga_stream->next_out = output_buffer;
242 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
243 compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
244 compressed_fpga_stream->zfree = &fpga_inflate_free;
245
246 inflateInit2(compressed_fpga_stream, 0);
247
248 fpga_image_ptr = output_buffer;
249
250 for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++)
251 header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
252
253 // Check for a valid .bit file (starts with _bitparse_fixed_header)
254 if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0)
255 return true;
256
257 return false;
258}
259
260
261static void DownloadFPGA_byte(unsigned char w)
262{
263#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
264 SEND_BIT(7);
265 SEND_BIT(6);
266 SEND_BIT(5);
267 SEND_BIT(4);
268 SEND_BIT(3);
269 SEND_BIT(2);
270 SEND_BIT(1);
271 SEND_BIT(0);
272}
273
274// Download the fpga image starting at current stream position with length FpgaImageLen bytes
275static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
276{
277 int i=0;
278
279 AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
280 AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
281 HIGH(GPIO_FPGA_ON); // ensure everything is powered on
282
283 SpinDelay(50);
284
285 LED_D_ON();
286
287 // These pins are inputs
288 AT91C_BASE_PIOA->PIO_ODR =
289 GPIO_FPGA_NINIT |
290 GPIO_FPGA_DONE;
291 // PIO controls the following pins
292 AT91C_BASE_PIOA->PIO_PER =
293 GPIO_FPGA_NINIT |
294 GPIO_FPGA_DONE;
295 // Enable pull-ups
296 AT91C_BASE_PIOA->PIO_PPUER =
297 GPIO_FPGA_NINIT |
298 GPIO_FPGA_DONE;
299
300 // setup initial logic state
301 HIGH(GPIO_FPGA_NPROGRAM);
302 LOW(GPIO_FPGA_CCLK);
303 LOW(GPIO_FPGA_DIN);
304 // These pins are outputs
305 AT91C_BASE_PIOA->PIO_OER =
306 GPIO_FPGA_NPROGRAM |
307 GPIO_FPGA_CCLK |
308 GPIO_FPGA_DIN;
309
310 // enter FPGA configuration mode
311 LOW(GPIO_FPGA_NPROGRAM);
312 SpinDelay(50);
313 HIGH(GPIO_FPGA_NPROGRAM);
314
315 i=100000;
316 // wait for FPGA ready to accept data signal
317 while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
318 i--;
319 }
320
321 // crude error indicator, leave both red LEDs on and return
322 if (i==0){
323 LED_C_ON();
324 LED_D_ON();
325 return;
326 }
327
328 for(i = 0; i < FpgaImageLen; i++) {
329 int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
330 if (b < 0) {
331 Dbprintf("Error %d during FpgaDownload", b);
332 break;
333 }
334 DownloadFPGA_byte(b);
335 }
336
337 // continue to clock FPGA until ready signal goes high
338 i=100000;
339 while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
340 HIGH(GPIO_FPGA_CCLK);
341 LOW(GPIO_FPGA_CCLK);
342 }
343 // crude error indicator, leave both red LEDs on and return
344 if (i==0){
345 LED_C_ON();
346 LED_D_ON();
347 return;
348 }
349 LED_D_OFF();
350}
351
352
353/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
354 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
355 * After that the format is 1 byte section type (ASCII character), 2 byte length
356 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
357 * length.
358 */
359static int bitparse_find_section(int bitstream_version, char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
360{
361 int result = 0;
362 #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
363 uint16_t numbytes = 0;
364 while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
365 char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
366 numbytes++;
367 unsigned int current_length = 0;
368 if(current_name < 'a' || current_name > 'e') {
369 /* Strange section name, abort */
370 break;
371 }
372 current_length = 0;
373 switch(current_name) {
374 case 'e':
375 /* Four byte length field */
376 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
377 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
378 numbytes += 2;
379 default: /* Fall through, two byte length field */
380 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
381 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
382 numbytes += 2;
383 }
384
385 if(current_name != 'e' && current_length > 255) {
386 /* Maybe a parse error */
387 break;
388 }
389
390 if(current_name == section_name) {
391 /* Found it */
392 *section_length = current_length;
393 result = 1;
394 break;
395 }
396
397 for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
398 get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
399 numbytes++;
400 }
401 }
402
403 return result;
404}
405
406
407//----------------------------------------------------------------------------
408// Check which FPGA image is currently loaded (if any). If necessary
409// decompress and load the correct (HF or LF) image to the FPGA
410//----------------------------------------------------------------------------
411void FpgaDownloadAndGo(int bitstream_version)
412{
413 z_stream compressed_fpga_stream;
414 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
415
416 // check whether or not the bitstream is already loaded
417 if (downloaded_bitstream == bitstream_version)
418 return;
419
420 // make sure that we have enough memory to decompress
421 BigBuf_free(); BigBuf_Clear_ext(false);
422
423 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
424 return;
425 }
426
427 unsigned int bitstream_length;
428 if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
429 DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
430 downloaded_bitstream = bitstream_version;
431 }
432
433 inflateEnd(&compressed_fpga_stream);
434
435 // free eventually allocated BigBuf memory
436 BigBuf_free(); BigBuf_Clear_ext(false);
437}
438
439
440//-----------------------------------------------------------------------------
441// Gather version information from FPGA image. Needs to decompress the begin
442// of the respective (HF or LF) image.
443// Note: decompression makes use of (i.e. overwrites) BigBuf[]. It is therefore
444// advisable to call this only once and store the results for later use.
445//-----------------------------------------------------------------------------
446void FpgaGatherVersion(int bitstream_version, char *dst, int len)
447{
448 unsigned int fpga_info_len;
449 char tempstr[40] = {0x00};
450 z_stream compressed_fpga_stream;
451 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
452
453 dst[0] = '\0';
454
455 // ensure that we can allocate enough memory for decompression:
456 BigBuf_free(); BigBuf_Clear_ext(false);
457
458 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer))
459 return;
460
461 if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
462 for (uint16_t i = 0; i < fpga_info_len; i++) {
463 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
464 if (i < sizeof(tempstr)) {
465 tempstr[i] = c;
466 }
467 }
468 if (!memcmp("fpga_lf", tempstr, 7))
469 strncat(dst, "LF ", len-1);
470 else if (!memcmp("fpga_hf", tempstr, 7))
471 strncat(dst, "HF ", len-1);
472 }
473 strncat(dst, "FPGA image built", len-1);
474 if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
475 strncat(dst, " for ", len-1);
476 for (uint16_t i = 0; i < fpga_info_len; i++) {
477 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
478 if (i < sizeof(tempstr)) {
479 tempstr[i] = c;
480 }
481 }
482 strncat(dst, tempstr, len-1);
483 }
484 if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
485 strncat(dst, " on ", len-1);
486 for (uint16_t i = 0; i < fpga_info_len; i++) {
487 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
488 if (i < sizeof(tempstr)) {
489 tempstr[i] = c;
490 }
491 }
492 strncat(dst, tempstr, len-1);
493 }
494 if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
495 strncat(dst, " at ", len-1);
496 for (uint16_t i = 0; i < fpga_info_len; i++) {
497 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
498 if (i < sizeof(tempstr)) {
499 tempstr[i] = c;
500 }
501 }
502 strncat(dst, tempstr, len-1);
503 }
504
505 strncat(dst, "\n", len-1);
506
507 inflateEnd(&compressed_fpga_stream);
508}
509
510
511//-----------------------------------------------------------------------------
512// Send a 16 bit command/data pair to the FPGA.
513// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
514// where C is the 4 bit command and D is the 12 bit data
515//-----------------------------------------------------------------------------
516void FpgaSendCommand(uint16_t cmd, uint16_t v)
517{
518 SetupSpi(SPI_FPGA_MODE);
519 while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
520 AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
521}
522//-----------------------------------------------------------------------------
523// Write the FPGA setup word (that determines what mode the logic is in, read
524// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
525// avoid changing this function's occurence everywhere in the source code.
526//-----------------------------------------------------------------------------
527void FpgaWriteConfWord(uint8_t v)
528{
529 FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
530}
531
532//-----------------------------------------------------------------------------
533// Set up the CMOS switches that mux the ADC: four switches, independently
534// closable, but should only close one at a time. Not an FPGA thing, but
535// the samples from the ADC always flow through the FPGA.
536//-----------------------------------------------------------------------------
537void SetAdcMuxFor(uint32_t whichGpio)
538{
539 AT91C_BASE_PIOA->PIO_OER =
540 GPIO_MUXSEL_HIPKD |
541 GPIO_MUXSEL_LOPKD |
542 GPIO_MUXSEL_LORAW |
543 GPIO_MUXSEL_HIRAW;
544
545 AT91C_BASE_PIOA->PIO_PER =
546 GPIO_MUXSEL_HIPKD |
547 GPIO_MUXSEL_LOPKD |
548 GPIO_MUXSEL_LORAW |
549 GPIO_MUXSEL_HIRAW;
550
551 LOW(GPIO_MUXSEL_HIPKD);
552 LOW(GPIO_MUXSEL_HIRAW);
553 LOW(GPIO_MUXSEL_LORAW);
554 LOW(GPIO_MUXSEL_LOPKD);
555
556 HIGH(whichGpio);
557}
558
559void Fpga_print_status(void)
560{
561 Dbprintf("Fgpa");
562 if(downloaded_bitstream == FPGA_BITSTREAM_HF) Dbprintf(" mode.............HF");
563 else if(downloaded_bitstream == FPGA_BITSTREAM_LF) Dbprintf(" mode.............LF");
564 else Dbprintf(" mode.............%d", downloaded_bitstream);
565}
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