| 1 | //----------------------------------------------------------------------------- |
| 2 | // The FPGA is responsible for interfacing between the A/D, the coil drivers, |
| 3 | // and the ARM. In the low-frequency modes it passes the data straight |
| 4 | // through, so that the ARM gets raw A/D samples over the SSP. In the high- |
| 5 | // frequency modes, the FPGA might perform some demodulation first, to |
| 6 | // reduce the amount of data that we must send to the ARM. |
| 7 | // |
| 8 | // I am not really an FPGA/ASIC designer, so I am sure that a lot of this |
| 9 | // could be improved. |
| 10 | // |
| 11 | // Jonathan Westhues, March 2006 |
| 12 | // Added ISO14443-A support by Gerhard de Koning Gans, April 2008 |
| 13 | //----------------------------------------------------------------------------- |
| 14 | |
| 15 | `include "lo_read.v" |
| 16 | `include "lo_passthru.v" |
| 17 | `include "lo_edge_detect.v" |
| 18 | `include "hi_read_tx.v" |
| 19 | `include "hi_read_rx_xcorr.v" |
| 20 | `include "hi_simulate.v" |
| 21 | `include "hi_iso14443a.v" |
| 22 | `include "util.v" |
| 23 | |
| 24 | module fpga( |
| 25 | spcki, miso, mosi, ncs, |
| 26 | pck0i, ck_1356meg, ck_1356megb, |
| 27 | pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4, |
| 28 | adc_d, adc_clk, adc_noe, |
| 29 | ssp_frame, ssp_din, ssp_dout, ssp_clk, |
| 30 | cross_hi, cross_lo, |
| 31 | dbg |
| 32 | ); |
| 33 | input spcki, mosi, ncs; |
| 34 | output miso; |
| 35 | input pck0i, ck_1356meg, ck_1356megb; |
| 36 | output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4; |
| 37 | input [7:0] adc_d; |
| 38 | output adc_clk, adc_noe; |
| 39 | input ssp_dout; |
| 40 | output ssp_frame, ssp_din, ssp_clk; |
| 41 | input cross_hi, cross_lo; |
| 42 | output dbg; |
| 43 | |
| 44 | //assign pck0 = pck0i; |
| 45 | IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b( |
| 46 | .O(pck0), |
| 47 | .I(pck0i) |
| 48 | ); |
| 49 | //assign spck = spcki; |
| 50 | IBUFG #(.IOSTANDARD("DEFAULT") ) spckb( |
| 51 | .O(spck), |
| 52 | .I(spcki) |
| 53 | ); |
| 54 | //----------------------------------------------------------------------------- |
| 55 | // The SPI receiver. This sets up the configuration word, which the rest of |
| 56 | // the logic looks at to determine how to connect the A/D and the coil |
| 57 | // drivers (i.e., which section gets it). Also assign some symbolic names |
| 58 | // to the configuration bits, for use below. |
| 59 | //----------------------------------------------------------------------------- |
| 60 | |
| 61 | reg [15:0] shift_reg; |
| 62 | reg [7:0] divisor; |
| 63 | reg [7:0] conf_word; |
| 64 | |
| 65 | // We switch modes between transmitting to the 13.56 MHz tag and receiving |
| 66 | // from it, which means that we must make sure that we can do so without |
| 67 | // glitching, or else we will glitch the transmitted carrier. |
| 68 | always @(posedge ncs) |
| 69 | begin |
| 70 | case(shift_reg[15:12]) |
| 71 | 4'b0001: conf_word <= shift_reg[7:0]; |
| 72 | 4'b0010: divisor <= shift_reg[7:0]; |
| 73 | endcase |
| 74 | end |
| 75 | |
| 76 | always @(posedge spck) |
| 77 | begin |
| 78 | if(~ncs) |
| 79 | begin |
| 80 | shift_reg[15:1] <= shift_reg[14:0]; |
| 81 | shift_reg[0] <= mosi; |
| 82 | end |
| 83 | end |
| 84 | |
| 85 | wire [2:0] major_mode; |
| 86 | assign major_mode = conf_word[7:5]; |
| 87 | |
| 88 | // For the low-frequency configuration: |
| 89 | wire lo_is_125khz; |
| 90 | assign lo_is_125khz = conf_word[3]; |
| 91 | |
| 92 | // For the high-frequency transmit configuration: modulation depth, either |
| 93 | // 100% (just quite driving antenna, steady LOW), or shallower (tri-state |
| 94 | // some fraction of the buffers) |
| 95 | wire hi_read_tx_shallow_modulation; |
| 96 | assign hi_read_tx_shallow_modulation = conf_word[0]; |
| 97 | |
| 98 | // For the high-frequency receive correlator: frequency against which to |
| 99 | // correlate. |
| 100 | wire hi_read_rx_xcorr_848; |
| 101 | assign hi_read_rx_xcorr_848 = conf_word[0]; |
| 102 | // and whether to drive the coil (reader) or just short it (snooper) |
| 103 | wire hi_read_rx_xcorr_snoop; |
| 104 | assign hi_read_rx_xcorr_snoop = conf_word[1]; |
| 105 | |
| 106 | // Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4 |
| 107 | wire hi_read_rx_xcorr_quarter; |
| 108 | assign hi_read_rx_xcorr_quarter = conf_word[2]; |
| 109 | |
| 110 | // For the high-frequency simulated tag: what kind of modulation to use. |
| 111 | wire [2:0] hi_simulate_mod_type; |
| 112 | assign hi_simulate_mod_type = conf_word[2:0]; |
| 113 | |
| 114 | // For the high-frequency simulated tag: what kind of modulation to use. |
| 115 | wire lf_field; |
| 116 | assign lf_field = conf_word[0]; |
| 117 | |
| 118 | //----------------------------------------------------------------------------- |
| 119 | // And then we instantiate the modules corresponding to each of the FPGA's |
| 120 | // major modes, and use muxes to connect the outputs of the active mode to |
| 121 | // the output pins. |
| 122 | //----------------------------------------------------------------------------- |
| 123 | |
| 124 | lo_read lr( |
| 125 | pck0, ck_1356meg, ck_1356megb, |
| 126 | lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4, |
| 127 | adc_d, lr_adc_clk, |
| 128 | lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk, |
| 129 | cross_hi, cross_lo, |
| 130 | lr_dbg, |
| 131 | lo_is_125khz, divisor |
| 132 | ); |
| 133 | |
| 134 | lo_passthru lp( |
| 135 | pck0, ck_1356meg, ck_1356megb, |
| 136 | lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4, |
| 137 | adc_d, lp_adc_clk, |
| 138 | lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk, |
| 139 | cross_hi, cross_lo, |
| 140 | lp_dbg, divisor |
| 141 | ); |
| 142 | |
| 143 | lo_edge_detect ls( |
| 144 | pck0, ck_1356meg, ck_1356megb, |
| 145 | ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4, |
| 146 | adc_d, ls_adc_clk, |
| 147 | ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk, |
| 148 | cross_hi, cross_lo, |
| 149 | ls_dbg, divisor, |
| 150 | lf_field |
| 151 | ); |
| 152 | |
| 153 | hi_read_tx ht( |
| 154 | pck0, ck_1356meg, ck_1356megb, |
| 155 | ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4, |
| 156 | adc_d, ht_adc_clk, |
| 157 | ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk, |
| 158 | cross_hi, cross_lo, |
| 159 | ht_dbg, |
| 160 | hi_read_tx_shallow_modulation |
| 161 | ); |
| 162 | |
| 163 | hi_read_rx_xcorr hrxc( |
| 164 | pck0, ck_1356meg, ck_1356megb, |
| 165 | hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4, |
| 166 | adc_d, hrxc_adc_clk, |
| 167 | hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk, |
| 168 | cross_hi, cross_lo, |
| 169 | hrxc_dbg, |
| 170 | hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter |
| 171 | ); |
| 172 | |
| 173 | hi_simulate hs( |
| 174 | pck0, ck_1356meg, ck_1356megb, |
| 175 | hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4, |
| 176 | adc_d, hs_adc_clk, |
| 177 | hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk, |
| 178 | cross_hi, cross_lo, |
| 179 | hs_dbg, |
| 180 | hi_simulate_mod_type |
| 181 | ); |
| 182 | |
| 183 | hi_iso14443a hisn( |
| 184 | pck0, ck_1356meg, ck_1356megb, |
| 185 | hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4, |
| 186 | adc_d, hisn_adc_clk, |
| 187 | hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk, |
| 188 | cross_hi, cross_lo, |
| 189 | hisn_dbg, |
| 190 | hi_simulate_mod_type |
| 191 | ); |
| 192 | |
| 193 | // Major modes: |
| 194 | // 000 -- LF reader (generic) |
| 195 | // 001 -- LF simulated tag (generic) |
| 196 | // 010 -- HF reader, transmitting to tag; modulation depth selectable |
| 197 | // 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable |
| 198 | // 100 -- HF simulated tag |
| 199 | // 101 -- HF ISO14443-A |
| 200 | // 110 -- LF passthrough |
| 201 | // 111 -- everything off |
| 202 | |
| 203 | mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0); |
| 204 | mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0); |
| 205 | mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0); |
| 206 | mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0); |
| 207 | mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0); |
| 208 | mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0); |
| 209 | mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0); |
| 210 | mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0); |
| 211 | mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0); |
| 212 | mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0); |
| 213 | mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0); |
| 214 | |
| 215 | // In all modes, let the ADC's outputs be enabled. |
| 216 | assign adc_noe = 1'b0; |
| 217 | |
| 218 | endmodule |