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uart_posix.c rework
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1# Ports
2telnet_port 4444
3gdb_port 3333
4
5# Interface
6interface buspirate
7buspirate_port /dev/ttyUSB0
8adapter_khz 1000
9
10# Communication speed
11buspirate_speed normal # or fast
12
13# Voltage regulator: enabled = 1 or disabled = 0
14buspirate_vreg 1
15
16# Pin mode: normal or open-drain
17buspirate_mode normal
18
19# Pull-up state: enabled = 1 or disabled = 0
20buspirate_pullup 1
21
22# use combined on interfaces or targets that can't set TRST/SRST separately
23reset_config srst_only srst_pulls_trst
24
25jtag newtap sam7x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x3f0f0f0f
26
27target create sam7x.cpu arm7tdmi -endian little -chain-position sam7x.cpu
28
29sam7x.cpu configure -event reset-init {
30 soft_reset_halt
31 mww 0xfffffd00 0xa5000004 # RSTC_CR: Reset peripherals
32 mww 0xfffffd44 0x00008000 # WDT_MR: disable watchdog
33 mww 0xfffffd08 0xa5000001 # RSTC_MR enable user reset
34 mww 0xfffffc20 0x00005001 # CKGR_MOR : enable the main oscillator
35 sleep 10
36 mww 0xfffffc2c 0x000b1c02 # CKGR_PLLR: 16MHz * 12/2 = 96MHz
37 sleep 10
38 mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 = 48 MHz
39 sleep 10
40 mww 0xffffff60 0x00480100 # MC_FMR: flash mode (FWS=1,FMCN=72)
41 sleep 100
42
43}
44
45gdb_memory_map enable
46#gdb_breakpoint_override hard
47#armv4_5 core_state arm
48
49sam7x.cpu configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x10000 -work-area-backup 0
50flash bank sam7x512.flash.0 at91sam7 0 0 0 0 sam7x.cpu 0 0 0 0 0 0 0 18432
51flash bank sam7x512.flash.1 at91sam7 0 0 0 0 sam7x.cpu 1 0 0 0 0 0 0 18432
52
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