]> git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/lfops.c
projects / proxmark3-svn / blob
? search:


072961a27fe506dee12a73a7a27c3cf221b18ca2
[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18 // split into two routines so we can avoid timing issues after sending commands //
19 void DoAcquisition125k_internal(bool silent)
20 {
21 uint8_t *dest = (uint8_t *)BigBuf;
22 int n = sizeof(BigBuf);
23 int i;
24
25 memset(dest, 0, n);
26 i = 0;
27 for(;;) {
28 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
29 AT91C_BASE_SSC->SSC_THR = 0x43;
30 LED_D_ON();
31 }
32 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
33 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
34 i++;
35 LED_D_OFF();
36 if (i >= n) break;
37 }
38 }
39 if( ! silent)
40 {
41 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
42 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
43 }
44 }
45
46 void DoAcquisition125k(void)
47 {
48 DoAcquisition125k_internal(false);
49 }
50
51 void SetupToAcquireRawAdcSamples(int divisor)
52 {
53 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
54 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
55 else if (divisor == 0)
56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
57 else
58 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
59
60 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
61
62 // Connect the A/D to the peak-detected low-frequency path.
63 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
64
65 // Give it a bit of time for the resonant antenna to settle.
66 SpinDelay(50);
67
68 // Now set up the SSC to get the ADC samples that are now streaming at us.
69 FpgaSetupSsc();
70 }
71
72 void AcquireRawAdcSamples125k(int divisor)
73 {
74 SetupToAcquireRawAdcSamples(divisor);
75 // Now call the acquisition routine
76 DoAcquisition125k_internal(false);
77 }
78
79 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
80 {
81 int at134khz;
82
83 /* Make sure the tag is reset */
84 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
85 SpinDelay(2500);
86
87 // see if 'h' was specified
88 if (command[strlen((char *) command) - 1] == 'h')
89 at134khz = TRUE;
90 else
91 at134khz = FALSE;
92
93 if (at134khz)
94 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
95 else
96 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
97
98 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
99
100 // Give it a bit of time for the resonant antenna to settle.
101 SpinDelay(50);
102 // And a little more time for the tag to fully power up
103 SpinDelay(2000);
104
105 // Now set up the SSC to get the ADC samples that are now streaming at us.
106 FpgaSetupSsc();
107
108 // now modulate the reader field
109 while(*command != '\0' && *command != ' ') {
110 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
111 LED_D_OFF();
112 SpinDelayUs(delay_off);
113 if (at134khz)
114 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
115 else
116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
117
118 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
119 LED_D_ON();
120 if(*(command++) == '0')
121 SpinDelayUs(period_0);
122 else
123 SpinDelayUs(period_1);
124 }
125 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
126 LED_D_OFF();
127 SpinDelayUs(delay_off);
128 if (at134khz)
129 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
130 else
131 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
132
133 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
134
135 // now do the read
136 DoAcquisition125k();
137 }
138
139 /* blank r/w tag data stream
140 ...0000000000000000 01111111
141 1010101010101010101010101010101010101010101010101010101010101010
142 0011010010100001
143 01111111
144 101010101010101[0]000...
145
146 [5555fe852c5555555555555555fe0000]
147 */
148 void ReadTItag(void)
149 {
150 // some hardcoded initial params
151 // when we read a TI tag we sample the zerocross line at 2Mhz
152 // TI tags modulate a 1 as 16 cycles of 123.2Khz
153 // TI tags modulate a 0 as 16 cycles of 134.2Khz
154 #define FSAMPLE 2000000
155 #define FREQLO 123200
156 #define FREQHI 134200
157
158 signed char *dest = (signed char *)BigBuf;
159 int n = sizeof(BigBuf);
160 // int *dest = GraphBuffer;
161 // int n = GraphTraceLen;
162
163 // 128 bit shift register [shift3:shift2:shift1:shift0]
164 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
165
166 int i, cycles=0, samples=0;
167 // how many sample points fit in 16 cycles of each frequency
168 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
169 // when to tell if we're close enough to one freq or another
170 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
171
172 // TI tags charge at 134.2Khz
173 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
174
175 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
176 // connects to SSP_DIN and the SSP_DOUT logic level controls
177 // whether we're modulating the antenna (high)
178 // or listening to the antenna (low)
179 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
180
181 // get TI tag data into the buffer
182 AcquireTiType();
183
184 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
185
186 for (i=0; i<n-1; i++) {
187 // count cycles by looking for lo to hi zero crossings
188 if ( (dest[i]<0) && (dest[i+1]>0) ) {
189 cycles++;
190 // after 16 cycles, measure the frequency
191 if (cycles>15) {
192 cycles=0;
193 samples=i-samples; // number of samples in these 16 cycles
194
195 // TI bits are coming to us lsb first so shift them
196 // right through our 128 bit right shift register
197 shift0 = (shift0>>1) | (shift1 << 31);
198 shift1 = (shift1>>1) | (shift2 << 31);
199 shift2 = (shift2>>1) | (shift3 << 31);
200 shift3 >>= 1;
201
202 // check if the cycles fall close to the number
203 // expected for either the low or high frequency
204 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
205 // low frequency represents a 1
206 shift3 |= (1<<31);
207 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
208 // high frequency represents a 0
209 } else {
210 // probably detected a gay waveform or noise
211 // use this as gaydar or discard shift register and start again
212 shift3 = shift2 = shift1 = shift0 = 0;
213 }
214 samples = i;
215
216 // for each bit we receive, test if we've detected a valid tag
217
218 // if we see 17 zeroes followed by 6 ones, we might have a tag
219 // remember the bits are backwards
220 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
221 // if start and end bytes match, we have a tag so break out of the loop
222 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
223 cycles = 0xF0B; //use this as a flag (ugly but whatever)
224 break;
225 }
226 }
227 }
228 }
229 }
230
231 // if flag is set we have a tag
232 if (cycles!=0xF0B) {
233 DbpString("Info: No valid tag detected.");
234 } else {
235 // put 64 bit data into shift1 and shift0
236 shift0 = (shift0>>24) | (shift1 << 8);
237 shift1 = (shift1>>24) | (shift2 << 8);
238
239 // align 16 bit crc into lower half of shift2
240 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
241
242 // if r/w tag, check ident match
243 if ( shift3&(1<<15) ) {
244 DbpString("Info: TI tag is rewriteable");
245 // only 15 bits compare, last bit of ident is not valid
246 if ( ((shift3>>16)^shift0)&0x7fff ) {
247 DbpString("Error: Ident mismatch!");
248 } else {
249 DbpString("Info: TI tag ident is valid");
250 }
251 } else {
252 DbpString("Info: TI tag is readonly");
253 }
254
255 // WARNING the order of the bytes in which we calc crc below needs checking
256 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
257 // bytes in reverse or something
258 // calculate CRC
259 uint32_t crc=0;
260
261 crc = update_crc16(crc, (shift0)&0xff);
262 crc = update_crc16(crc, (shift0>>8)&0xff);
263 crc = update_crc16(crc, (shift0>>16)&0xff);
264 crc = update_crc16(crc, (shift0>>24)&0xff);
265 crc = update_crc16(crc, (shift1)&0xff);
266 crc = update_crc16(crc, (shift1>>8)&0xff);
267 crc = update_crc16(crc, (shift1>>16)&0xff);
268 crc = update_crc16(crc, (shift1>>24)&0xff);
269
270 Dbprintf("Info: Tag data: %x%08x, crc=%x",
271 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
272 if (crc != (shift2&0xffff)) {
273 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
274 } else {
275 DbpString("Info: CRC is good");
276 }
277 }
278 }
279
280 void WriteTIbyte(uint8_t b)
281 {
282 int i = 0;
283
284 // modulate 8 bits out to the antenna
285 for (i=0; i<8; i++)
286 {
287 if (b&(1<<i)) {
288 // stop modulating antenna
289 LOW(GPIO_SSC_DOUT);
290 SpinDelayUs(1000);
291 // modulate antenna
292 HIGH(GPIO_SSC_DOUT);
293 SpinDelayUs(1000);
294 } else {
295 // stop modulating antenna
296 LOW(GPIO_SSC_DOUT);
297 SpinDelayUs(300);
298 // modulate antenna
299 HIGH(GPIO_SSC_DOUT);
300 SpinDelayUs(1700);
301 }
302 }
303 }
304
305 void AcquireTiType(void)
306 {
307 int i, j, n;
308 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
309 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
310 #define TIBUFLEN 1250
311
312 // clear buffer
313 memset(BigBuf,0,sizeof(BigBuf));
314
315 // Set up the synchronous serial port
316 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
317 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
318
319 // steal this pin from the SSP and use it to control the modulation
320 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
321 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
322
323 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
324 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
325
326 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
327 // 48/2 = 24 MHz clock must be divided by 12
328 AT91C_BASE_SSC->SSC_CMR = 12;
329
330 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
331 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
332 AT91C_BASE_SSC->SSC_TCMR = 0;
333 AT91C_BASE_SSC->SSC_TFMR = 0;
334
335 LED_D_ON();
336
337 // modulate antenna
338 HIGH(GPIO_SSC_DOUT);
339
340 // Charge TI tag for 50ms.
341 SpinDelay(50);
342
343 // stop modulating antenna and listen
344 LOW(GPIO_SSC_DOUT);
345
346 LED_D_OFF();
347
348 i = 0;
349 for(;;) {
350 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
351 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
352 i++; if(i >= TIBUFLEN) break;
353 }
354 WDT_HIT();
355 }
356
357 // return stolen pin to SSP
358 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
359 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
360
361 char *dest = (char *)BigBuf;
362 n = TIBUFLEN*32;
363 // unpack buffer
364 for (i=TIBUFLEN-1; i>=0; i--) {
365 for (j=0; j<32; j++) {
366 if(BigBuf[i] & (1 << j)) {
367 dest[--n] = 1;
368 } else {
369 dest[--n] = -1;
370 }
371 }
372 }
373 }
374
375 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
376 // if crc provided, it will be written with the data verbatim (even if bogus)
377 // if not provided a valid crc will be computed from the data and written.
378 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
379 {
380 if(crc == 0) {
381 crc = update_crc16(crc, (idlo)&0xff);
382 crc = update_crc16(crc, (idlo>>8)&0xff);
383 crc = update_crc16(crc, (idlo>>16)&0xff);
384 crc = update_crc16(crc, (idlo>>24)&0xff);
385 crc = update_crc16(crc, (idhi)&0xff);
386 crc = update_crc16(crc, (idhi>>8)&0xff);
387 crc = update_crc16(crc, (idhi>>16)&0xff);
388 crc = update_crc16(crc, (idhi>>24)&0xff);
389 }
390 Dbprintf("Writing to tag: %x%08x, crc=%x",
391 (unsigned int) idhi, (unsigned int) idlo, crc);
392
393 // TI tags charge at 134.2Khz
394 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
395 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
396 // connects to SSP_DIN and the SSP_DOUT logic level controls
397 // whether we're modulating the antenna (high)
398 // or listening to the antenna (low)
399 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
400 LED_A_ON();
401
402 // steal this pin from the SSP and use it to control the modulation
403 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
404 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
405
406 // writing algorithm:
407 // a high bit consists of a field off for 1ms and field on for 1ms
408 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
409 // initiate a charge time of 50ms (field on) then immediately start writing bits
410 // start by writing 0xBB (keyword) and 0xEB (password)
411 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
412 // finally end with 0x0300 (write frame)
413 // all data is sent lsb firts
414 // finish with 15ms programming time
415
416 // modulate antenna
417 HIGH(GPIO_SSC_DOUT);
418 SpinDelay(50); // charge time
419
420 WriteTIbyte(0xbb); // keyword
421 WriteTIbyte(0xeb); // password
422 WriteTIbyte( (idlo )&0xff );
423 WriteTIbyte( (idlo>>8 )&0xff );
424 WriteTIbyte( (idlo>>16)&0xff );
425 WriteTIbyte( (idlo>>24)&0xff );
426 WriteTIbyte( (idhi )&0xff );
427 WriteTIbyte( (idhi>>8 )&0xff );
428 WriteTIbyte( (idhi>>16)&0xff );
429 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
430 WriteTIbyte( (crc )&0xff ); // crc lo
431 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
432 WriteTIbyte(0x00); // write frame lo
433 WriteTIbyte(0x03); // write frame hi
434 HIGH(GPIO_SSC_DOUT);
435 SpinDelay(50); // programming time
436
437 LED_A_OFF();
438
439 // get TI tag data into the buffer
440 AcquireTiType();
441
442 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
443 DbpString("Now use tiread to check");
444 }
445
446 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
447 {
448 int i;
449 uint8_t *tab = (uint8_t *)BigBuf;
450
451 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
452
453 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
454
455 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
456 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
457
458 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
459 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
460
461 i = 0;
462 for(;;) {
463 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
464 if(BUTTON_PRESS()) {
465 DbpString("Stopped");
466 return;
467 }
468 WDT_HIT();
469 }
470
471 if (ledcontrol)
472 LED_D_ON();
473
474 if(tab[i])
475 OPEN_COIL();
476 else
477 SHORT_COIL();
478
479 if (ledcontrol)
480 LED_D_OFF();
481
482 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
483 if(BUTTON_PRESS()) {
484 DbpString("Stopped");
485 return;
486 }
487 WDT_HIT();
488 }
489
490 i++;
491 if(i == period) {
492 i = 0;
493 if (gap) {
494 SHORT_COIL();
495 SpinDelayUs(gap);
496 }
497 }
498 }
499 }
500
501 #define DEBUG_FRAME_CONTENTS 1
502 void SimulateTagLowFrequencyBidir(int divisor, int t0)
503 {
504 }
505
506 // compose fc/8 fc/10 waveform
507 static void fc(int c, int *n) {
508 uint8_t *dest = (uint8_t *)BigBuf;
509 int idx;
510
511 // for when we want an fc8 pattern every 4 logical bits
512 if(c==0) {
513 dest[((*n)++)]=1;
514 dest[((*n)++)]=1;
515 dest[((*n)++)]=0;
516 dest[((*n)++)]=0;
517 dest[((*n)++)]=0;
518 dest[((*n)++)]=0;
519 dest[((*n)++)]=0;
520 dest[((*n)++)]=0;
521 }
522 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
523 if(c==8) {
524 for (idx=0; idx<6; idx++) {
525 dest[((*n)++)]=1;
526 dest[((*n)++)]=1;
527 dest[((*n)++)]=0;
528 dest[((*n)++)]=0;
529 dest[((*n)++)]=0;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 dest[((*n)++)]=0;
533 }
534 }
535
536 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
537 if(c==10) {
538 for (idx=0; idx<5; idx++) {
539 dest[((*n)++)]=1;
540 dest[((*n)++)]=1;
541 dest[((*n)++)]=1;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 dest[((*n)++)]=0;
546 dest[((*n)++)]=0;
547 dest[((*n)++)]=0;
548 dest[((*n)++)]=0;
549 }
550 }
551 }
552
553 // prepare a waveform pattern in the buffer based on the ID given then
554 // simulate a HID tag until the button is pressed
555 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
556 {
557 int n=0, i=0;
558 /*
559 HID tag bitstream format
560 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
561 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
562 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
563 A fc8 is inserted before every 4 bits
564 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
565 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
566 */
567
568 if (hi>0xFFF) {
569 DbpString("Tags can only have 44 bits.");
570 return;
571 }
572 fc(0,&n);
573 // special start of frame marker containing invalid bit sequences
574 fc(8, &n); fc(8, &n); // invalid
575 fc(8, &n); fc(10, &n); // logical 0
576 fc(10, &n); fc(10, &n); // invalid
577 fc(8, &n); fc(10, &n); // logical 0
578
579 WDT_HIT();
580 // manchester encode bits 43 to 32
581 for (i=11; i>=0; i--) {
582 if ((i%4)==3) fc(0,&n);
583 if ((hi>>i)&1) {
584 fc(10, &n); fc(8, &n); // low-high transition
585 } else {
586 fc(8, &n); fc(10, &n); // high-low transition
587 }
588 }
589
590 WDT_HIT();
591 // manchester encode bits 31 to 0
592 for (i=31; i>=0; i--) {
593 if ((i%4)==3) fc(0,&n);
594 if ((lo>>i)&1) {
595 fc(10, &n); fc(8, &n); // low-high transition
596 } else {
597 fc(8, &n); fc(10, &n); // high-low transition
598 }
599 }
600
601 if (ledcontrol)
602 LED_A_ON();
603 SimulateTagLowFrequency(n, 0, ledcontrol);
604
605 if (ledcontrol)
606 LED_A_OFF();
607 }
608 void setup_for_125khz()
609 {
610 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
611 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
612
613 // Connect the A/D to the peak-detected low-frequency path.
614 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
615
616 // Give it a bit of time for the resonant antenna to settle.
617 SpinDelay(50);
618
619 // Now set up the SSC to get the ADC samples that are now streaming at us.
620 FpgaSetupSsc();
621
622 }
623 void get_samples(int ledcontrol, uint8_t* dest, int size)
624 {
625 int i = 0;
626
627 memset(dest,128,size);
628 for(;;) {
629 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
630 AT91C_BASE_SSC->SSC_THR = 0x43;
631 if (ledcontrol) LED_D_ON();
632 }
633 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
634 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
635 // we don't care about actual value, only if it's more or less than a
636 // threshold essentially we capture zero crossings for later analysis
637 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
638 i++;
639 if (ledcontrol) LED_D_OFF();
640 if(i >= size) {
641 break;
642 }
643 }
644 }
645 }
646
647 uint8_t fsk_demod(uint8_t * dest, int size)
648 {
649 uint8_t last_transition = 0;
650 uint8_t idx = 1;
651
652 // we don't care about actual value, only if it's more or less than a
653 // threshold essentially we capture zero crossings for later analysis
654 uint8_t threshold_value = 127;
655
656 WDT_HIT();
657
658 // sync to first lo-hi transition, and threshold
659
660 //Need to threshold first sample
661 if(dest[0] < threshold_value) dest[0] = 0;
662 else dest[0] = 1;
663
664 uint8_t numBits = 0;
665 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
666 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
667 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
668 for(idx = 1; idx < size; idx++) {
669
670 // threshold current value
671 if (dest[idx] < threshold_value) dest[idx] = 0;
672 else dest[idx] = 1;
673
674 // Check for 0->1 transition
675 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
676
677 if (idx-last_transition < 9) {
678 dest[numBits]=1;
679 } else {
680 dest[numBits]=0;
681 }
682 last_transition = idx;
683 numBits++;
684 }
685 }
686 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
687 }
688
689 uint8_t aggregate_bits(uint8_t *dest,uint8_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
690 {
691 uint8_t lastval=dest[0];
692 uint8_t idx=0;
693 uint8_t numBits=0;
694 uint8_t n=1, i=0;
695
696 for( idx=1; idx < size; idx++) {
697
698 if (dest[idx]==lastval) {
699 n++;
700 continue;
701 }
702 //if lastval was 1, we have a 1->0 crossing
703 if ( lastval ) {
704 n=(n+1)/7;
705 } else {// 0->1 crossing
706 n=(n+1)/6;
707 }
708 if(n < 13)
709 {
710 memset(dest+i, lastval ^ 1, n);
711 numBits += n;
712 }
713 n=0;
714 lastval=dest[idx];
715 }//end for
716
717 return numBits;
718
719 }
720 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
721 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
722 {
723 uint8_t *dest = (uint8_t *)BigBuf;
724
725 int size=0, idx=0, found=0;
726 uint32_t hi2=0, hi=0, lo=0;
727
728 // Configure to go in 125Khz listen mode
729 SetupToAcquireRawAdcSamples(0);
730
731 for(;;) {
732 WDT_HIT();
733 if (ledcontrol)
734 LED_A_ON();
735 if(BUTTON_PRESS()) {
736 DbpString("Stopped");
737 if (ledcontrol)
738 LED_A_OFF();
739 return;
740 }
741
742
743 DoAcquisition125k_internal(true);
744 size = sizeof(BigBuf);
745
746 // FSK demodulator
747 size = fsk_demod(dest, size);
748
749 WDT_HIT();
750
751 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
752
753 // 1->0 : fc/8 in sets of 6
754 // 0->1 : fc/10 in sets of 5
755 size = aggregate_bits(dest,size, 6,5,5);
756
757 WDT_HIT();
758
759 // final loop, go over previously decoded manchester data and decode into usable tag ID
760 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
761 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
762
763 for( idx=0; idx < size-sizeof(frame_marker_mask); idx++) {
764
765 if (found) {
766 if(dest[idx] == dest[idx+1])
767 {// 1 1 or 00
768 found=0;
769 hi2=0;
770 hi=0;
771 lo=0;
772 }else
773 {
774 //Shift in a bit. Start by shifting high registers
775 hi2 = (hi2<<1)|(hi>>31);
776 hi = (hi<<1)|(lo>>31);
777 //Then, shift in a 0 or one into low
778 if (dest[idx] && !dest[idx+1]) // 1 0
779 lo=(lo<<1)|0;
780 else // 0 1
781 lo=(lo<<1)|1;
782 }
783 idx++;
784 }
785
786 // search for a start of frame marker
787 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
788 { // Found start of frame marker
789 found=1;
790 idx+=sizeof(frame_marker_mask);
791 if (found && (hi2|hi|lo)) {
792 if (hi2 != 0){
793 Dbprintf("TAG ID: %x%08x%08x (%d)",
794 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
795 }
796 else {
797 Dbprintf("TAG ID: %x%08x (%d)",
798 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
799 }
800 /* if we're only looking for one tag */
801 if (findone)
802 {
803 *high = hi;
804 *low = lo;
805 return;
806 }
807 hi2=0;
808 hi=0;
809 lo=0;
810 found=0;
811 }
812 }
813 }
814 WDT_HIT();
815 }
816 }
817
818 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
819 {
820 uint32_t num = 0;
821 for(int i = 0 ; i < numbits ; i++)
822 {
823 num = (num << 1) | (*src);
824 src++;
825 }
826 return num;
827 }
828
829
830 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
831 {
832 uint8_t *dest = (uint8_t *)BigBuf;
833 int size=0, idx=0;
834 uint32_t code=0, code2=0;
835 //uint32_t hi2=0, hi=0, lo=0;
836
837 setup_for_125khz();
838
839 for(;;) {
840 WDT_HIT();
841 if (ledcontrol)
842 LED_A_ON();
843 if(BUTTON_PRESS()) {
844 DbpString("Stopped");
845 if (ledcontrol)
846 LED_A_OFF();
847 return;
848 }
849
850 DoAcquisition125k_internal(true);
851 size = sizeof(BigBuf);
852
853 // FSK demodulator
854 size = fsk_demod(dest, size);
855 WDT_HIT();
856 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
857 // 1->0 : fc/8 in sets of 7
858 // 0->1 : fc/10 in sets of 6
859 size = aggregate_bits(dest, size, 7,6,13);
860
861 WDT_HIT();
862
863 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
864 for( idx=0; idx < size - 64; idx++) {
865
866 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
867
868 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
869 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
870 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
871 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
872 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
873 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
874 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
875 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
876
877 code = bytebits_to_byte(dest+idx,32);
878 code2 = bytebits_to_byte(dest+idx+32,32);
879
880 short version = bytebits_to_byte(dest+idx+14,4);
881 char unknown = bytebits_to_byte(dest+idx+19,8) ;
882 uint16_t number = bytebits_to_byte(dest+idx+36,9);
883
884 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
885 if (ledcontrol) LED_D_OFF();
886
887 // if we're only looking for one tag
888 if (findone){
889 LED_A_OFF();
890 return;
891 }
892 }
893 }
894 WDT_HIT();
895 }
896
897 /*------------------------------
898 * T5555/T5557/T5567 routines
899 *------------------------------
900 */
901
902 /* T55x7 configuration register definitions */
903 #define T55x7_POR_DELAY 0x00000001
904 #define T55x7_ST_TERMINATOR 0x00000008
905 #define T55x7_PWD 0x00000010
906 #define T55x7_MAXBLOCK_SHIFT 5
907 #define T55x7_AOR 0x00000200
908 #define T55x7_PSKCF_RF_2 0
909 #define T55x7_PSKCF_RF_4 0x00000400
910 #define T55x7_PSKCF_RF_8 0x00000800
911 #define T55x7_MODULATION_DIRECT 0
912 #define T55x7_MODULATION_PSK1 0x00001000
913 #define T55x7_MODULATION_PSK2 0x00002000
914 #define T55x7_MODULATION_PSK3 0x00003000
915 #define T55x7_MODULATION_FSK1 0x00004000
916 #define T55x7_MODULATION_FSK2 0x00005000
917 #define T55x7_MODULATION_FSK1a 0x00006000
918 #define T55x7_MODULATION_FSK2a 0x00007000
919 #define T55x7_MODULATION_MANCHESTER 0x00008000
920 #define T55x7_MODULATION_BIPHASE 0x00010000
921 #define T55x7_BITRATE_RF_8 0
922 #define T55x7_BITRATE_RF_16 0x00040000
923 #define T55x7_BITRATE_RF_32 0x00080000
924 #define T55x7_BITRATE_RF_40 0x000C0000
925 #define T55x7_BITRATE_RF_50 0x00100000
926 #define T55x7_BITRATE_RF_64 0x00140000
927 #define T55x7_BITRATE_RF_100 0x00180000
928 #define T55x7_BITRATE_RF_128 0x001C0000
929
930 /* T5555 (Q5) configuration register definitions */
931 #define T5555_ST_TERMINATOR 0x00000001
932 #define T5555_MAXBLOCK_SHIFT 0x00000001
933 #define T5555_MODULATION_MANCHESTER 0
934 #define T5555_MODULATION_PSK1 0x00000010
935 #define T5555_MODULATION_PSK2 0x00000020
936 #define T5555_MODULATION_PSK3 0x00000030
937 #define T5555_MODULATION_FSK1 0x00000040
938 #define T5555_MODULATION_FSK2 0x00000050
939 #define T5555_MODULATION_BIPHASE 0x00000060
940 #define T5555_MODULATION_DIRECT 0x00000070
941 #define T5555_INVERT_OUTPUT 0x00000080
942 #define T5555_PSK_RF_2 0
943 #define T5555_PSK_RF_4 0x00000100
944 #define T5555_PSK_RF_8 0x00000200
945 #define T5555_USE_PWD 0x00000400
946 #define T5555_USE_AOR 0x00000800
947 #define T5555_BITRATE_SHIFT 12
948 #define T5555_FAST_WRITE 0x00004000
949 #define T5555_PAGE_SELECT 0x00008000
950
951 /*
952 * Relevant times in microsecond
953 * To compensate antenna falling times shorten the write times
954 * and enlarge the gap ones.
955 */
956 #define START_GAP 250
957 #define WRITE_GAP 160
958 #define WRITE_0 144 // 192
959 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
960
961 // Write one bit to card
962 void T55xxWriteBit(int bit)
963 {
964 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
965 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
966 if (bit == 0)
967 SpinDelayUs(WRITE_0);
968 else
969 SpinDelayUs(WRITE_1);
970 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
971 SpinDelayUs(WRITE_GAP);
972 }
973
974 // Write one card block in page 0, no lock
975 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
976 {
977 unsigned int i;
978
979 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
980 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
981
982 // Give it a bit of time for the resonant antenna to settle.
983 // And for the tag to fully power up
984 SpinDelay(150);
985
986 // Now start writting
987 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
988 SpinDelayUs(START_GAP);
989
990 // Opcode
991 T55xxWriteBit(1);
992 T55xxWriteBit(0); //Page 0
993 if (PwdMode == 1){
994 // Pwd
995 for (i = 0x80000000; i != 0; i >>= 1)
996 T55xxWriteBit(Pwd & i);
997 }
998 // Lock bit
999 T55xxWriteBit(0);
1000
1001 // Data
1002 for (i = 0x80000000; i != 0; i >>= 1)
1003 T55xxWriteBit(Data & i);
1004
1005 // Block
1006 for (i = 0x04; i != 0; i >>= 1)
1007 T55xxWriteBit(Block & i);
1008
1009 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1010 // so wait a little more)
1011 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1012 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1013 SpinDelay(20);
1014 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1015 }
1016
1017 // Read one card block in page 0
1018 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1019 {
1020 uint8_t *dest = (uint8_t *)BigBuf;
1021 int m=0, i=0;
1022
1023 m = sizeof(BigBuf);
1024 // Clear destination buffer before sending the command
1025 memset(dest, 128, m);
1026 // Connect the A/D to the peak-detected low-frequency path.
1027 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1028 // Now set up the SSC to get the ADC samples that are now streaming at us.
1029 FpgaSetupSsc();
1030
1031 LED_D_ON();
1032 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1033 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1034
1035 // Give it a bit of time for the resonant antenna to settle.
1036 // And for the tag to fully power up
1037 SpinDelay(150);
1038
1039 // Now start writting
1040 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1041 SpinDelayUs(START_GAP);
1042
1043 // Opcode
1044 T55xxWriteBit(1);
1045 T55xxWriteBit(0); //Page 0
1046 if (PwdMode == 1){
1047 // Pwd
1048 for (i = 0x80000000; i != 0; i >>= 1)
1049 T55xxWriteBit(Pwd & i);
1050 }
1051 // Lock bit
1052 T55xxWriteBit(0);
1053 // Block
1054 for (i = 0x04; i != 0; i >>= 1)
1055 T55xxWriteBit(Block & i);
1056
1057 // Turn field on to read the response
1058 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1059 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1060
1061 // Now do the acquisition
1062 i = 0;
1063 for(;;) {
1064 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1065 AT91C_BASE_SSC->SSC_THR = 0x43;
1066 }
1067 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1068 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1069 // we don't care about actual value, only if it's more or less than a
1070 // threshold essentially we capture zero crossings for later analysis
1071 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1072 i++;
1073 if (i >= m) break;
1074 }
1075 }
1076
1077 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1078 LED_D_OFF();
1079 DbpString("DONE!");
1080 }
1081
1082 // Read card traceability data (page 1)
1083 void T55xxReadTrace(void){
1084 uint8_t *dest = (uint8_t *)BigBuf;
1085 int m=0, i=0;
1086
1087 m = sizeof(BigBuf);
1088 // Clear destination buffer before sending the command
1089 memset(dest, 128, m);
1090 // Connect the A/D to the peak-detected low-frequency path.
1091 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1092 // Now set up the SSC to get the ADC samples that are now streaming at us.
1093 FpgaSetupSsc();
1094
1095 LED_D_ON();
1096 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1097 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1098
1099 // Give it a bit of time for the resonant antenna to settle.
1100 // And for the tag to fully power up
1101 SpinDelay(150);
1102
1103 // Now start writting
1104 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1105 SpinDelayUs(START_GAP);
1106
1107 // Opcode
1108 T55xxWriteBit(1);
1109 T55xxWriteBit(1); //Page 1
1110
1111 // Turn field on to read the response
1112 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1113 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1114
1115 // Now do the acquisition
1116 i = 0;
1117 for(;;) {
1118 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1119 AT91C_BASE_SSC->SSC_THR = 0x43;
1120 }
1121 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1122 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1123 i++;
1124 if (i >= m) break;
1125 }
1126 }
1127
1128 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1129 LED_D_OFF();
1130 DbpString("DONE!");
1131 }
1132
1133 /*-------------- Cloning routines -----------*/
1134 // Copy HID id to card and setup block 0 config
1135 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1136 {
1137 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1138 int last_block = 0;
1139
1140 if (longFMT){
1141 // Ensure no more than 84 bits supplied
1142 if (hi2>0xFFFFF) {
1143 DbpString("Tags can only have 84 bits.");
1144 return;
1145 }
1146 // Build the 6 data blocks for supplied 84bit ID
1147 last_block = 6;
1148 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1149 for (int i=0;i<4;i++) {
1150 if (hi2 & (1<<(19-i)))
1151 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1152 else
1153 data1 |= (1<<((3-i)*2)); // 0 -> 01
1154 }
1155
1156 data2 = 0;
1157 for (int i=0;i<16;i++) {
1158 if (hi2 & (1<<(15-i)))
1159 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1160 else
1161 data2 |= (1<<((15-i)*2)); // 0 -> 01
1162 }
1163
1164 data3 = 0;
1165 for (int i=0;i<16;i++) {
1166 if (hi & (1<<(31-i)))
1167 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1168 else
1169 data3 |= (1<<((15-i)*2)); // 0 -> 01
1170 }
1171
1172 data4 = 0;
1173 for (int i=0;i<16;i++) {
1174 if (hi & (1<<(15-i)))
1175 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1176 else
1177 data4 |= (1<<((15-i)*2)); // 0 -> 01
1178 }
1179
1180 data5 = 0;
1181 for (int i=0;i<16;i++) {
1182 if (lo & (1<<(31-i)))
1183 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1184 else
1185 data5 |= (1<<((15-i)*2)); // 0 -> 01
1186 }
1187
1188 data6 = 0;
1189 for (int i=0;i<16;i++) {
1190 if (lo & (1<<(15-i)))
1191 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1192 else
1193 data6 |= (1<<((15-i)*2)); // 0 -> 01
1194 }
1195 }
1196 else {
1197 // Ensure no more than 44 bits supplied
1198 if (hi>0xFFF) {
1199 DbpString("Tags can only have 44 bits.");
1200 return;
1201 }
1202
1203 // Build the 3 data blocks for supplied 44bit ID
1204 last_block = 3;
1205
1206 data1 = 0x1D000000; // load preamble
1207
1208 for (int i=0;i<12;i++) {
1209 if (hi & (1<<(11-i)))
1210 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1211 else
1212 data1 |= (1<<((11-i)*2)); // 0 -> 01
1213 }
1214
1215 data2 = 0;
1216 for (int i=0;i<16;i++) {
1217 if (lo & (1<<(31-i)))
1218 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1219 else
1220 data2 |= (1<<((15-i)*2)); // 0 -> 01
1221 }
1222
1223 data3 = 0;
1224 for (int i=0;i<16;i++) {
1225 if (lo & (1<<(15-i)))
1226 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1227 else
1228 data3 |= (1<<((15-i)*2)); // 0 -> 01
1229 }
1230 }
1231
1232 LED_D_ON();
1233 // Program the data blocks for supplied ID
1234 // and the block 0 for HID format
1235 T55xxWriteBlock(data1,1,0,0);
1236 T55xxWriteBlock(data2,2,0,0);
1237 T55xxWriteBlock(data3,3,0,0);
1238
1239 if (longFMT) { // if long format there are 6 blocks
1240 T55xxWriteBlock(data4,4,0,0);
1241 T55xxWriteBlock(data5,5,0,0);
1242 T55xxWriteBlock(data6,6,0,0);
1243 }
1244
1245 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1246 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1247 T55x7_MODULATION_FSK2a |
1248 last_block << T55x7_MAXBLOCK_SHIFT,
1249 0,0,0);
1250
1251 LED_D_OFF();
1252
1253 DbpString("DONE!");
1254 }
1255
1256 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1257 {
1258 int data1=0, data2=0; //up to six blocks for long format
1259
1260 data1 = hi; // load preamble
1261 data2 = lo;
1262
1263 LED_D_ON();
1264 // Program the data blocks for supplied ID
1265 // and the block 0 for HID format
1266 T55xxWriteBlock(data1,1,0,0);
1267 T55xxWriteBlock(data2,2,0,0);
1268
1269 //Config Block
1270 T55xxWriteBlock(0x00147040,0,0,0);
1271 LED_D_OFF();
1272
1273 DbpString("DONE!");
1274 }
1275
1276 // Define 9bit header for EM410x tags
1277 #define EM410X_HEADER 0x1FF
1278 #define EM410X_ID_LENGTH 40
1279
1280 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1281 {
1282 int i, id_bit;
1283 uint64_t id = EM410X_HEADER;
1284 uint64_t rev_id = 0; // reversed ID
1285 int c_parity[4]; // column parity
1286 int r_parity = 0; // row parity
1287 uint32_t clock = 0;
1288
1289 // Reverse ID bits given as parameter (for simpler operations)
1290 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1291 if (i < 32) {
1292 rev_id = (rev_id << 1) | (id_lo & 1);
1293 id_lo >>= 1;
1294 } else {
1295 rev_id = (rev_id << 1) | (id_hi & 1);
1296 id_hi >>= 1;
1297 }
1298 }
1299
1300 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1301 id_bit = rev_id & 1;
1302
1303 if (i % 4 == 0) {
1304 // Don't write row parity bit at start of parsing
1305 if (i)
1306 id = (id << 1) | r_parity;
1307 // Start counting parity for new row
1308 r_parity = id_bit;
1309 } else {
1310 // Count row parity
1311 r_parity ^= id_bit;
1312 }
1313
1314 // First elements in column?
1315 if (i < 4)
1316 // Fill out first elements
1317 c_parity[i] = id_bit;
1318 else
1319 // Count column parity
1320 c_parity[i % 4] ^= id_bit;
1321
1322 // Insert ID bit
1323 id = (id << 1) | id_bit;
1324 rev_id >>= 1;
1325 }
1326
1327 // Insert parity bit of last row
1328 id = (id << 1) | r_parity;
1329
1330 // Fill out column parity at the end of tag
1331 for (i = 0; i < 4; ++i)
1332 id = (id << 1) | c_parity[i];
1333
1334 // Add stop bit
1335 id <<= 1;
1336
1337 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1338 LED_D_ON();
1339
1340 // Write EM410x ID
1341 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1342 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1343
1344 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1345 if (card) {
1346 // Clock rate is stored in bits 8-15 of the card value
1347 clock = (card & 0xFF00) >> 8;
1348 Dbprintf("Clock rate: %d", clock);
1349 switch (clock)
1350 {
1351 case 32:
1352 clock = T55x7_BITRATE_RF_32;
1353 break;
1354 case 16:
1355 clock = T55x7_BITRATE_RF_16;
1356 break;
1357 case 0:
1358 // A value of 0 is assumed to be 64 for backwards-compatibility
1359 // Fall through...
1360 case 64:
1361 clock = T55x7_BITRATE_RF_64;
1362 break;
1363 default:
1364 Dbprintf("Invalid clock rate: %d", clock);
1365 return;
1366 }
1367
1368 // Writing configuration for T55x7 tag
1369 T55xxWriteBlock(clock |
1370 T55x7_MODULATION_MANCHESTER |
1371 2 << T55x7_MAXBLOCK_SHIFT,
1372 0, 0, 0);
1373 }
1374 else
1375 // Writing configuration for T5555(Q5) tag
1376 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1377 T5555_MODULATION_MANCHESTER |
1378 2 << T5555_MAXBLOCK_SHIFT,
1379 0, 0, 0);
1380
1381 LED_D_OFF();
1382 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1383 (uint32_t)(id >> 32), (uint32_t)id);
1384 }
1385
1386 // Clone Indala 64-bit tag by UID to T55x7
1387 void CopyIndala64toT55x7(int hi, int lo)
1388 {
1389
1390 //Program the 2 data blocks for supplied 64bit UID
1391 // and the block 0 for Indala64 format
1392 T55xxWriteBlock(hi,1,0,0);
1393 T55xxWriteBlock(lo,2,0,0);
1394 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1395 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1396 T55x7_MODULATION_PSK1 |
1397 2 << T55x7_MAXBLOCK_SHIFT,
1398 0, 0, 0);
1399 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1400 // T5567WriteBlock(0x603E1042,0);
1401
1402 DbpString("DONE!");
1403
1404 }
1405
1406 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1407 {
1408
1409 //Program the 7 data blocks for supplied 224bit UID
1410 // and the block 0 for Indala224 format
1411 T55xxWriteBlock(uid1,1,0,0);
1412 T55xxWriteBlock(uid2,2,0,0);
1413 T55xxWriteBlock(uid3,3,0,0);
1414 T55xxWriteBlock(uid4,4,0,0);
1415 T55xxWriteBlock(uid5,5,0,0);
1416 T55xxWriteBlock(uid6,6,0,0);
1417 T55xxWriteBlock(uid7,7,0,0);
1418 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1419 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1420 T55x7_MODULATION_PSK1 |
1421 7 << T55x7_MAXBLOCK_SHIFT,
1422 0,0,0);
1423 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1424 // T5567WriteBlock(0x603E10E2,0);
1425
1426 DbpString("DONE!");
1427
1428 }
1429
1430
1431 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1432 #define max(x,y) ( x<y ? y:x)
1433
1434 int DemodPCF7931(uint8_t **outBlocks) {
1435 uint8_t BitStream[256];
1436 uint8_t Blocks[8][16];
1437 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1438 int GraphTraceLen = sizeof(BigBuf);
1439 int i, j, lastval, bitidx, half_switch;
1440 int clock = 64;
1441 int tolerance = clock / 8;
1442 int pmc, block_done;
1443 int lc, warnings = 0;
1444 int num_blocks = 0;
1445 int lmin=128, lmax=128;
1446 uint8_t dir;
1447
1448 AcquireRawAdcSamples125k(0);
1449
1450 lmin = 64;
1451 lmax = 192;
1452
1453 i = 2;
1454
1455 /* Find first local max/min */
1456 if(GraphBuffer[1] > GraphBuffer[0]) {
1457 while(i < GraphTraceLen) {
1458 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1459 break;
1460 i++;
1461 }
1462 dir = 0;
1463 }
1464 else {
1465 while(i < GraphTraceLen) {
1466 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1467 break;
1468 i++;
1469 }
1470 dir = 1;
1471 }
1472
1473 lastval = i++;
1474 half_switch = 0;
1475 pmc = 0;
1476 block_done = 0;
1477
1478 for (bitidx = 0; i < GraphTraceLen; i++)
1479 {
1480 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1481 {
1482 lc = i - lastval;
1483 lastval = i;
1484
1485 // Switch depending on lc length:
1486 // Tolerance is 1/8 of clock rate (arbitrary)
1487 if (abs(lc-clock/4) < tolerance) {
1488 // 16T0
1489 if((i - pmc) == lc) { /* 16T0 was previous one */
1490 /* It's a PMC ! */
1491 i += (128+127+16+32+33+16)-1;
1492 lastval = i;
1493 pmc = 0;
1494 block_done = 1;
1495 }
1496 else {
1497 pmc = i;
1498 }
1499 } else if (abs(lc-clock/2) < tolerance) {
1500 // 32TO
1501 if((i - pmc) == lc) { /* 16T0 was previous one */
1502 /* It's a PMC ! */
1503 i += (128+127+16+32+33)-1;
1504 lastval = i;
1505 pmc = 0;
1506 block_done = 1;
1507 }
1508 else if(half_switch == 1) {
1509 BitStream[bitidx++] = 0;
1510 half_switch = 0;
1511 }
1512 else
1513 half_switch++;
1514 } else if (abs(lc-clock) < tolerance) {
1515 // 64TO
1516 BitStream[bitidx++] = 1;
1517 } else {
1518 // Error
1519 warnings++;
1520 if (warnings > 10)
1521 {
1522 Dbprintf("Error: too many detection errors, aborting.");
1523 return 0;
1524 }
1525 }
1526
1527 if(block_done == 1) {
1528 if(bitidx == 128) {
1529 for(j=0; j<16; j++) {
1530 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1531 64*BitStream[j*8+6]+
1532 32*BitStream[j*8+5]+
1533 16*BitStream[j*8+4]+
1534 8*BitStream[j*8+3]+
1535 4*BitStream[j*8+2]+
1536 2*BitStream[j*8+1]+
1537 BitStream[j*8];
1538 }
1539 num_blocks++;
1540 }
1541 bitidx = 0;
1542 block_done = 0;
1543 half_switch = 0;
1544 }
1545 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1546 else dir = 1;
1547 }
1548 if(bitidx==255)
1549 bitidx=0;
1550 warnings = 0;
1551 if(num_blocks == 4) break;
1552 }
1553 memcpy(outBlocks, Blocks, 16*num_blocks);
1554 return num_blocks;
1555 }
1556
1557 int IsBlock0PCF7931(uint8_t *Block) {
1558 // Assume RFU means 0 :)
1559 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1560 return 1;
1561 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1562 return 1;
1563 return 0;
1564 }
1565
1566 int IsBlock1PCF7931(uint8_t *Block) {
1567 // Assume RFU means 0 :)
1568 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1569 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1570 return 1;
1571
1572 return 0;
1573 }
1574
1575 #define ALLOC 16
1576
1577 void ReadPCF7931() {
1578 uint8_t Blocks[8][17];
1579 uint8_t tmpBlocks[4][16];
1580 int i, j, ind, ind2, n;
1581 int num_blocks = 0;
1582 int max_blocks = 8;
1583 int ident = 0;
1584 int error = 0;
1585 int tries = 0;
1586
1587 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1588
1589 do {
1590 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1591 n = DemodPCF7931((uint8_t**)tmpBlocks);
1592 if(!n)
1593 error++;
1594 if(error==10 && num_blocks == 0) {
1595 Dbprintf("Error, no tag or bad tag");
1596 return;
1597 }
1598 else if (tries==20 || error==10) {
1599 Dbprintf("Error reading the tag");
1600 Dbprintf("Here is the partial content");
1601 goto end;
1602 }
1603
1604 for(i=0; i<n; i++)
1605 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1606 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1607 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1608 if(!ident) {
1609 for(i=0; i<n; i++) {
1610 if(IsBlock0PCF7931(tmpBlocks[i])) {
1611 // Found block 0 ?
1612 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1613 // Found block 1!
1614 // \o/
1615 ident = 1;
1616 memcpy(Blocks[0], tmpBlocks[i], 16);
1617 Blocks[0][ALLOC] = 1;
1618 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1619 Blocks[1][ALLOC] = 1;
1620 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1621 // Debug print
1622 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1623 num_blocks = 2;
1624 // Handle following blocks
1625 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1626 if(j==n) j=0;
1627 if(j==i) break;
1628 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1629 Blocks[ind2][ALLOC] = 1;
1630 }
1631 break;
1632 }
1633 }
1634 }
1635 }
1636 else {
1637 for(i=0; i<n; i++) { // Look for identical block in known blocks
1638 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1639 for(j=0; j<max_blocks; j++) {
1640 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1641 // Found an identical block
1642 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1643 if(ind2 < 0)
1644 ind2 = max_blocks;
1645 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1646 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1647 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1648 Blocks[ind2][ALLOC] = 1;
1649 num_blocks++;
1650 if(num_blocks == max_blocks) goto end;
1651 }
1652 }
1653 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1654 if(ind2 > max_blocks)
1655 ind2 = 0;
1656 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1657 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1658 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1659 Blocks[ind2][ALLOC] = 1;
1660 num_blocks++;
1661 if(num_blocks == max_blocks) goto end;
1662 }
1663 }
1664 }
1665 }
1666 }
1667 }
1668 }
1669 tries++;
1670 if (BUTTON_PRESS()) return;
1671 } while (num_blocks != max_blocks);
1672 end:
1673 Dbprintf("-----------------------------------------");
1674 Dbprintf("Memory content:");
1675 Dbprintf("-----------------------------------------");
1676 for(i=0; i<max_blocks; i++) {
1677 if(Blocks[i][ALLOC]==1)
1678 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1679 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1680 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1681 else
1682 Dbprintf("<missing block %d>", i);
1683 }
1684 Dbprintf("-----------------------------------------");
1685
1686 return ;
1687 }
1688
1689
1690 //-----------------------------------
1691 // EM4469 / EM4305 routines
1692 //-----------------------------------
1693 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1694 #define FWD_CMD_WRITE 0xA
1695 #define FWD_CMD_READ 0x9
1696 #define FWD_CMD_DISABLE 0x5
1697
1698
1699 uint8_t forwardLink_data[64]; //array of forwarded bits
1700 uint8_t * forward_ptr; //ptr for forward message preparation
1701 uint8_t fwd_bit_sz; //forwardlink bit counter
1702 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1703
1704 //====================================================================
1705 // prepares command bits
1706 // see EM4469 spec
1707 //====================================================================
1708 //--------------------------------------------------------------------
1709 uint8_t Prepare_Cmd( uint8_t cmd ) {
1710 //--------------------------------------------------------------------
1711
1712 *forward_ptr++ = 0; //start bit
1713 *forward_ptr++ = 0; //second pause for 4050 code
1714
1715 *forward_ptr++ = cmd;
1716 cmd >>= 1;
1717 *forward_ptr++ = cmd;
1718 cmd >>= 1;
1719 *forward_ptr++ = cmd;
1720 cmd >>= 1;
1721 *forward_ptr++ = cmd;
1722
1723 return 6; //return number of emited bits
1724 }
1725
1726 //====================================================================
1727 // prepares address bits
1728 // see EM4469 spec
1729 //====================================================================
1730
1731 //--------------------------------------------------------------------
1732 uint8_t Prepare_Addr( uint8_t addr ) {
1733 //--------------------------------------------------------------------
1734
1735 register uint8_t line_parity;
1736
1737 uint8_t i;
1738 line_parity = 0;
1739 for(i=0;i<6;i++) {
1740 *forward_ptr++ = addr;
1741 line_parity ^= addr;
1742 addr >>= 1;
1743 }
1744
1745 *forward_ptr++ = (line_parity & 1);
1746
1747 return 7; //return number of emited bits
1748 }
1749
1750 //====================================================================
1751 // prepares data bits intreleaved with parity bits
1752 // see EM4469 spec
1753 //====================================================================
1754
1755 //--------------------------------------------------------------------
1756 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1757 //--------------------------------------------------------------------
1758
1759 register uint8_t line_parity;
1760 register uint8_t column_parity;
1761 register uint8_t i, j;
1762 register uint16_t data;
1763
1764 data = data_low;
1765 column_parity = 0;
1766
1767 for(i=0; i<4; i++) {
1768 line_parity = 0;
1769 for(j=0; j<8; j++) {
1770 line_parity ^= data;
1771 column_parity ^= (data & 1) << j;
1772 *forward_ptr++ = data;
1773 data >>= 1;
1774 }
1775 *forward_ptr++ = line_parity;
1776 if(i == 1)
1777 data = data_hi;
1778 }
1779
1780 for(j=0; j<8; j++) {
1781 *forward_ptr++ = column_parity;
1782 column_parity >>= 1;
1783 }
1784 *forward_ptr = 0;
1785
1786 return 45; //return number of emited bits
1787 }
1788
1789 //====================================================================
1790 // Forward Link send function
1791 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1792 // fwd_bit_count set with number of bits to be sent
1793 //====================================================================
1794 void SendForward(uint8_t fwd_bit_count) {
1795
1796 fwd_write_ptr = forwardLink_data;
1797 fwd_bit_sz = fwd_bit_count;
1798
1799 LED_D_ON();
1800
1801 //Field on
1802 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1803 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
1804
1805 // Give it a bit of time for the resonant antenna to settle.
1806 // And for the tag to fully power up
1807 SpinDelay(150);
1808
1809 // force 1st mod pulse (start gap must be longer for 4305)
1810 fwd_bit_sz--; //prepare next bit modulation
1811 fwd_write_ptr++;
1812 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1813 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1814 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1815 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
1816 SpinDelayUs(16*8); //16 cycles on (8us each)
1817
1818 // now start writting
1819 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1820 if(((*fwd_write_ptr++) & 1) == 1)
1821 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1822 else {
1823 //These timings work for 4469/4269/4305 (with the 55*8 above)
1824 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1825 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1826 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1827 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
1828 SpinDelayUs(9*8); //16 cycles on (8us each)
1829 }
1830 }
1831 }
1832
1833 void EM4xLogin(uint32_t Password) {
1834
1835 uint8_t fwd_bit_count;
1836
1837 forward_ptr = forwardLink_data;
1838 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1839 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1840
1841 SendForward(fwd_bit_count);
1842
1843 //Wait for command to complete
1844 SpinDelay(20);
1845
1846 }
1847
1848 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1849
1850 uint8_t fwd_bit_count;
1851 uint8_t *dest = (uint8_t *)BigBuf;
1852 int m=0, i=0;
1853
1854 //If password mode do login
1855 if (PwdMode == 1) EM4xLogin(Pwd);
1856
1857 forward_ptr = forwardLink_data;
1858 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1859 fwd_bit_count += Prepare_Addr( Address );
1860
1861 m = sizeof(BigBuf);
1862 // Clear destination buffer before sending the command
1863 memset(dest, 128, m);
1864 // Connect the A/D to the peak-detected low-frequency path.
1865 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1866 // Now set up the SSC to get the ADC samples that are now streaming at us.
1867 FpgaSetupSsc();
1868
1869 SendForward(fwd_bit_count);
1870
1871 // Now do the acquisition
1872 i = 0;
1873 for(;;) {
1874 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1875 AT91C_BASE_SSC->SSC_THR = 0x43;
1876 }
1877 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1878 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1879 i++;
1880 if (i >= m) break;
1881 }
1882 }
1883 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1884 LED_D_OFF();
1885 }
1886
1887 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1888
1889 uint8_t fwd_bit_count;
1890
1891 //If password mode do login
1892 if (PwdMode == 1) EM4xLogin(Pwd);
1893
1894 forward_ptr = forwardLink_data;
1895 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1896 fwd_bit_count += Prepare_Addr( Address );
1897 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1898
1899 SendForward(fwd_bit_count);
1900
1901 //Wait for write to complete
1902 SpinDelay(20);
1903 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1904 LED_D_OFF();
1905 }
Proxmark3 GIT tracking
Impressum, Datenschutz