1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
13 #include "iso14443a.h"
17 #include "proxmark3.h"
21 #include "iso14443crc.h"
22 #include "crapto1/crapto1.h"
23 #include "mifareutil.h"
24 #include "mifaresniff.h"
26 #include "protocols.h"
28 #include "fpgaloader.h"
34 // DEMOD_MOD_FIRST_HALF,
35 // DEMOD_NOMOD_FIRST_HALF,
41 uint16_t collisionPos
;
48 uint32_t startTime
, endTime
;
63 STATE_START_OF_COMMUNICATION
,
79 uint32_t startTime
, endTime
;
84 static uint32_t iso14a_timeout
;
85 #define MAX_ISO14A_TIMEOUT 524288
89 // the block number for the ISO14443-4 PCB
90 static uint8_t iso14_pcb_blocknum
= 0;
95 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
96 #define REQUEST_GUARD_TIME (7000/16 + 1)
97 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
98 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
99 // bool LastCommandWasRequest = false;
102 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
104 // When the PM acts as reader and is receiving tag data, it takes
105 // 3 ticks delay in the AD converter
106 // 16 ticks until the modulation detector completes and sets curbit
107 // 8 ticks until bit_to_arm is assigned from curbit
108 // 8*16 ticks for the transfer from FPGA to ARM
109 // 4*16 ticks until we measure the time
110 // - 8*16 ticks because we measure the time of the previous transfer
111 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
113 // When the PM acts as a reader and is sending, it takes
114 // 4*16 ticks until we can write data to the sending hold register
115 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
116 // 8 ticks until the first transfer starts
117 // 8 ticks later the FPGA samples the data
118 // 1 tick to assign mod_sig_coil
119 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
121 // When the PM acts as tag and is receiving it takes
122 // 2 ticks delay in the RF part (for the first falling edge),
123 // 3 ticks for the A/D conversion,
124 // 8 ticks on average until the start of the SSC transfer,
125 // 8 ticks until the SSC samples the first data
126 // 7*16 ticks to complete the transfer from FPGA to ARM
127 // 8 ticks until the next ssp_clk rising edge
128 // 4*16 ticks until we measure the time
129 // - 8*16 ticks because we measure the time of the previous transfer
130 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
132 // The FPGA will report its internal sending delay in
133 uint16_t FpgaSendQueueDelay
;
134 // the 5 first bits are the number of bits buffered in mod_sig_buf
135 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
136 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
138 // When the PM acts as tag and is sending, it takes
139 // 4*16 + 8 ticks until we can write data to the sending hold register
140 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
141 // 8 ticks later the FPGA samples the first data
142 // + 16 ticks until assigned to mod_sig
143 // + 1 tick to assign mod_sig_coil
144 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
145 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8 + 8*16 + 8 + 16 + 1 + DELAY_FPGA_QUEUE)
147 // When the PM acts as sniffer and is receiving tag data, it takes
148 // 3 ticks A/D conversion
149 // 14 ticks to complete the modulation detection
150 // 8 ticks (on average) until the result is stored in to_arm
151 // + the delays in transferring data - which is the same for
152 // sniffing reader and tag data and therefore not relevant
153 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
155 // When the PM acts as sniffer and is receiving reader data, it takes
156 // 2 ticks delay in analogue RF receiver (for the falling edge of the
157 // start bit, which marks the start of the communication)
158 // 3 ticks A/D conversion
159 // 8 ticks on average until the data is stored in to_arm.
160 // + the delays in transferring data - which is the same for
161 // sniffing reader and tag data and therefore not relevant
162 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
164 //variables used for timing purposes:
165 //these are in ssp_clk cycles:
166 static uint32_t NextTransferTime
;
167 static uint32_t LastTimeProxToAirStart
;
168 static uint32_t LastProxToAirDuration
;
172 // CARD TO READER - manchester
173 // Sequence D: 11110000 modulation with subcarrier during first half
174 // Sequence E: 00001111 modulation with subcarrier during second half
175 // Sequence F: 00000000 no modulation with subcarrier
176 // READER TO CARD - miller
177 // Sequence X: 00001100 drop after half a period
178 // Sequence Y: 00000000 no drop
179 // Sequence Z: 11000000 drop at start
187 void iso14a_set_trigger(bool enable
) {
192 void iso14a_set_timeout(uint32_t timeout
) {
193 // adjust timeout by FPGA delays and 2 additional ssp_frames to detect SOF
194 iso14a_timeout
= timeout
+ (DELAY_AIR2ARM_AS_READER
+ DELAY_ARM2AIR_AS_READER
)/(16*8) + 2;
195 if(MF_DBGLEVEL
>= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", timeout
, timeout
/ 106);
199 uint32_t iso14a_get_timeout(void) {
200 return iso14a_timeout
- (DELAY_AIR2ARM_AS_READER
+ DELAY_ARM2AIR_AS_READER
)/(16*8) - 2;
203 //-----------------------------------------------------------------------------
204 // Generate the parity value for a byte sequence
206 //-----------------------------------------------------------------------------
207 void GetParity(const uint8_t *pbtCmd
, uint16_t iLen
, uint8_t *par
)
209 uint16_t paritybit_cnt
= 0;
210 uint16_t paritybyte_cnt
= 0;
211 uint8_t parityBits
= 0;
213 for (uint16_t i
= 0; i
< iLen
; i
++) {
214 // Generate the parity bits
215 parityBits
|= ((oddparity8(pbtCmd
[i
])) << (7-paritybit_cnt
));
216 if (paritybit_cnt
== 7) {
217 par
[paritybyte_cnt
] = parityBits
; // save 8 Bits parity
218 parityBits
= 0; // and advance to next Parity Byte
226 // save remaining parity bits
227 par
[paritybyte_cnt
] = parityBits
;
231 void AppendCrc14443a(uint8_t* data
, int len
)
233 ComputeCrc14443(CRC_14443_A
,data
,len
,data
+len
,data
+len
+1);
236 static void AppendCrc14443b(uint8_t* data
, int len
)
238 ComputeCrc14443(CRC_14443_B
,data
,len
,data
+len
,data
+len
+1);
242 //=============================================================================
243 // ISO 14443 Type A - Miller decoder
244 //=============================================================================
246 // This decoder is used when the PM3 acts as a tag.
247 // The reader will generate "pauses" by temporarily switching of the field.
248 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
249 // The FPGA does a comparison with a threshold and would deliver e.g.:
250 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
251 // The Miller decoder needs to identify the following sequences:
252 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
253 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
254 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
255 // Note 1: the bitstream may start at any time. We therefore need to sync.
256 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
257 //-----------------------------------------------------------------------------
260 // Lookup-Table to decide if 4 raw bits are a modulation.
261 // We accept the following:
262 // 0001 - a 3 tick wide pause
263 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
264 // 0111 - a 2 tick wide pause shifted left
265 // 1001 - a 2 tick wide pause shifted right
266 const bool Mod_Miller_LUT
[] = {
267 false, true, false, true, false, false, false, true,
268 false, true, false, false, false, false, false, false
270 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
271 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
273 static void UartReset()
275 Uart
.state
= STATE_UNSYNCD
;
277 Uart
.len
= 0; // number of decoded data bytes
278 Uart
.parityLen
= 0; // number of decoded parity bytes
279 Uart
.shiftReg
= 0; // shiftreg to hold decoded data bits
280 Uart
.parityBits
= 0; // holds 8 parity bits
285 static void UartInit(uint8_t *data
, uint8_t *parity
)
288 Uart
.parity
= parity
;
289 Uart
.fourBits
= 0x00000000; // clear the buffer for 4 Bits
293 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
294 static RAMFUNC
bool MillerDecoding(uint8_t bit
, uint32_t non_real_time
)
297 Uart
.fourBits
= (Uart
.fourBits
<< 8) | bit
;
299 if (Uart
.state
== STATE_UNSYNCD
) { // not yet synced
301 Uart
.syncBit
= 9999; // not set
302 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
303 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
304 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
305 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
306 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
307 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
308 if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 0)) == ISO14443A_STARTBIT_PATTERN
>> 0) Uart
.syncBit
= 7;
309 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 1)) == ISO14443A_STARTBIT_PATTERN
>> 1) Uart
.syncBit
= 6;
310 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 2)) == ISO14443A_STARTBIT_PATTERN
>> 2) Uart
.syncBit
= 5;
311 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 3)) == ISO14443A_STARTBIT_PATTERN
>> 3) Uart
.syncBit
= 4;
312 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 4)) == ISO14443A_STARTBIT_PATTERN
>> 4) Uart
.syncBit
= 3;
313 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 5)) == ISO14443A_STARTBIT_PATTERN
>> 5) Uart
.syncBit
= 2;
314 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 6)) == ISO14443A_STARTBIT_PATTERN
>> 6) Uart
.syncBit
= 1;
315 else if ((Uart
.fourBits
& (ISO14443A_STARTBIT_MASK
>> 7)) == ISO14443A_STARTBIT_PATTERN
>> 7) Uart
.syncBit
= 0;
317 if (Uart
.syncBit
!= 9999) { // found a sync bit
318 Uart
.startTime
= non_real_time
?non_real_time
:(GetCountSspClk() & 0xfffffff8);
319 Uart
.startTime
-= Uart
.syncBit
;
320 Uart
.endTime
= Uart
.startTime
;
321 Uart
.state
= STATE_START_OF_COMMUNICATION
;
326 if (IsMillerModulationNibble1(Uart
.fourBits
>> Uart
.syncBit
)) {
327 if (IsMillerModulationNibble2(Uart
.fourBits
>> Uart
.syncBit
)) { // Modulation in both halves - error
329 } else { // Modulation in first half = Sequence Z = logic "0"
330 if (Uart
.state
== STATE_MILLER_X
) { // error - must not follow after X
334 Uart
.shiftReg
= (Uart
.shiftReg
>> 1); // add a 0 to the shiftreg
335 Uart
.state
= STATE_MILLER_Z
;
336 Uart
.endTime
= Uart
.startTime
+ 8*(9*Uart
.len
+ Uart
.bitCount
+ 1) - 6;
337 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
338 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
339 Uart
.parityBits
<<= 1; // make room for the parity bit
340 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
343 if((Uart
.len
&0x0007) == 0) { // every 8 data bytes
344 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
351 if (IsMillerModulationNibble2(Uart
.fourBits
>> Uart
.syncBit
)) { // Modulation second half = Sequence X = logic "1"
353 Uart
.shiftReg
= (Uart
.shiftReg
>> 1) | 0x100; // add a 1 to the shiftreg
354 Uart
.state
= STATE_MILLER_X
;
355 Uart
.endTime
= Uart
.startTime
+ 8*(9*Uart
.len
+ Uart
.bitCount
+ 1) - 2;
356 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
357 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
358 Uart
.parityBits
<<= 1; // make room for the new parity bit
359 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
362 if ((Uart
.len
&0x0007) == 0) { // every 8 data bytes
363 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
367 } else { // no modulation in both halves - Sequence Y
368 if (Uart
.state
== STATE_MILLER_Z
|| Uart
.state
== STATE_MILLER_Y
) { // Y after logic "0" - End of Communication
369 Uart
.state
= STATE_UNSYNCD
;
370 Uart
.bitCount
--; // last "0" was part of EOC sequence
371 Uart
.shiftReg
<<= 1; // drop it
372 if(Uart
.bitCount
> 0) { // if we decoded some bits
373 Uart
.shiftReg
>>= (9 - Uart
.bitCount
); // right align them
374 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff); // add last byte to the output
375 Uart
.parityBits
<<= 1; // add a (void) parity bit
376 Uart
.parityBits
<<= (8 - (Uart
.len
&0x0007)); // left align parity bits
377 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // and store it
379 } else if (Uart
.len
& 0x0007) { // there are some parity bits to store
380 Uart
.parityBits
<<= (8 - (Uart
.len
&0x0007)); // left align remaining parity bits
381 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // and store them
384 return true; // we are finished with decoding the raw data sequence
386 UartReset(); // Nothing received - start over
389 if (Uart
.state
== STATE_START_OF_COMMUNICATION
) { // error - must not follow directly after SOC
391 } else { // a logic "0"
393 Uart
.shiftReg
= (Uart
.shiftReg
>> 1); // add a 0 to the shiftreg
394 Uart
.state
= STATE_MILLER_Y
;
395 if(Uart
.bitCount
>= 9) { // if we decoded a full byte (including parity)
396 Uart
.output
[Uart
.len
++] = (Uart
.shiftReg
& 0xff);
397 Uart
.parityBits
<<= 1; // make room for the parity bit
398 Uart
.parityBits
|= ((Uart
.shiftReg
>> 8) & 0x01); // store parity bit
401 if ((Uart
.len
&0x0007) == 0) { // every 8 data bytes
402 Uart
.parity
[Uart
.parityLen
++] = Uart
.parityBits
; // store 8 parity bits
412 return false; // not finished yet, need more data
417 //=============================================================================
418 // ISO 14443 Type A - Manchester decoder
419 //=============================================================================
421 // This decoder is used when the PM3 acts as a reader.
422 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
423 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
424 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
425 // The Manchester decoder needs to identify the following sequences:
426 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
427 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
428 // 8 ticks unmodulated: Sequence F = end of communication
429 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
430 // Note 1: the bitstream may start at any time. We therefore need to sync.
431 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
434 // Lookup-Table to decide if 4 raw bits are a modulation.
435 // We accept three or four "1" in any position
436 const bool Mod_Manchester_LUT
[] = {
437 false, false, false, false, false, false, false, true,
438 false, false, false, true, false, true, true, true
441 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
442 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
445 static void DemodReset()
447 Demod
.state
= DEMOD_UNSYNCD
;
448 Demod
.len
= 0; // number of decoded data bytes
450 Demod
.shiftReg
= 0; // shiftreg to hold decoded data bits
451 Demod
.parityBits
= 0; //
452 Demod
.collisionPos
= 0; // Position of collision bit
453 Demod
.twoBits
= 0xffff; // buffer for 2 Bits
459 static void DemodInit(uint8_t *data
, uint8_t *parity
)
462 Demod
.parity
= parity
;
466 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
467 static RAMFUNC
int ManchesterDecoding(uint8_t bit
, uint16_t offset
, uint32_t non_real_time
)
470 Demod
.twoBits
= (Demod
.twoBits
<< 8) | bit
;
472 if (Demod
.state
== DEMOD_UNSYNCD
) {
474 if (Demod
.highCnt
< 2) { // wait for a stable unmodulated signal
475 if (Demod
.twoBits
== 0x0000) {
481 Demod
.syncBit
= 0xFFFF; // not set
482 if ((Demod
.twoBits
& 0x7700) == 0x7000) Demod
.syncBit
= 7;
483 else if ((Demod
.twoBits
& 0x3B80) == 0x3800) Demod
.syncBit
= 6;
484 else if ((Demod
.twoBits
& 0x1DC0) == 0x1C00) Demod
.syncBit
= 5;
485 else if ((Demod
.twoBits
& 0x0EE0) == 0x0E00) Demod
.syncBit
= 4;
486 else if ((Demod
.twoBits
& 0x0770) == 0x0700) Demod
.syncBit
= 3;
487 else if ((Demod
.twoBits
& 0x03B8) == 0x0380) Demod
.syncBit
= 2;
488 else if ((Demod
.twoBits
& 0x01DC) == 0x01C0) Demod
.syncBit
= 1;
489 else if ((Demod
.twoBits
& 0x00EE) == 0x00E0) Demod
.syncBit
= 0;
490 if (Demod
.syncBit
!= 0xFFFF) {
491 Demod
.startTime
= non_real_time
?non_real_time
:(GetCountSspClk() & 0xfffffff8);
492 Demod
.startTime
-= Demod
.syncBit
;
493 Demod
.bitCount
= offset
; // number of decoded data bits
494 Demod
.state
= DEMOD_MANCHESTER_DATA
;
500 if (IsManchesterModulationNibble1(Demod
.twoBits
>> Demod
.syncBit
)) { // modulation in first half
501 if (IsManchesterModulationNibble2(Demod
.twoBits
>> Demod
.syncBit
)) { // ... and in second half = collision
502 if (!Demod
.collisionPos
) {
503 Demod
.collisionPos
= (Demod
.len
<< 3) + Demod
.bitCount
;
505 } // modulation in first half only - Sequence D = 1
507 Demod
.shiftReg
= (Demod
.shiftReg
>> 1) | 0x100; // in both cases, add a 1 to the shiftreg
508 if(Demod
.bitCount
== 9) { // if we decoded a full byte (including parity)
509 Demod
.output
[Demod
.len
++] = (Demod
.shiftReg
& 0xff);
510 Demod
.parityBits
<<= 1; // make room for the parity bit
511 Demod
.parityBits
|= ((Demod
.shiftReg
>> 8) & 0x01); // store parity bit
514 if((Demod
.len
&0x0007) == 0) { // every 8 data bytes
515 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // store 8 parity bits
516 Demod
.parityBits
= 0;
519 Demod
.endTime
= Demod
.startTime
+ 8*(9*Demod
.len
+ Demod
.bitCount
+ 1) - 4;
520 } else { // no modulation in first half
521 if (IsManchesterModulationNibble2(Demod
.twoBits
>> Demod
.syncBit
)) { // and modulation in second half = Sequence E = 0
523 Demod
.shiftReg
= (Demod
.shiftReg
>> 1); // add a 0 to the shiftreg
524 if(Demod
.bitCount
>= 9) { // if we decoded a full byte (including parity)
525 Demod
.output
[Demod
.len
++] = (Demod
.shiftReg
& 0xff);
526 Demod
.parityBits
<<= 1; // make room for the new parity bit
527 Demod
.parityBits
|= ((Demod
.shiftReg
>> 8) & 0x01); // store parity bit
530 if ((Demod
.len
&0x0007) == 0) { // every 8 data bytes
531 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // store 8 parity bits1
532 Demod
.parityBits
= 0;
535 Demod
.endTime
= Demod
.startTime
+ 8*(9*Demod
.len
+ Demod
.bitCount
+ 1);
536 } else { // no modulation in both halves - End of communication
537 if(Demod
.bitCount
> 0) { // there are some remaining data bits
538 Demod
.shiftReg
>>= (9 - Demod
.bitCount
); // right align the decoded bits
539 Demod
.output
[Demod
.len
++] = Demod
.shiftReg
& 0xff; // and add them to the output
540 Demod
.parityBits
<<= 1; // add a (void) parity bit
541 Demod
.parityBits
<<= (8 - (Demod
.len
&0x0007)); // left align remaining parity bits
542 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // and store them
544 } else if (Demod
.len
& 0x0007) { // there are some parity bits to store
545 Demod
.parityBits
<<= (8 - (Demod
.len
&0x0007)); // left align remaining parity bits
546 Demod
.parity
[Demod
.parityLen
++] = Demod
.parityBits
; // and store them
549 return true; // we are finished with decoding the raw data sequence
550 } else { // nothing received. Start over
558 return false; // not finished yet, need more data
561 //=============================================================================
562 // Finally, a `sniffer' for ISO 14443 Type A
563 // Both sides of communication!
564 //=============================================================================
566 //-----------------------------------------------------------------------------
567 // Record the sequence of commands sent by the reader to the tag, with
568 // triggering so that we start recording at the point that the tag is moved
570 //-----------------------------------------------------------------------------
571 void RAMFUNC
SnoopIso14443a(uint8_t param
) {
573 // bit 0 - trigger from first card answer
574 // bit 1 - trigger from first reader 7-bit request
578 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER
);
580 // Allocate memory from BigBuf for some buffers
581 // free all previous allocations first
584 // The command (reader -> tag) that we're receiving.
585 uint8_t *receivedCmd
= BigBuf_malloc(MAX_FRAME_SIZE
);
586 uint8_t *receivedCmdPar
= BigBuf_malloc(MAX_PARITY_SIZE
);
588 // The response (tag -> reader) that we're receiving.
589 uint8_t *receivedResponse
= BigBuf_malloc(MAX_FRAME_SIZE
);
590 uint8_t *receivedResponsePar
= BigBuf_malloc(MAX_PARITY_SIZE
);
592 // The DMA buffer, used to stream samples from the FPGA
593 uint8_t *dmaBuf
= BigBuf_malloc(DMA_BUFFER_SIZE
);
599 uint8_t *data
= dmaBuf
;
600 uint8_t previous_data
= 0;
603 bool TagIsActive
= false;
604 bool ReaderIsActive
= false;
606 // Set up the demodulator for tag -> reader responses.
607 DemodInit(receivedResponse
, receivedResponsePar
);
609 // Set up the demodulator for the reader -> tag commands
610 UartInit(receivedCmd
, receivedCmdPar
);
612 // Setup and start DMA.
613 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
);
615 // We won't start recording the frames that we acquire until we trigger;
616 // a good trigger condition to get started is probably when we see a
617 // response from the tag.
618 // triggered == false -- to wait first for card
619 bool triggered
= !(param
& 0x03);
621 // And now we loop, receiving samples.
622 for(uint32_t rsamples
= 0; true; ) {
625 DbpString("cancelled by button");
632 int register readBufDataP
= data
- dmaBuf
;
633 int register dmaBufDataP
= DMA_BUFFER_SIZE
- AT91C_BASE_PDC_SSC
->PDC_RCR
;
634 if (readBufDataP
<= dmaBufDataP
){
635 dataLen
= dmaBufDataP
- readBufDataP
;
637 dataLen
= DMA_BUFFER_SIZE
- readBufDataP
+ dmaBufDataP
;
639 // test for length of buffer
640 if(dataLen
> maxDataLen
) {
641 maxDataLen
= dataLen
;
642 if(dataLen
> (9 * DMA_BUFFER_SIZE
/ 10)) {
643 Dbprintf("blew circular buffer! dataLen=%d", dataLen
);
647 if(dataLen
< 1) continue;
649 // primary buffer was stopped( <-- we lost data!
650 if (!AT91C_BASE_PDC_SSC
->PDC_RCR
) {
651 AT91C_BASE_PDC_SSC
->PDC_RPR
= (uint32_t) dmaBuf
;
652 AT91C_BASE_PDC_SSC
->PDC_RCR
= DMA_BUFFER_SIZE
;
653 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen
); // temporary
655 // secondary buffer sets as primary, secondary buffer was stopped
656 if (!AT91C_BASE_PDC_SSC
->PDC_RNCR
) {
657 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
;
658 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
663 if (rsamples
& 0x01) { // Need two samples to feed Miller and Manchester-Decoder
665 if(!TagIsActive
) { // no need to try decoding reader data if the tag is sending
666 uint8_t readerdata
= (previous_data
& 0xF0) | (*data
>> 4);
667 if (MillerDecoding(readerdata
, (rsamples
-1)*4)) {
670 // check - if there is a short 7bit request from reader
671 if ((!triggered
) && (param
& 0x02) && (Uart
.len
== 1) && (Uart
.bitCount
== 7)) triggered
= true;
674 if (!LogTrace(receivedCmd
,
676 Uart
.startTime
*16 - DELAY_READER_AIR2ARM_AS_SNIFFER
,
677 Uart
.endTime
*16 - DELAY_READER_AIR2ARM_AS_SNIFFER
,
681 /* And ready to receive another command. */
683 /* And also reset the demod code, which might have been */
684 /* false-triggered by the commands from the reader. */
688 ReaderIsActive
= (Uart
.state
!= STATE_UNSYNCD
);
691 if(!ReaderIsActive
) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
692 uint8_t tagdata
= (previous_data
<< 4) | (*data
& 0x0F);
693 if(ManchesterDecoding(tagdata
, 0, (rsamples
-1)*4)) {
696 if (!LogTrace(receivedResponse
,
698 Demod
.startTime
*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER
,
699 Demod
.endTime
*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER
,
703 if ((!triggered
) && (param
& 0x01)) triggered
= true;
705 // And ready to receive another response.
707 // And reset the Miller decoder including itS (now outdated) input buffer
708 UartInit(receivedCmd
, receivedCmdPar
);
712 TagIsActive
= (Demod
.state
!= DEMOD_UNSYNCD
);
716 previous_data
= *data
;
719 if(data
== dmaBuf
+ DMA_BUFFER_SIZE
) {
724 DbpString("COMMAND FINISHED");
727 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen
, Uart
.state
, Uart
.len
);
728 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart
.output
[0]);
732 //-----------------------------------------------------------------------------
733 // Prepare tag messages
734 //-----------------------------------------------------------------------------
735 static void CodeIso14443aAsTagPar(const uint8_t *cmd
, uint16_t len
, uint8_t *parity
)
739 // Correction bit, might be removed when not needed
744 ToSendStuffBit(1); // 1
750 ToSend
[++ToSendMax
] = SEC_D
;
751 LastProxToAirDuration
= 8 * ToSendMax
- 4;
753 for(uint16_t i
= 0; i
< len
; i
++) {
757 for(uint16_t j
= 0; j
< 8; j
++) {
759 ToSend
[++ToSendMax
] = SEC_D
;
761 ToSend
[++ToSendMax
] = SEC_E
;
766 // Get the parity bit
767 if (parity
[i
>>3] & (0x80>>(i
&0x0007))) {
768 ToSend
[++ToSendMax
] = SEC_D
;
769 LastProxToAirDuration
= 8 * ToSendMax
- 4;
771 ToSend
[++ToSendMax
] = SEC_E
;
772 LastProxToAirDuration
= 8 * ToSendMax
;
777 ToSend
[++ToSendMax
] = SEC_F
;
779 // Convert from last byte pos to length
784 static void Code4bitAnswerAsTag(uint8_t cmd
)
790 // Correction bit, might be removed when not needed
795 ToSendStuffBit(1); // 1
801 ToSend
[++ToSendMax
] = SEC_D
;
804 for(i
= 0; i
< 4; i
++) {
806 ToSend
[++ToSendMax
] = SEC_D
;
807 LastProxToAirDuration
= 8 * ToSendMax
- 4;
809 ToSend
[++ToSendMax
] = SEC_E
;
810 LastProxToAirDuration
= 8 * ToSendMax
;
816 ToSend
[++ToSendMax
] = SEC_F
;
818 // Convert from last byte pos to length
823 static uint8_t *LastReaderTraceTime
= NULL
;
825 static void EmLogTraceReader(void) {
826 // remember last reader trace start to fix timing info later
827 LastReaderTraceTime
= BigBuf_get_addr() + BigBuf_get_traceLen();
828 LogTrace(Uart
.output
, Uart
.len
, Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
, Uart
.parity
, true);
832 static void FixLastReaderTraceTime(uint32_t tag_StartTime
) {
833 uint32_t reader_EndTime
= Uart
.endTime
*16 - DELAY_AIR2ARM_AS_TAG
;
834 uint32_t reader_StartTime
= Uart
.startTime
*16 - DELAY_AIR2ARM_AS_TAG
;
835 uint16_t reader_modlen
= reader_EndTime
- reader_StartTime
;
836 uint16_t approx_fdt
= tag_StartTime
- reader_EndTime
;
837 uint16_t exact_fdt
= (approx_fdt
- 20 + 32)/64 * 64 + 20;
838 reader_StartTime
= tag_StartTime
- exact_fdt
- reader_modlen
;
839 LastReaderTraceTime
[0] = (reader_StartTime
>> 0) & 0xff;
840 LastReaderTraceTime
[1] = (reader_StartTime
>> 8) & 0xff;
841 LastReaderTraceTime
[2] = (reader_StartTime
>> 16) & 0xff;
842 LastReaderTraceTime
[3] = (reader_StartTime
>> 24) & 0xff;
846 static void EmLogTraceTag(uint8_t *tag_data
, uint16_t tag_len
, uint8_t *tag_Parity
, uint32_t ProxToAirDuration
) {
847 uint32_t tag_StartTime
= LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_TAG
;
848 uint32_t tag_EndTime
= (LastTimeProxToAirStart
+ ProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_TAG
;
849 LogTrace(tag_data
, tag_len
, tag_StartTime
, tag_EndTime
, tag_Parity
, false);
850 FixLastReaderTraceTime(tag_StartTime
);
854 //-----------------------------------------------------------------------------
855 // Wait for commands from reader
856 // Stop when button is pressed
857 // Or return true when command is captured
858 //-----------------------------------------------------------------------------
859 static int GetIso14443aCommandFromReader(uint8_t *received
, uint8_t *parity
, int *len
)
861 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
862 // only, since we are receiving, not transmitting).
863 // Signal field is off with the appropriate LED
865 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
867 // Now run a `software UART' on the stream of incoming samples.
868 UartInit(received
, parity
);
871 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
876 if(BUTTON_PRESS()) return false;
878 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
879 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
880 if(MillerDecoding(b
, 0)) {
890 static int EmSend4bitEx(uint8_t resp
);
891 int EmSend4bit(uint8_t resp
);
892 static int EmSendCmdExPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
);
893 int EmSendCmdEx(uint8_t *resp
, uint16_t respLen
);
894 int EmSendPrecompiledCmd(tag_response_info_t
*response_info
);
897 static bool prepare_tag_modulation(tag_response_info_t
* response_info
, size_t max_buffer_size
) {
898 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
899 // This will need the following byte array for a modulation sequence
900 // 144 data bits (18 * 8)
903 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
904 // 1 just for the case
906 // 166 bytes, since every bit that needs to be send costs us a byte
910 // Prepare the tag modulation bits from the message
911 GetParity(response_info
->response
, response_info
->response_n
, &(response_info
->par
));
912 CodeIso14443aAsTagPar(response_info
->response
,response_info
->response_n
, &(response_info
->par
));
914 // Make sure we do not exceed the free buffer space
915 if (ToSendMax
> max_buffer_size
) {
916 Dbprintf("Out of memory, when modulating bits for tag answer:");
917 Dbhexdump(response_info
->response_n
, response_info
->response
, false);
921 // Copy the byte array, used for this modulation to the buffer position
922 memcpy(response_info
->modulation
, ToSend
, ToSendMax
);
924 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
925 response_info
->modulation_n
= ToSendMax
;
926 response_info
->ProxToAirDuration
= LastProxToAirDuration
;
932 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
933 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
934 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits for the modulation
935 // -> need 273 bytes buffer
936 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
938 bool prepare_allocated_tag_modulation(tag_response_info_t
* response_info
, uint8_t **buffer
, size_t *max_buffer_size
) {
940 // Retrieve and store the current buffer index
941 response_info
->modulation
= *buffer
;
943 // Forward the prepare tag modulation function to the inner function
944 if (prepare_tag_modulation(response_info
, *max_buffer_size
)) {
945 // Update the free buffer offset and the remaining buffer size
946 *buffer
+= ToSendMax
;
947 *max_buffer_size
-= ToSendMax
;
954 //-----------------------------------------------------------------------------
955 // Main loop of simulated tag: receive commands from reader, decide what
956 // response to send, and send it.
957 //-----------------------------------------------------------------------------
958 void SimulateIso14443aTag(int tagType
, int uid_1st
, int uid_2nd
, byte_t
* data
)
962 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
963 uint8_t response1
[2];
966 case 1: { // MIFARE Classic
967 // Says: I am Mifare 1k - original line
972 case 2: { // MIFARE Ultralight
973 // Says: I am a stupid memory tag, no crypto
978 case 3: { // MIFARE DESFire
979 // Says: I am a DESFire tag, ph33r me
984 case 4: { // ISO/IEC 14443-4
985 // Says: I am a javacard (JCOP)
990 case 5: { // MIFARE TNP3XXX
997 Dbprintf("Error: unkown tagtype (%d)",tagType
);
1002 // The second response contains the (mandatory) first 24 bits of the UID
1003 uint8_t response2
[5] = {0x00};
1005 // Check if the uid uses the (optional) part
1006 uint8_t response2a
[5] = {0x00};
1009 response2
[0] = 0x88;
1010 num_to_bytes(uid_1st
,3,response2
+1);
1011 num_to_bytes(uid_2nd
,4,response2a
);
1012 response2a
[4] = response2a
[0] ^ response2a
[1] ^ response2a
[2] ^ response2a
[3];
1014 // Configure the ATQA and SAK accordingly
1015 response1
[0] |= 0x40;
1018 num_to_bytes(uid_1st
,4,response2
);
1019 // Configure the ATQA and SAK accordingly
1020 response1
[0] &= 0xBF;
1024 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1025 response2
[4] = response2
[0] ^ response2
[1] ^ response2
[2] ^ response2
[3];
1027 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1028 uint8_t response3
[3] = {0x00};
1030 ComputeCrc14443(CRC_14443_A
, response3
, 1, &response3
[1], &response3
[2]);
1032 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1033 uint8_t response3a
[3] = {0x00};
1034 response3a
[0] = sak
& 0xFB;
1035 ComputeCrc14443(CRC_14443_A
, response3a
, 1, &response3a
[1], &response3a
[2]);
1037 uint8_t response5
[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1038 uint8_t response6
[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1039 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1040 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1041 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1042 // TC(1) = 0x02: CID supported, NAD not supported
1043 ComputeCrc14443(CRC_14443_A
, response6
, 4, &response6
[4], &response6
[5]);
1045 #define TAG_RESPONSE_COUNT 7
1046 tag_response_info_t responses
[TAG_RESPONSE_COUNT
] = {
1047 { .response
= response1
, .response_n
= sizeof(response1
) }, // Answer to request - respond with card type
1048 { .response
= response2
, .response_n
= sizeof(response2
) }, // Anticollision cascade1 - respond with uid
1049 { .response
= response2a
, .response_n
= sizeof(response2a
) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1050 { .response
= response3
, .response_n
= sizeof(response3
) }, // Acknowledge select - cascade 1
1051 { .response
= response3a
, .response_n
= sizeof(response3a
) }, // Acknowledge select - cascade 2
1052 { .response
= response5
, .response_n
= sizeof(response5
) }, // Authentication answer (random nonce)
1053 { .response
= response6
, .response_n
= sizeof(response6
) }, // dummy ATS (pseudo-ATR), answer to RATS
1056 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1057 // Such a response is less time critical, so we can prepare them on the fly
1058 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1059 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1060 uint8_t dynamic_response_buffer
[DYNAMIC_RESPONSE_BUFFER_SIZE
];
1061 uint8_t dynamic_modulation_buffer
[DYNAMIC_MODULATION_BUFFER_SIZE
];
1062 tag_response_info_t dynamic_response_info
= {
1063 .response
= dynamic_response_buffer
,
1065 .modulation
= dynamic_modulation_buffer
,
1069 // We need to listen to the high-frequency, peak-detected path.
1070 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
1072 BigBuf_free_keep_EM();
1074 // allocate buffers:
1075 uint8_t *receivedCmd
= BigBuf_malloc(MAX_FRAME_SIZE
);
1076 uint8_t *receivedCmdPar
= BigBuf_malloc(MAX_PARITY_SIZE
);
1077 uint8_t *free_buffer_pointer
= BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE
);
1078 size_t free_buffer_size
= ALLOCATED_TAG_MODULATION_BUFFER_SIZE
;
1083 // Prepare the responses of the anticollision phase
1084 // there will be not enough time to do this at the moment the reader sends it REQA
1085 for (size_t i
=0; i
<TAG_RESPONSE_COUNT
; i
++) {
1086 prepare_allocated_tag_modulation(&responses
[i
], &free_buffer_pointer
, &free_buffer_size
);
1091 // To control where we are in the protocol
1095 // Just to allow some checks
1101 tag_response_info_t
* p_response
;
1105 // Clean receive command buffer
1106 if(!GetIso14443aCommandFromReader(receivedCmd
, receivedCmdPar
, &len
)) {
1107 DbpString("Button press");
1113 // Okay, look at the command now.
1115 if(receivedCmd
[0] == 0x26) { // Received a REQUEST
1116 p_response
= &responses
[0]; order
= 1;
1117 } else if(receivedCmd
[0] == 0x52) { // Received a WAKEUP
1118 p_response
= &responses
[0]; order
= 6;
1119 } else if(receivedCmd
[1] == 0x20 && receivedCmd
[0] == 0x93) { // Received request for UID (cascade 1)
1120 p_response
= &responses
[1]; order
= 2;
1121 } else if(receivedCmd
[1] == 0x20 && receivedCmd
[0] == 0x95) { // Received request for UID (cascade 2)
1122 p_response
= &responses
[2]; order
= 20;
1123 } else if(receivedCmd
[1] == 0x70 && receivedCmd
[0] == 0x93) { // Received a SELECT (cascade 1)
1124 p_response
= &responses
[3]; order
= 3;
1125 } else if(receivedCmd
[1] == 0x70 && receivedCmd
[0] == 0x95) { // Received a SELECT (cascade 2)
1126 p_response
= &responses
[4]; order
= 30;
1127 } else if(receivedCmd
[0] == 0x30) { // Received a (plain) READ
1128 EmSendCmdEx(data
+(4*receivedCmd
[1]),16);
1129 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1130 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1132 } else if(receivedCmd
[0] == 0x50) { // Received a HALT
1134 } else if(receivedCmd
[0] == 0x60 || receivedCmd
[0] == 0x61) { // Received an authentication request
1135 p_response
= &responses
[5]; order
= 7;
1136 } else if(receivedCmd
[0] == 0xE0) { // Received a RATS request
1137 if (tagType
== 1 || tagType
== 2) { // RATS not supported
1138 EmSend4bit(CARD_NACK_NA
);
1141 p_response
= &responses
[6]; order
= 70;
1143 } else if (order
== 7 && len
== 8) { // Received {nr] and {ar} (part of authentication)
1144 uint32_t nr
= bytes_to_num(receivedCmd
,4);
1145 uint32_t ar
= bytes_to_num(receivedCmd
+4,4);
1146 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr
,ar
);
1148 // Check for ISO 14443A-4 compliant commands, look at left nibble
1149 switch (receivedCmd
[0]) {
1152 case 0x0A: { // IBlock (command)
1153 dynamic_response_info
.response
[0] = receivedCmd
[0];
1154 dynamic_response_info
.response
[1] = 0x00;
1155 dynamic_response_info
.response
[2] = 0x90;
1156 dynamic_response_info
.response
[3] = 0x00;
1157 dynamic_response_info
.response_n
= 4;
1161 case 0x1B: { // Chaining command
1162 dynamic_response_info
.response
[0] = 0xaa | ((receivedCmd
[0]) & 1);
1163 dynamic_response_info
.response_n
= 2;
1168 dynamic_response_info
.response
[0] = receivedCmd
[0] ^ 0x11;
1169 dynamic_response_info
.response_n
= 2;
1173 memcpy(dynamic_response_info
.response
,"\xAB\x00",2);
1174 dynamic_response_info
.response_n
= 2;
1178 case 0xC2: { // Readers sends deselect command
1179 memcpy(dynamic_response_info
.response
,"\xCA\x00",2);
1180 dynamic_response_info
.response_n
= 2;
1184 // Never seen this command before
1185 Dbprintf("Received unknown command (len=%d):",len
);
1186 Dbhexdump(len
,receivedCmd
,false);
1188 dynamic_response_info
.response_n
= 0;
1192 if (dynamic_response_info
.response_n
> 0) {
1193 // Copy the CID from the reader query
1194 dynamic_response_info
.response
[1] = receivedCmd
[1];
1196 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1197 AppendCrc14443a(dynamic_response_info
.response
,dynamic_response_info
.response_n
);
1198 dynamic_response_info
.response_n
+= 2;
1200 if (prepare_tag_modulation(&dynamic_response_info
,DYNAMIC_MODULATION_BUFFER_SIZE
) == false) {
1201 Dbprintf("Error preparing tag response");
1204 p_response
= &dynamic_response_info
;
1208 // Count number of wakeups received after a halt
1209 if(order
== 6 && lastorder
== 5) { happened
++; }
1211 // Count number of other messages after a halt
1212 if(order
!= 6 && lastorder
== 5) { happened2
++; }
1214 if(cmdsRecvd
> 999) {
1215 DbpString("1000 commands later...");
1220 if (p_response
!= NULL
) {
1221 EmSendPrecompiledCmd(p_response
);
1224 if (!get_tracing()) {
1225 Dbprintf("Trace Full. Simulation stopped.");
1230 Dbprintf("%x %x %x", happened
, happened2
, cmdsRecvd
);
1232 BigBuf_free_keep_EM();
1236 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1237 // of bits specified in the delay parameter.
1238 static void PrepareDelayedTransfer(uint16_t delay
)
1240 uint8_t bitmask
= 0;
1241 uint8_t bits_to_shift
= 0;
1242 uint8_t bits_shifted
= 0;
1246 for (uint16_t i
= 0; i
< delay
; i
++) {
1247 bitmask
|= (0x01 << i
);
1249 ToSend
[ToSendMax
++] = 0x00;
1250 for (uint16_t i
= 0; i
< ToSendMax
; i
++) {
1251 bits_to_shift
= ToSend
[i
] & bitmask
;
1252 ToSend
[i
] = ToSend
[i
] >> delay
;
1253 ToSend
[i
] = ToSend
[i
] | (bits_shifted
<< (8 - delay
));
1254 bits_shifted
= bits_to_shift
;
1260 //-------------------------------------------------------------------------------------
1261 // Transmit the command (to the tag) that was placed in ToSend[].
1262 // Parameter timing:
1263 // if NULL: transfer at next possible time, taking into account
1264 // request guard time, startup frame guard time and frame delay time
1265 // if == 0: transfer immediately and return time of transfer
1266 // if != 0: delay transfer until time specified
1267 //-------------------------------------------------------------------------------------
1268 static void TransmitFor14443a(const uint8_t *cmd
, uint16_t len
, uint32_t *timing
)
1271 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_READER_MOD
);
1273 uint32_t ThisTransferTime
= 0;
1276 if(*timing
== 0) { // Measure time
1277 *timing
= (GetCountSspClk() + 8) & 0xfffffff8;
1279 PrepareDelayedTransfer(*timing
& 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1281 if(MF_DBGLEVEL
>= 4 && GetCountSspClk() >= (*timing
& 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1282 while(GetCountSspClk() < (*timing
& 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1283 LastTimeProxToAirStart
= *timing
;
1285 ThisTransferTime
= ((MAX(NextTransferTime
, GetCountSspClk()) & 0xfffffff8) + 8);
1286 while(GetCountSspClk() < ThisTransferTime
);
1287 LastTimeProxToAirStart
= ThisTransferTime
;
1291 AT91C_BASE_SSC
->SSC_THR
= SEC_Y
;
1295 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1296 AT91C_BASE_SSC
->SSC_THR
= cmd
[c
];
1304 NextTransferTime
= MAX(NextTransferTime
, LastTimeProxToAirStart
+ REQUEST_GUARD_TIME
);
1308 //-----------------------------------------------------------------------------
1309 // Prepare reader command (in bits, support short frames) to send to FPGA
1310 //-----------------------------------------------------------------------------
1311 static void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd
, uint16_t bits
, const uint8_t *parity
)
1319 // Start of Communication (Seq. Z)
1320 ToSend
[++ToSendMax
] = SEC_Z
;
1321 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1324 size_t bytecount
= nbytes(bits
);
1325 // Generate send structure for the data bits
1326 for (i
= 0; i
< bytecount
; i
++) {
1327 // Get the current byte to send
1329 size_t bitsleft
= MIN((bits
-(i
*8)),8);
1331 for (j
= 0; j
< bitsleft
; j
++) {
1334 ToSend
[++ToSendMax
] = SEC_X
;
1335 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 2;
1340 ToSend
[++ToSendMax
] = SEC_Z
;
1341 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1344 ToSend
[++ToSendMax
] = SEC_Y
;
1351 // Only transmit parity bit if we transmitted a complete byte
1352 if (j
== 8 && parity
!= NULL
) {
1353 // Get the parity bit
1354 if (parity
[i
>>3] & (0x80 >> (i
&0x0007))) {
1356 ToSend
[++ToSendMax
] = SEC_X
;
1357 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 2;
1362 ToSend
[++ToSendMax
] = SEC_Z
;
1363 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1366 ToSend
[++ToSendMax
] = SEC_Y
;
1373 // End of Communication: Logic 0 followed by Sequence Y
1376 ToSend
[++ToSendMax
] = SEC_Z
;
1377 LastProxToAirDuration
= 8 * (ToSendMax
+1) - 6;
1380 ToSend
[++ToSendMax
] = SEC_Y
;
1383 ToSend
[++ToSendMax
] = SEC_Y
;
1385 // Convert to length of command:
1390 //-----------------------------------------------------------------------------
1391 // Wait for commands from reader
1392 // Stop when button is pressed (return 1) or field was gone (return 2)
1393 // Or return 0 when command is captured
1394 //-----------------------------------------------------------------------------
1395 int EmGetCmd(uint8_t *received
, uint16_t *len
, uint8_t *parity
)
1399 uint32_t timer
= 0, vtime
= 0;
1403 // Set ADC to read field strength
1404 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_SWRST
;
1405 AT91C_BASE_ADC
->ADC_MR
=
1406 ADC_MODE_PRESCALE(63) |
1407 ADC_MODE_STARTUP_TIME(1) |
1408 ADC_MODE_SAMPLE_HOLD_TIME(15);
1409 AT91C_BASE_ADC
->ADC_CHER
= ADC_CHANNEL(ADC_CHAN_HF_LOW
);
1411 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_START
;
1413 // Run a 'software UART' on the stream of incoming samples.
1414 UartInit(received
, parity
);
1416 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN
1418 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1419 AT91C_BASE_SSC
->SSC_THR
= SEC_F
;
1420 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1422 } while (GetCountSspClk() < LastTimeProxToAirStart
+ LastProxToAirDuration
+ (FpgaSendQueueDelay
>>3));
1424 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1425 // only, since we are receiving, not transmitting).
1426 // Signal field is off with the appropriate LED
1428 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_LISTEN
);
1433 if (BUTTON_PRESS()) return 1;
1435 // test if the field exists
1436 if (AT91C_BASE_ADC
->ADC_SR
& ADC_END_OF_CONVERSION(ADC_CHAN_HF_LOW
)) {
1438 analogAVG
+= AT91C_BASE_ADC
->ADC_CDR
[ADC_CHAN_HF_LOW
];
1439 AT91C_BASE_ADC
->ADC_CR
= AT91C_ADC_START
;
1440 if (analogCnt
>= 32) {
1441 if ((MAX_ADC_HF_VOLTAGE_LOW
* (analogAVG
/ analogCnt
) >> 10) < MF_MINFIELDV
) {
1442 vtime
= GetTickCount();
1443 if (!timer
) timer
= vtime
;
1444 // 50ms no field --> card to idle state
1445 if (vtime
- timer
> 50) return 2;
1447 if (timer
) timer
= 0;
1453 // receive and test the miller decoding
1454 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1455 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1456 if(MillerDecoding(b
, 0)) {
1467 static int EmSendCmd14443aRaw(uint8_t *resp
, uint16_t respLen
)
1471 bool correctionNeeded
;
1473 // Modulate Manchester
1474 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_TAGSIM_MOD
);
1476 // include correction bit if necessary
1477 if (Uart
.bitCount
== 7)
1479 // Short tags (7 bits) don't have parity, determine the correct value from MSB
1480 correctionNeeded
= Uart
.output
[0] & 0x40;
1484 // Look at the last parity bit
1485 correctionNeeded
= Uart
.parity
[(Uart
.len
-1)/8] & (0x80 >> ((Uart
.len
-1) & 7));
1488 if(correctionNeeded
) {
1489 // 1236, so correction bit needed
1495 // clear receiving shift register and holding register
1496 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1497 b
= AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1498 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1499 b
= AT91C_BASE_SSC
->SSC_RHR
; (void) b
;
1501 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1502 for (uint16_t j
= 0; j
< 5; j
++) { // allow timeout - better late than never
1503 while(!(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
));
1504 if (AT91C_BASE_SSC
->SSC_RHR
) break;
1507 LastTimeProxToAirStart
= (GetCountSspClk() & 0xfffffff8) + (correctionNeeded
?8:0);
1510 for(; i
< respLen
; ) {
1511 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1512 AT91C_BASE_SSC
->SSC_THR
= resp
[i
++];
1513 FpgaSendQueueDelay
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1516 if(BUTTON_PRESS()) {
1525 static int EmSend4bitEx(uint8_t resp
){
1526 Code4bitAnswerAsTag(resp
);
1527 int res
= EmSendCmd14443aRaw(ToSend
, ToSendMax
);
1528 // do the tracing for the previous reader request and this tag answer:
1529 EmLogTraceTag(&resp
, 1, NULL
, LastProxToAirDuration
);
1534 int EmSend4bit(uint8_t resp
){
1535 return EmSend4bitEx(resp
);
1539 static int EmSendCmdExPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
){
1540 CodeIso14443aAsTagPar(resp
, respLen
, par
);
1541 int res
= EmSendCmd14443aRaw(ToSend
, ToSendMax
);
1542 // do the tracing for the previous reader request and this tag answer:
1543 EmLogTraceTag(resp
, respLen
, par
, LastProxToAirDuration
);
1548 int EmSendCmdEx(uint8_t *resp
, uint16_t respLen
){
1549 uint8_t par
[MAX_PARITY_SIZE
];
1550 GetParity(resp
, respLen
, par
);
1551 return EmSendCmdExPar(resp
, respLen
, par
);
1555 int EmSendCmd(uint8_t *resp
, uint16_t respLen
){
1556 uint8_t par
[MAX_PARITY_SIZE
];
1557 GetParity(resp
, respLen
, par
);
1558 return EmSendCmdExPar(resp
, respLen
, par
);
1562 int EmSendCmdPar(uint8_t *resp
, uint16_t respLen
, uint8_t *par
){
1563 return EmSendCmdExPar(resp
, respLen
, par
);
1567 int EmSendPrecompiledCmd(tag_response_info_t
*response_info
) {
1568 int ret
= EmSendCmd14443aRaw(response_info
->modulation
, response_info
->modulation_n
);
1569 // do the tracing for the previous reader request and this tag answer:
1570 EmLogTraceTag(response_info
->response
, response_info
->response_n
, &(response_info
->par
), response_info
->ProxToAirDuration
);
1575 //-----------------------------------------------------------------------------
1576 // Wait a certain time for tag response
1577 // If a response is captured return true
1578 // If it takes too long return false
1579 //-----------------------------------------------------------------------------
1580 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse
, uint8_t *receivedResponsePar
, uint16_t offset
)
1584 // Set FPGA mode to "reader listen mode", no modulation (listen
1585 // only, since we are receiving, not transmitting).
1586 // Signal field is on with the appropriate LED
1588 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_READER_LISTEN
);
1590 // Now get the answer from the card
1591 DemodInit(receivedResponse
, receivedResponsePar
);
1594 uint8_t b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1600 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1601 b
= (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1602 if(ManchesterDecoding(b
, offset
, 0)) {
1603 NextTransferTime
= MAX(NextTransferTime
, Demod
.endTime
- (DELAY_AIR2ARM_AS_READER
+ DELAY_ARM2AIR_AS_READER
)/16 + FRAME_DELAY_TIME_PICC_TO_PCD
);
1605 } else if (c
++ > iso14a_timeout
&& Demod
.state
== DEMOD_UNSYNCD
) {
1613 void ReaderTransmitBitsPar(uint8_t* frame
, uint16_t bits
, uint8_t *par
, uint32_t *timing
)
1615 CodeIso14443aBitsAsReaderPar(frame
, bits
, par
);
1617 // Send command to tag
1618 TransmitFor14443a(ToSend
, ToSendMax
, timing
);
1622 // Log reader command in trace buffer
1623 LogTrace(frame
, nbytes(bits
), LastTimeProxToAirStart
*16 + DELAY_ARM2AIR_AS_READER
, (LastTimeProxToAirStart
+ LastProxToAirDuration
)*16 + DELAY_ARM2AIR_AS_READER
, par
, true);
1627 void ReaderTransmitPar(uint8_t* frame
, uint16_t len
, uint8_t *par
, uint32_t *timing
)
1629 ReaderTransmitBitsPar(frame
, len
*8, par
, timing
);
1633 static void ReaderTransmitBits(uint8_t* frame
, uint16_t len
, uint32_t *timing
)
1635 // Generate parity and redirect
1636 uint8_t par
[MAX_PARITY_SIZE
];
1637 GetParity(frame
, len
/8, par
);
1638 ReaderTransmitBitsPar(frame
, len
, par
, timing
);
1642 void ReaderTransmit(uint8_t* frame
, uint16_t len
, uint32_t *timing
)
1644 // Generate parity and redirect
1645 uint8_t par
[MAX_PARITY_SIZE
];
1646 GetParity(frame
, len
, par
);
1647 ReaderTransmitBitsPar(frame
, len
*8, par
, timing
);
1651 static int ReaderReceiveOffset(uint8_t* receivedAnswer
, uint16_t offset
, uint8_t *parity
)
1653 if (!GetIso14443aAnswerFromTag(receivedAnswer
, parity
, offset
)) return false;
1654 LogTrace(receivedAnswer
, Demod
.len
, Demod
.startTime
*16 - DELAY_AIR2ARM_AS_READER
, Demod
.endTime
*16 - DELAY_AIR2ARM_AS_READER
, parity
, false);
1659 int ReaderReceive(uint8_t *receivedAnswer
, uint8_t *parity
)
1661 if (!GetIso14443aAnswerFromTag(receivedAnswer
, parity
, 0)) return false;
1662 LogTrace(receivedAnswer
, Demod
.len
, Demod
.startTime
*16 - DELAY_AIR2ARM_AS_READER
, Demod
.endTime
*16 - DELAY_AIR2ARM_AS_READER
, parity
, false);
1667 static void iso14a_set_ATS_times(uint8_t *ats
) {
1673 if (ats
[0] > 1) { // there is a format byte T0
1674 if ((ats
[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
1675 if ((ats
[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
1680 fwi
= (tb1
& 0xf0) >> 4; // frame waiting time integer (FWI)
1682 fwt
= 256 * 16 * (1 << fwi
); // frame waiting time (FWT) in 1/fc
1683 iso14a_set_timeout(fwt
/(8*16));
1685 sfgi
= tb1
& 0x0f; // startup frame guard time integer (SFGI)
1686 if (sfgi
!= 0 && sfgi
!= 15) {
1687 sfgt
= 256 * 16 * (1 << sfgi
); // startup frame guard time (SFGT) in 1/fc
1688 NextTransferTime
= MAX(NextTransferTime
, Demod
.endTime
+ (sfgt
- DELAY_AIR2ARM_AS_READER
- DELAY_ARM2AIR_AS_READER
)/16);
1695 static int GetATQA(uint8_t *resp
, uint8_t *resp_par
) {
1697 #define WUPA_RETRY_TIMEOUT 10 // 10ms
1698 uint8_t wupa
[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1700 uint32_t save_iso14a_timeout
= iso14a_get_timeout();
1701 iso14a_set_timeout(1236/(16*8)+1); // response to WUPA is expected at exactly 1236/fc. No need to wait longer.
1703 uint32_t start_time
= GetTickCount();
1706 // we may need several tries if we did send an unknown command or a wrong authentication before...
1708 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1709 ReaderTransmitBitsPar(wupa
, 7, NULL
, NULL
);
1711 len
= ReaderReceive(resp
, resp_par
);
1712 } while (len
== 0 && GetTickCount() <= start_time
+ WUPA_RETRY_TIMEOUT
);
1714 iso14a_set_timeout(save_iso14a_timeout
);
1719 // performs iso14443a anticollision (optional) and card select procedure
1720 // fills the uid and cuid pointer unless NULL
1721 // fills the card info record unless NULL
1722 // if anticollision is false, then the UID must be provided in uid_ptr[]
1723 // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1724 // requests ATS unless no_rats is true
1725 int iso14443a_select_card(byte_t
*uid_ptr
, iso14a_card_select_t
*p_hi14a_card
, uint32_t *cuid_ptr
, bool anticollision
, uint8_t num_cascades
, bool no_rats
) {
1726 uint8_t sel_all
[] = { 0x93,0x20 };
1727 uint8_t sel_uid
[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1728 uint8_t rats
[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1729 uint8_t resp
[MAX_FRAME_SIZE
]; // theoretically. A usual RATS will be much smaller
1730 uint8_t resp_par
[MAX_PARITY_SIZE
];
1732 size_t uid_resp_len
;
1734 uint8_t sak
= 0x04; // cascade uid
1735 int cascade_level
= 0;
1740 p_hi14a_card
->uidlen
= 0;
1741 memset(p_hi14a_card
->uid
, 0, 10);
1742 p_hi14a_card
->ats_len
= 0;
1745 if (!GetATQA(resp
, resp_par
)) {
1750 memcpy(p_hi14a_card
->atqa
, resp
, 2);
1753 if (anticollision
) {
1756 memset(uid_ptr
,0,10);
1760 // check for proprietary anticollision:
1761 if ((resp
[0] & 0x1F) == 0) {
1765 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1766 // which case we need to make a cascade 2 request and select - this is a long UID
1767 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1768 for(; sak
& 0x04; cascade_level
++) {
1769 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1770 sel_uid
[0] = sel_all
[0] = 0x93 + cascade_level
* 2;
1772 if (anticollision
) {
1774 ReaderTransmit(sel_all
, sizeof(sel_all
), NULL
);
1775 if (!ReaderReceive(resp
, resp_par
)) {
1779 if (Demod
.collisionPos
) { // we had a collision and need to construct the UID bit by bit
1780 memset(uid_resp
, 0, 4);
1781 uint16_t uid_resp_bits
= 0;
1782 uint16_t collision_answer_offset
= 0;
1783 // anti-collision-loop:
1784 while (Demod
.collisionPos
) {
1785 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod
.collisionPos
);
1786 for (uint16_t i
= collision_answer_offset
; i
< Demod
.collisionPos
; i
++, uid_resp_bits
++) { // add valid UID bits before collision point
1787 uint16_t UIDbit
= (resp
[i
/8] >> (i
% 8)) & 0x01;
1788 uid_resp
[uid_resp_bits
/ 8] |= UIDbit
<< (uid_resp_bits
% 8);
1790 uid_resp
[uid_resp_bits
/8] |= 1 << (uid_resp_bits
% 8); // next time select the card(s) with a 1 in the collision position
1792 // construct anticollosion command:
1793 sel_uid
[1] = ((2 + uid_resp_bits
/8) << 4) | (uid_resp_bits
& 0x07); // length of data in bytes and bits
1794 for (uint16_t i
= 0; i
<= uid_resp_bits
/8; i
++) {
1795 sel_uid
[2+i
] = uid_resp
[i
];
1797 collision_answer_offset
= uid_resp_bits
%8;
1798 ReaderTransmitBits(sel_uid
, 16 + uid_resp_bits
, NULL
);
1799 if (!ReaderReceiveOffset(resp
, collision_answer_offset
, resp_par
)) {
1803 // finally, add the last bits and BCC of the UID
1804 for (uint16_t i
= collision_answer_offset
; i
< (Demod
.len
-1)*8; i
++, uid_resp_bits
++) {
1805 uint16_t UIDbit
= (resp
[i
/8] >> (i
%8)) & 0x01;
1806 uid_resp
[uid_resp_bits
/8] |= UIDbit
<< (uid_resp_bits
% 8);
1809 } else { // no collision, use the response to SELECT_ALL as current uid
1810 memcpy(uid_resp
, resp
, 4);
1813 if (cascade_level
< num_cascades
- 1) {
1815 memcpy(uid_resp
+1, uid_ptr
+cascade_level
*3, 3);
1817 memcpy(uid_resp
, uid_ptr
+cascade_level
*3, 4);
1822 // calculate crypto UID. Always use last 4 Bytes.
1824 *cuid_ptr
= bytes_to_num(uid_resp
, 4);
1827 // Construct SELECT UID command
1828 sel_uid
[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1829 memcpy(sel_uid
+2, uid_resp
, 4); // the UID received during anticollision, or the provided UID
1830 sel_uid
[6] = sel_uid
[2] ^ sel_uid
[3] ^ sel_uid
[4] ^ sel_uid
[5]; // calculate and add BCC
1831 AppendCrc14443a(sel_uid
, 7); // calculate and add CRC
1832 ReaderTransmit(sel_uid
, sizeof(sel_uid
), NULL
);
1835 if (!ReaderReceive(resp
, resp_par
)) {
1840 // Test if more parts of the uid are coming
1841 if ((sak
& 0x04) /* && uid_resp[0] == 0x88 */) {
1842 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1843 // http://www.nxp.com/documents/application_note/AN10927.pdf
1844 uid_resp
[0] = uid_resp
[1];
1845 uid_resp
[1] = uid_resp
[2];
1846 uid_resp
[2] = uid_resp
[3];
1850 if(uid_ptr
&& anticollision
) {
1851 memcpy(uid_ptr
+ (cascade_level
*3), uid_resp
, uid_resp_len
);
1855 memcpy(p_hi14a_card
->uid
+ (cascade_level
*3), uid_resp
, uid_resp_len
);
1856 p_hi14a_card
->uidlen
+= uid_resp_len
;
1861 p_hi14a_card
->sak
= sak
;
1864 // PICC compilant with iso14443a-4 ---> (SAK & 0x20 != 0)
1865 if( (sak
& 0x20) == 0) return 2;
1868 // Request for answer to select
1869 AppendCrc14443a(rats
, 2);
1870 ReaderTransmit(rats
, sizeof(rats
), NULL
);
1872 if (!(len
= ReaderReceive(resp
, resp_par
))) {
1877 memcpy(p_hi14a_card
->ats
, resp
, len
);
1878 p_hi14a_card
->ats_len
= len
;
1881 // reset the PCB block number
1882 iso14_pcb_blocknum
= 0;
1884 // set default timeout and delay next transfer based on ATS
1885 iso14a_set_ATS_times(resp
);
1892 void iso14443a_setup(uint8_t fpga_minor_mode
) {
1893 FpgaDownloadAndGo(FPGA_BITSTREAM_HF
);
1894 // Set up the synchronous serial port
1895 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A
);
1896 // connect Demodulated Signal to ADC:
1897 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
1899 // Signal field is on with the appropriate LED
1900 if (fpga_minor_mode
== FPGA_HF_ISO14443A_READER_MOD
1901 || fpga_minor_mode
== FPGA_HF_ISO14443A_READER_LISTEN
) {
1906 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| fpga_minor_mode
);
1913 NextTransferTime
= 2*DELAY_ARM2AIR_AS_READER
;
1914 iso14a_set_timeout(1060); // 10ms default
1917 /* Peter Fillmore 2015
1918 Added card id field to the function
1919 info from ISO14443A standard
1922 b3 = depends on block
1923 b4 = Card ID following if set to 1
1924 b5 = depends on block type
1925 b6 = depends on block type
1928 b8 b7 b6 b5 b4 b3 b2 b1
1932 b8 b7 b6 b5 b4 b3 b2 b1
1936 b8 b7 b6 b5 b4 b3 b2 b1
1938 b5,b6 = 00 - DESELECT
1941 int iso14_apdu(uint8_t *cmd
, uint16_t cmd_len
, void *data
, uint8_t *res
) {
1942 uint8_t parity
[MAX_PARITY_SIZE
];
1943 uint8_t real_cmd
[cmd_len
+ 4];
1946 // ISO 14443 APDU frame: PCB [CID] [NAD] APDU CRC PCB=0x02
1947 real_cmd
[0] = 0x02; // bnr,nad,cid,chn=0; i-block(0x00)
1948 // put block number into the PCB
1949 real_cmd
[0] |= iso14_pcb_blocknum
;
1950 memcpy(real_cmd
+ 1, cmd
, cmd_len
);
1953 real_cmd
[0] = 0xA2; // r-block + ACK
1954 real_cmd
[0] |= iso14_pcb_blocknum
;
1956 AppendCrc14443a(real_cmd
, cmd_len
+ 1);
1958 ReaderTransmit(real_cmd
, cmd_len
+ 3, NULL
);
1960 size_t len
= ReaderReceive(data
, parity
);
1961 uint8_t *data_bytes
= (uint8_t *) data
;
1964 return 0; //DATA LINK ERROR
1967 while(len
&& ((data_bytes
[0] & 0xF2) == 0xF2)) {
1968 uint32_t save_iso14a_timeout
= iso14a_get_timeout();
1969 // temporarily increase timeout
1970 iso14a_set_timeout(MAX((data_bytes
[1] & 0x3f) * save_iso14a_timeout
, MAX_ISO14A_TIMEOUT
));
1971 // Transmit WTX back
1972 // byte1 - WTXM [1..59]. command FWT=FWT*WTXM
1973 data_bytes
[1] = data_bytes
[1] & 0x3f; // 2 high bits mandatory set to 0b
1974 // now need to fix CRC.
1975 AppendCrc14443a(data_bytes
, len
- 2);
1977 ReaderTransmit(data_bytes
, len
, NULL
);
1978 // retrieve the result again (with increased timeout)
1979 len
= ReaderReceive(data
, parity
);
1982 iso14a_set_timeout(save_iso14a_timeout
);
1985 // if we received an I- or R(ACK)-Block with a block number equal to the
1986 // current block number, toggle the current block number
1987 if (len
>= 3 // PCB+CRC = 3 bytes
1988 && ((data_bytes
[0] & 0xC0) == 0 // I-Block
1989 || (data_bytes
[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1990 && (data_bytes
[0] & 0x01) == iso14_pcb_blocknum
) // equal block numbers
1992 iso14_pcb_blocknum
^= 1;
1995 // if we received I-block with chaining we need to send ACK and receive another block of data
1997 *res
= data_bytes
[0];
2000 if (len
>= 3 && !CheckCrc14443(CRC_14443_A
, data_bytes
, len
)) {
2009 // memmove(data_bytes, data_bytes + 1, len);
2010 for (int i
= 0; i
< len
; i
++)
2011 data_bytes
[i
] = data_bytes
[i
+ 1];
2018 //-----------------------------------------------------------------------------
2019 // Read an ISO 14443a tag. Send out commands and store answers.
2021 //-----------------------------------------------------------------------------
2022 void ReaderIso14443a(UsbCommand
*c
)
2024 iso14a_command_t param
= c
->arg
[0];
2025 uint8_t *cmd
= c
->d
.asBytes
;
2026 size_t len
= c
->arg
[1] & 0xffff;
2027 size_t lenbits
= c
->arg
[1] >> 16;
2028 uint32_t timeout
= c
->arg
[2];
2030 byte_t buf
[USB_CMD_DATA_SIZE
] = {0};
2031 uint8_t par
[MAX_PARITY_SIZE
];
2032 bool cantSELECT
= false;
2036 if(param
& ISO14A_CLEAR_TRACE
) {
2040 if(param
& ISO14A_REQUEST_TRIGGER
) {
2041 iso14a_set_trigger(true);
2044 if(param
& ISO14A_CONNECT
) {
2046 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN
);
2047 if(!(param
& ISO14A_NO_SELECT
)) {
2048 iso14a_card_select_t
*card
= (iso14a_card_select_t
*)buf
;
2049 arg0
= iso14443a_select_card(NULL
, card
, NULL
, true, 0, param
& ISO14A_NO_RATS
);
2051 // if we cant select then we cant send data
2052 if (arg0
!= 1 && arg0
!= 2) {
2053 // 1 - all is OK with ATS, 2 - without ATS
2056 FpgaDisableTracing();
2058 cmd_send(CMD_ACK
,arg0
,card
->uidlen
,0,buf
,sizeof(iso14a_card_select_t
));
2063 if(param
& ISO14A_SET_TIMEOUT
) {
2064 iso14a_set_timeout(timeout
);
2067 if(param
& ISO14A_APDU
&& !cantSELECT
) {
2069 arg0
= iso14_apdu(cmd
, len
, buf
, &res
);
2070 FpgaDisableTracing();
2072 cmd_send(CMD_ACK
, arg0
, res
, 0, buf
, sizeof(buf
));
2076 if(param
& ISO14A_RAW
&& !cantSELECT
) {
2077 if(param
& ISO14A_APPEND_CRC
) {
2078 if(param
& ISO14A_TOPAZMODE
) {
2079 AppendCrc14443b(cmd
,len
);
2081 AppendCrc14443a(cmd
,len
);
2084 if (lenbits
) lenbits
+= 16;
2086 if(lenbits
>0) { // want to send a specific number of bits (e.g. short commands)
2087 if(param
& ISO14A_TOPAZMODE
) {
2088 int bits_to_send
= lenbits
;
2090 ReaderTransmitBitsPar(&cmd
[i
++], MIN(bits_to_send
, 7), NULL
, NULL
); // first byte is always short (7bits) and no parity
2092 while (bits_to_send
> 0) {
2093 ReaderTransmitBitsPar(&cmd
[i
++], MIN(bits_to_send
, 8), NULL
, NULL
); // following bytes are 8 bit and no parity
2097 GetParity(cmd
, lenbits
/8, par
);
2098 ReaderTransmitBitsPar(cmd
, lenbits
, par
, NULL
); // bytes are 8 bit with odd parity
2100 } else { // want to send complete bytes only
2101 if(param
& ISO14A_TOPAZMODE
) {
2103 ReaderTransmitBitsPar(&cmd
[i
++], 7, NULL
, NULL
); // first byte: 7 bits, no paritiy
2105 ReaderTransmitBitsPar(&cmd
[i
++], 8, NULL
, NULL
); // following bytes: 8 bits, no paritiy
2108 ReaderTransmit(cmd
,len
, NULL
); // 8 bits, odd parity
2111 arg0
= ReaderReceive(buf
, par
);
2112 FpgaDisableTracing();
2115 cmd_send(CMD_ACK
,arg0
,0,0,buf
,sizeof(buf
));
2119 if(param
& ISO14A_REQUEST_TRIGGER
) {
2120 iso14a_set_trigger(false);
2123 if(param
& ISO14A_NO_DISCONNECT
) {
2127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2132 // Determine the distance between two nonces.
2133 // Assume that the difference is small, but we don't know which is first.
2134 // Therefore try in alternating directions.
2135 static int32_t dist_nt(uint32_t nt1
, uint32_t nt2
) {
2138 uint32_t nttmp1
, nttmp2
;
2140 if (nt1
== nt2
) return 0;
2145 for (i
= 1; i
< 32768; i
++) {
2146 nttmp1
= prng_successor(nttmp1
, 1);
2147 if (nttmp1
== nt2
) return i
;
2148 nttmp2
= prng_successor(nttmp2
, 1);
2149 if (nttmp2
== nt1
) return -i
;
2152 return(-99999); // either nt1 or nt2 are invalid nonces
2156 //-----------------------------------------------------------------------------
2157 // Recover several bits of the cypher stream. This implements (first stages of)
2158 // the algorithm described in "The Dark Side of Security by Obscurity and
2159 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2160 // (article by Nicolas T. Courtois, 2009)
2161 //-----------------------------------------------------------------------------
2162 void ReaderMifare(bool first_try
)
2165 uint8_t mf_auth
[] = { 0x60,0x00,0xf5,0x7b };
2166 uint8_t mf_nr_ar
[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2167 static uint8_t mf_nr_ar3
;
2169 uint8_t receivedAnswer
[MAX_MIFARE_FRAME_SIZE
];
2170 uint8_t receivedAnswerPar
[MAX_MIFARE_PARITY_SIZE
];
2172 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD
);
2174 // free eventually allocated BigBuf memory. We want all for tracing.
2180 uint8_t nt_diff
= 0;
2181 uint8_t par
[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2182 static uint8_t par_low
= 0;
2184 uint8_t uid
[10] ={0};
2188 uint32_t previous_nt
= 0;
2189 static uint32_t nt_attacked
= 0;
2190 uint8_t par_list
[8] = {0x00};
2191 uint8_t ks_list
[8] = {0x00};
2193 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2194 uint32_t sync_time
= GetCountSspClk() & 0xfffffff8;
2195 static int32_t sync_cycles
;
2196 int catch_up_cycles
= 0;
2197 int last_catch_up
= 0;
2198 uint16_t elapsed_prng_sequences
;
2199 uint16_t consecutive_resyncs
= 0;
2204 par
[0] = par_low
= 0;
2205 sync_cycles
= PRNG_SEQUENCE_LENGTH
; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2209 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2211 mf_nr_ar
[3] = mf_nr_ar3
;
2220 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2221 #define MAX_SYNC_TRIES 32
2222 #define SYNC_TIME_BUFFER 16 // if there is only SYNC_TIME_BUFFER left before next planned sync, wait for next PRNG cycle
2223 #define NUM_DEBUG_INFOS 8 // per strategy
2224 #define MAX_STRATEGY 3
2225 uint16_t unexpected_random
= 0;
2226 uint16_t sync_tries
= 0;
2227 int16_t debug_info_nr
= -1;
2228 uint16_t strategy
= 0;
2229 int32_t debug_info
[MAX_STRATEGY
][NUM_DEBUG_INFOS
];
2230 uint32_t select_time
;
2233 for(uint16_t i
= 0; true; i
++) {
2238 // Test if the action was cancelled
2239 if(BUTTON_PRESS()) {
2244 if (strategy
== 2) {
2245 // test with additional hlt command
2247 int len
= mifare_sendcmd_short(NULL
, false, 0x50, 0x00, receivedAnswer
, receivedAnswerPar
, &halt_time
);
2248 if (len
&& MF_DBGLEVEL
>= 3) {
2249 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len
);
2253 if (strategy
== 3) {
2254 // test with FPGA power off/on
2255 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2257 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD
);
2261 if(!iso14443a_select_card(uid
, NULL
, &cuid
, true, 0, true)) {
2262 if (MF_DBGLEVEL
>= 1) Dbprintf("Mifare: Can't select card");
2265 select_time
= GetCountSspClk();
2267 elapsed_prng_sequences
= 1;
2268 if (debug_info_nr
== -1) {
2269 sync_time
= (sync_time
& 0xfffffff8) + sync_cycles
+ catch_up_cycles
;
2270 catch_up_cycles
= 0;
2272 // if we missed the sync time already or are about to miss it, advance to the next nonce repeat
2273 while(sync_time
< GetCountSspClk() + SYNC_TIME_BUFFER
) {
2274 elapsed_prng_sequences
++;
2275 sync_time
= (sync_time
& 0xfffffff8) + sync_cycles
;
2278 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2279 ReaderTransmit(mf_auth
, sizeof(mf_auth
), &sync_time
);
2281 // collect some information on tag nonces for debugging:
2282 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2283 if (strategy
== 0) {
2284 // nonce distances at fixed time after card select:
2285 sync_time
= select_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2286 } else if (strategy
== 1) {
2287 // nonce distances at fixed time between authentications:
2288 sync_time
= sync_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2289 } else if (strategy
== 2) {
2290 // nonce distances at fixed time after halt:
2291 sync_time
= halt_time
+ DEBUG_FIXED_SYNC_CYCLES
;
2293 // nonce_distances at fixed time after power on
2294 sync_time
= DEBUG_FIXED_SYNC_CYCLES
;
2296 ReaderTransmit(mf_auth
, sizeof(mf_auth
), &sync_time
);
2299 // Receive the (4 Byte) "random" nonce
2300 if (!ReaderReceive(receivedAnswer
, receivedAnswerPar
)) {
2301 if (MF_DBGLEVEL
>= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2306 nt
= bytes_to_num(receivedAnswer
, 4);
2308 // Transmit reader nonce with fake par
2309 ReaderTransmitPar(mf_nr_ar
, sizeof(mf_nr_ar
), par
, NULL
);
2311 if (first_try
&& previous_nt
&& !nt_attacked
) { // we didn't calibrate our clock yet
2312 int nt_distance
= dist_nt(previous_nt
, nt
);
2313 if (nt_distance
== 0) {
2316 if (nt_distance
== -99999) { // invalid nonce received
2317 unexpected_random
++;
2318 if (unexpected_random
> MAX_UNEXPECTED_RANDOM
) {
2319 isOK
= -3; // Card has an unpredictable PRNG. Give up
2322 continue; // continue trying...
2325 if (++sync_tries
> MAX_SYNC_TRIES
) {
2326 if (strategy
> MAX_STRATEGY
|| MF_DBGLEVEL
< 3) {
2327 isOK
= -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2329 } else { // continue for a while, just to collect some debug info
2330 debug_info
[strategy
][debug_info_nr
] = nt_distance
;
2332 if (debug_info_nr
== NUM_DEBUG_INFOS
) {
2339 sync_cycles
= (sync_cycles
- nt_distance
/elapsed_prng_sequences
);
2340 if (sync_cycles
<= 0) {
2341 sync_cycles
+= PRNG_SEQUENCE_LENGTH
;
2343 if (MF_DBGLEVEL
>= 3) {
2344 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i
, nt_distance
, elapsed_prng_sequences
, sync_cycles
);
2350 if ((nt
!= nt_attacked
) && nt_attacked
) { // we somehow lost sync. Try to catch up again...
2351 catch_up_cycles
= -dist_nt(nt_attacked
, nt
);
2352 if (catch_up_cycles
== 99999) { // invalid nonce received. Don't resync on that one.
2353 catch_up_cycles
= 0;
2356 catch_up_cycles
/= elapsed_prng_sequences
;
2357 if (catch_up_cycles
== last_catch_up
) {
2358 consecutive_resyncs
++;
2361 last_catch_up
= catch_up_cycles
;
2362 consecutive_resyncs
= 0;
2364 if (consecutive_resyncs
< 3) {
2365 if (MF_DBGLEVEL
>= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i
, -catch_up_cycles
, consecutive_resyncs
);
2368 sync_cycles
= sync_cycles
+ catch_up_cycles
;
2369 if (MF_DBGLEVEL
>= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i
, -catch_up_cycles
, sync_cycles
);
2371 catch_up_cycles
= 0;
2372 consecutive_resyncs
= 0;
2377 consecutive_resyncs
= 0;
2379 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2380 if (ReaderReceive(receivedAnswer
, receivedAnswerPar
)) {
2381 catch_up_cycles
= 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2384 par_low
= par
[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2388 if(led_on
) LED_B_ON(); else LED_B_OFF();
2390 par_list
[nt_diff
] = SwapBits(par
[0], 8);
2391 ks_list
[nt_diff
] = receivedAnswer
[0] ^ 0x05;
2393 // Test if the information is complete
2394 if (nt_diff
== 0x07) {
2399 nt_diff
= (nt_diff
+ 1) & 0x07;
2400 mf_nr_ar
[3] = (mf_nr_ar
[3] & 0x1F) | (nt_diff
<< 5);
2403 if (nt_diff
== 0 && first_try
)
2406 if (par
[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2411 par
[0] = ((par
[0] & 0x1F) + 1) | par_low
;
2417 mf_nr_ar
[3] &= 0x1F;
2420 if (MF_DBGLEVEL
>= 3) {
2421 for (uint16_t i
= 0; i
<= MAX_STRATEGY
; i
++) {
2422 for(uint16_t j
= 0; j
< NUM_DEBUG_INFOS
; j
++) {
2423 Dbprintf("collected debug info[%d][%d] = %d", i
, j
, debug_info
[i
][j
]);
2429 FpgaDisableTracing();
2432 memcpy(buf
+ 0, uid
, 4);
2433 num_to_bytes(nt
, 4, buf
+ 4);
2434 memcpy(buf
+ 8, par_list
, 8);
2435 memcpy(buf
+ 16, ks_list
, 8);
2436 memcpy(buf
+ 24, mf_nr_ar
, 8);
2438 cmd_send(CMD_ACK
, isOK
, 0, 0, buf
, 32);
2441 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2448 //-----------------------------------------------------------------------------
2451 //-----------------------------------------------------------------------------
2452 void RAMFUNC
SniffMifare(uint8_t param
) {
2454 // bit 0 - trigger from first card answer
2455 // bit 1 - trigger from first reader 7-bit request
2457 // C(red) A(yellow) B(green)
2459 // init trace buffer
2463 // The command (reader -> tag) that we're receiving.
2464 // The length of a received command will in most cases be no more than 18 bytes.
2465 // So 32 should be enough!
2466 uint8_t receivedCmd
[MAX_MIFARE_FRAME_SIZE
];
2467 uint8_t receivedCmdPar
[MAX_MIFARE_PARITY_SIZE
];
2468 // The response (tag -> reader) that we're receiving.
2469 uint8_t receivedResponse
[MAX_MIFARE_FRAME_SIZE
];
2470 uint8_t receivedResponsePar
[MAX_MIFARE_PARITY_SIZE
];
2472 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER
);
2474 // free eventually allocated BigBuf memory
2476 // allocate the DMA buffer, used to stream samples from the FPGA
2477 uint8_t *dmaBuf
= BigBuf_malloc(DMA_BUFFER_SIZE
);
2478 uint8_t *data
= dmaBuf
;
2479 uint8_t previous_data
= 0;
2482 bool ReaderIsActive
= false;
2483 bool TagIsActive
= false;
2485 // Set up the demodulator for tag -> reader responses.
2486 DemodInit(receivedResponse
, receivedResponsePar
);
2488 // Set up the demodulator for the reader -> tag commands
2489 UartInit(receivedCmd
, receivedCmdPar
);
2491 // Setup for the DMA.
2492 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
); // set transfer address and number of bytes. Start transfer.
2499 // And now we loop, receiving samples.
2500 for(uint32_t sniffCounter
= 0; true; ) {
2502 if(BUTTON_PRESS()) {
2503 DbpString("Canceled by button.");
2510 if ((sniffCounter
& 0x0000FFFF) == 0) { // from time to time
2511 // check if a transaction is completed (timeout after 2000ms).
2512 // if yes, stop the DMA transfer and send what we have so far to the client
2513 if (MfSniffSend(2000)) {
2514 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2518 ReaderIsActive
= false;
2519 TagIsActive
= false;
2520 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
); // set transfer address and number of bytes. Start transfer.
2524 int register readBufDataP
= data
- dmaBuf
; // number of bytes we have processed so far
2525 int register dmaBufDataP
= DMA_BUFFER_SIZE
- AT91C_BASE_PDC_SSC
->PDC_RCR
; // number of bytes already transferred
2526 if (readBufDataP
<= dmaBufDataP
){ // we are processing the same block of data which is currently being transferred
2527 dataLen
= dmaBufDataP
- readBufDataP
; // number of bytes still to be processed
2529 dataLen
= DMA_BUFFER_SIZE
- readBufDataP
+ dmaBufDataP
; // number of bytes still to be processed
2531 // test for length of buffer
2532 if(dataLen
> maxDataLen
) { // we are more behind than ever...
2533 maxDataLen
= dataLen
;
2534 if(dataLen
> (9 * DMA_BUFFER_SIZE
/ 10)) {
2535 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen
);
2539 if(dataLen
< 1) continue;
2541 // primary buffer was stopped ( <-- we lost data!
2542 if (!AT91C_BASE_PDC_SSC
->PDC_RCR
) {
2543 AT91C_BASE_PDC_SSC
->PDC_RPR
= (uint32_t) dmaBuf
;
2544 AT91C_BASE_PDC_SSC
->PDC_RCR
= DMA_BUFFER_SIZE
;
2545 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen
); // temporary
2547 // secondary buffer sets as primary, secondary buffer was stopped
2548 if (!AT91C_BASE_PDC_SSC
->PDC_RNCR
) {
2549 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) dmaBuf
;
2550 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
2555 if (sniffCounter
& 0x01) {
2557 if(!TagIsActive
) { // no need to try decoding tag data if the reader is sending
2558 uint8_t readerdata
= (previous_data
& 0xF0) | (*data
>> 4);
2559 if(MillerDecoding(readerdata
, (sniffCounter
-1)*4)) {
2563 if (MfSniffLogic(receivedCmd
, Uart
.len
, Uart
.parity
, Uart
.bitCount
, true)) break;
2565 /* And ready to receive another command. */
2566 UartInit(receivedCmd
, receivedCmdPar
);
2568 /* And also reset the demod code */
2571 ReaderIsActive
= (Uart
.state
!= STATE_UNSYNCD
);
2574 if(!ReaderIsActive
) { // no need to try decoding tag data if the reader is sending
2575 uint8_t tagdata
= (previous_data
<< 4) | (*data
& 0x0F);
2576 if(ManchesterDecoding(tagdata
, 0, (sniffCounter
-1)*4)) {
2580 if (MfSniffLogic(receivedResponse
, Demod
.len
, Demod
.parity
, Demod
.bitCount
, false)) break;
2582 // And ready to receive another response.
2584 // And reset the Miller decoder including its (now outdated) input buffer
2585 UartInit(receivedCmd
, receivedCmdPar
);
2587 TagIsActive
= (Demod
.state
!= DEMOD_UNSYNCD
);
2591 previous_data
= *data
;
2594 if(data
== dmaBuf
+ DMA_BUFFER_SIZE
) {
2600 DbpString("COMMAND FINISHED.");
2602 FpgaDisableSscDma();
2603 FpgaDisableTracing();
2606 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen
, Uart
.state
, Uart
.len
);