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1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18 // split into two routines so we can avoid timing issues after sending commands //
19 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
20 {
21 uint8_t *dest = (uint8_t *)BigBuf;
22 int n = sizeof(BigBuf);
23 int i;
24
25 memset(dest, 0, n);
26 i = 0;
27 for(;;) {
28 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
29 AT91C_BASE_SSC->SSC_THR = 0x43;
30 LED_D_ON();
31 }
32 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
33 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
34 LED_D_OFF();
35 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
36 continue;
37 else
38 trigger_threshold = -1;
39 if (++i >= n) break;
40 }
41 }
42 if(!silent)
43 {
44 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
45 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
46
47 }
48 }
49 void DoAcquisition125k(int trigger_threshold)
50 {
51 DoAcquisition125k_internal(trigger_threshold, false);
52 }
53
54 //void SetupToAcquireRawAdcSamples(int divisor)
55 void LFSetupFPGAForADC(int divisor, bool lf_field)
56 {
57 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
58 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
59 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
60 else if (divisor == 0)
61 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
62 else
63 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
64
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
66
67 // Connect the A/D to the peak-detected low-frequency path.
68 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
69 // Give it a bit of time for the resonant antenna to settle.
70 SpinDelay(50);
71 // Now set up the SSC to get the ADC samples that are now streaming at us.
72 FpgaSetupSsc();
73 }
74
75 void AcquireRawAdcSamples125k(int divisor)
76 {
77 LFSetupFPGAForADC(divisor, true);
78 // Now call the acquisition routine
79 DoAcquisition125k_internal(-1,false);
80 }
81 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
82 {
83 LFSetupFPGAForADC(divisor, false);
84 DoAcquisition125k(trigger_threshold);
85 }
86
87 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
88 {
89 int at134khz;
90
91 /* Make sure the tag is reset */
92 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
93 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
94 SpinDelay(2500);
95
96 // see if 'h' was specified
97 if (command[strlen((char *) command) - 1] == 'h')
98 at134khz = TRUE;
99 else
100 at134khz = FALSE;
101
102 if (at134khz)
103 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
104 else
105 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
106
107 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
108
109 // Give it a bit of time for the resonant antenna to settle.
110 SpinDelay(50);
111 // And a little more time for the tag to fully power up
112 SpinDelay(2000);
113
114 // Now set up the SSC to get the ADC samples that are now streaming at us.
115 FpgaSetupSsc();
116
117 // now modulate the reader field
118 while(*command != '\0' && *command != ' ') {
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
120 LED_D_OFF();
121 SpinDelayUs(delay_off);
122 if (at134khz)
123 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
124 else
125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
126
127 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
128 LED_D_ON();
129 if(*(command++) == '0')
130 SpinDelayUs(period_0);
131 else
132 SpinDelayUs(period_1);
133 }
134 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
135 LED_D_OFF();
136 SpinDelayUs(delay_off);
137 if (at134khz)
138 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
139 else
140 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
141
142 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
143
144 // now do the read
145 DoAcquisition125k(-1);
146 }
147
148 /* blank r/w tag data stream
149 ...0000000000000000 01111111
150 1010101010101010101010101010101010101010101010101010101010101010
151 0011010010100001
152 01111111
153 101010101010101[0]000...
154
155 [5555fe852c5555555555555555fe0000]
156 */
157 void ReadTItag(void)
158 {
159 // some hardcoded initial params
160 // when we read a TI tag we sample the zerocross line at 2Mhz
161 // TI tags modulate a 1 as 16 cycles of 123.2Khz
162 // TI tags modulate a 0 as 16 cycles of 134.2Khz
163 #define FSAMPLE 2000000
164 #define FREQLO 123200
165 #define FREQHI 134200
166
167 signed char *dest = (signed char *)BigBuf;
168 int n = sizeof(BigBuf);
169 // int *dest = GraphBuffer;
170 // int n = GraphTraceLen;
171
172 // 128 bit shift register [shift3:shift2:shift1:shift0]
173 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
174
175 int i, cycles=0, samples=0;
176 // how many sample points fit in 16 cycles of each frequency
177 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
178 // when to tell if we're close enough to one freq or another
179 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
180
181 // TI tags charge at 134.2Khz
182 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
183 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
184
185 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
186 // connects to SSP_DIN and the SSP_DOUT logic level controls
187 // whether we're modulating the antenna (high)
188 // or listening to the antenna (low)
189 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
190
191 // get TI tag data into the buffer
192 AcquireTiType();
193
194 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
195
196 for (i=0; i<n-1; i++) {
197 // count cycles by looking for lo to hi zero crossings
198 if ( (dest[i]<0) && (dest[i+1]>0) ) {
199 cycles++;
200 // after 16 cycles, measure the frequency
201 if (cycles>15) {
202 cycles=0;
203 samples=i-samples; // number of samples in these 16 cycles
204
205 // TI bits are coming to us lsb first so shift them
206 // right through our 128 bit right shift register
207 shift0 = (shift0>>1) | (shift1 << 31);
208 shift1 = (shift1>>1) | (shift2 << 31);
209 shift2 = (shift2>>1) | (shift3 << 31);
210 shift3 >>= 1;
211
212 // check if the cycles fall close to the number
213 // expected for either the low or high frequency
214 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
215 // low frequency represents a 1
216 shift3 |= (1<<31);
217 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
218 // high frequency represents a 0
219 } else {
220 // probably detected a gay waveform or noise
221 // use this as gaydar or discard shift register and start again
222 shift3 = shift2 = shift1 = shift0 = 0;
223 }
224 samples = i;
225
226 // for each bit we receive, test if we've detected a valid tag
227
228 // if we see 17 zeroes followed by 6 ones, we might have a tag
229 // remember the bits are backwards
230 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
231 // if start and end bytes match, we have a tag so break out of the loop
232 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
233 cycles = 0xF0B; //use this as a flag (ugly but whatever)
234 break;
235 }
236 }
237 }
238 }
239 }
240
241 // if flag is set we have a tag
242 if (cycles!=0xF0B) {
243 DbpString("Info: No valid tag detected.");
244 } else {
245 // put 64 bit data into shift1 and shift0
246 shift0 = (shift0>>24) | (shift1 << 8);
247 shift1 = (shift1>>24) | (shift2 << 8);
248
249 // align 16 bit crc into lower half of shift2
250 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
251
252 // if r/w tag, check ident match
253 if ( shift3&(1<<15) ) {
254 DbpString("Info: TI tag is rewriteable");
255 // only 15 bits compare, last bit of ident is not valid
256 if ( ((shift3>>16)^shift0)&0x7fff ) {
257 DbpString("Error: Ident mismatch!");
258 } else {
259 DbpString("Info: TI tag ident is valid");
260 }
261 } else {
262 DbpString("Info: TI tag is readonly");
263 }
264
265 // WARNING the order of the bytes in which we calc crc below needs checking
266 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
267 // bytes in reverse or something
268 // calculate CRC
269 uint32_t crc=0;
270
271 crc = update_crc16(crc, (shift0)&0xff);
272 crc = update_crc16(crc, (shift0>>8)&0xff);
273 crc = update_crc16(crc, (shift0>>16)&0xff);
274 crc = update_crc16(crc, (shift0>>24)&0xff);
275 crc = update_crc16(crc, (shift1)&0xff);
276 crc = update_crc16(crc, (shift1>>8)&0xff);
277 crc = update_crc16(crc, (shift1>>16)&0xff);
278 crc = update_crc16(crc, (shift1>>24)&0xff);
279
280 Dbprintf("Info: Tag data: %x%08x, crc=%x",
281 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
282 if (crc != (shift2&0xffff)) {
283 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
284 } else {
285 DbpString("Info: CRC is good");
286 }
287 }
288 }
289
290 void WriteTIbyte(uint8_t b)
291 {
292 int i = 0;
293
294 // modulate 8 bits out to the antenna
295 for (i=0; i<8; i++)
296 {
297 if (b&(1<<i)) {
298 // stop modulating antenna
299 LOW(GPIO_SSC_DOUT);
300 SpinDelayUs(1000);
301 // modulate antenna
302 HIGH(GPIO_SSC_DOUT);
303 SpinDelayUs(1000);
304 } else {
305 // stop modulating antenna
306 LOW(GPIO_SSC_DOUT);
307 SpinDelayUs(300);
308 // modulate antenna
309 HIGH(GPIO_SSC_DOUT);
310 SpinDelayUs(1700);
311 }
312 }
313 }
314
315 void AcquireTiType(void)
316 {
317 int i, j, n;
318 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
319 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
320 #define TIBUFLEN 1250
321
322 // clear buffer
323 memset(BigBuf,0,sizeof(BigBuf));
324
325 // Set up the synchronous serial port
326 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
327 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
328
329 // steal this pin from the SSP and use it to control the modulation
330 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
331 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
332
333 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
334 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
335
336 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
337 // 48/2 = 24 MHz clock must be divided by 12
338 AT91C_BASE_SSC->SSC_CMR = 12;
339
340 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
341 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
342 AT91C_BASE_SSC->SSC_TCMR = 0;
343 AT91C_BASE_SSC->SSC_TFMR = 0;
344
345 LED_D_ON();
346
347 // modulate antenna
348 HIGH(GPIO_SSC_DOUT);
349
350 // Charge TI tag for 50ms.
351 SpinDelay(50);
352
353 // stop modulating antenna and listen
354 LOW(GPIO_SSC_DOUT);
355
356 LED_D_OFF();
357
358 i = 0;
359 for(;;) {
360 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
361 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
362 i++; if(i >= TIBUFLEN) break;
363 }
364 WDT_HIT();
365 }
366
367 // return stolen pin to SSP
368 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
369 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
370
371 char *dest = (char *)BigBuf;
372 n = TIBUFLEN*32;
373 // unpack buffer
374 for (i=TIBUFLEN-1; i>=0; i--) {
375 for (j=0; j<32; j++) {
376 if(BigBuf[i] & (1 << j)) {
377 dest[--n] = 1;
378 } else {
379 dest[--n] = -1;
380 }
381 }
382 }
383 }
384
385 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
386 // if crc provided, it will be written with the data verbatim (even if bogus)
387 // if not provided a valid crc will be computed from the data and written.
388 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
389 {
390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 if(crc == 0) {
392 crc = update_crc16(crc, (idlo)&0xff);
393 crc = update_crc16(crc, (idlo>>8)&0xff);
394 crc = update_crc16(crc, (idlo>>16)&0xff);
395 crc = update_crc16(crc, (idlo>>24)&0xff);
396 crc = update_crc16(crc, (idhi)&0xff);
397 crc = update_crc16(crc, (idhi>>8)&0xff);
398 crc = update_crc16(crc, (idhi>>16)&0xff);
399 crc = update_crc16(crc, (idhi>>24)&0xff);
400 }
401 Dbprintf("Writing to tag: %x%08x, crc=%x",
402 (unsigned int) idhi, (unsigned int) idlo, crc);
403
404 // TI tags charge at 134.2Khz
405 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
406 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
407 // connects to SSP_DIN and the SSP_DOUT logic level controls
408 // whether we're modulating the antenna (high)
409 // or listening to the antenna (low)
410 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
411 LED_A_ON();
412
413 // steal this pin from the SSP and use it to control the modulation
414 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
415 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
416
417 // writing algorithm:
418 // a high bit consists of a field off for 1ms and field on for 1ms
419 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
420 // initiate a charge time of 50ms (field on) then immediately start writing bits
421 // start by writing 0xBB (keyword) and 0xEB (password)
422 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
423 // finally end with 0x0300 (write frame)
424 // all data is sent lsb firts
425 // finish with 15ms programming time
426
427 // modulate antenna
428 HIGH(GPIO_SSC_DOUT);
429 SpinDelay(50); // charge time
430
431 WriteTIbyte(0xbb); // keyword
432 WriteTIbyte(0xeb); // password
433 WriteTIbyte( (idlo )&0xff );
434 WriteTIbyte( (idlo>>8 )&0xff );
435 WriteTIbyte( (idlo>>16)&0xff );
436 WriteTIbyte( (idlo>>24)&0xff );
437 WriteTIbyte( (idhi )&0xff );
438 WriteTIbyte( (idhi>>8 )&0xff );
439 WriteTIbyte( (idhi>>16)&0xff );
440 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
441 WriteTIbyte( (crc )&0xff ); // crc lo
442 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
443 WriteTIbyte(0x00); // write frame lo
444 WriteTIbyte(0x03); // write frame hi
445 HIGH(GPIO_SSC_DOUT);
446 SpinDelay(50); // programming time
447
448 LED_A_OFF();
449
450 // get TI tag data into the buffer
451 AcquireTiType();
452
453 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
454 DbpString("Now use tiread to check");
455 }
456
457 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
458 {
459 int i;
460 uint8_t *tab = (uint8_t *)BigBuf;
461
462 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
463 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
464
465 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
466
467 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
468 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
469
470 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
471 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
472
473 i = 0;
474 for(;;) {
475 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
476 if(BUTTON_PRESS()) {
477 DbpString("Stopped");
478 return;
479 }
480 WDT_HIT();
481 }
482
483 if (ledcontrol)
484 LED_D_ON();
485
486 if(tab[i])
487 OPEN_COIL();
488 else
489 SHORT_COIL();
490
491 if (ledcontrol)
492 LED_D_OFF();
493
494 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
495 if(BUTTON_PRESS()) {
496 DbpString("Stopped");
497 return;
498 }
499 WDT_HIT();
500 }
501
502 i++;
503 if(i == period) {
504 i = 0;
505 if (gap) {
506 SHORT_COIL();
507 SpinDelayUs(gap);
508 }
509 }
510 }
511 }
512
513 #define DEBUG_FRAME_CONTENTS 1
514 void SimulateTagLowFrequencyBidir(int divisor, int t0)
515 {
516 }
517
518 // compose fc/8 fc/10 waveform
519 static void fc(int c, int *n) {
520 uint8_t *dest = (uint8_t *)BigBuf;
521 int idx;
522
523 // for when we want an fc8 pattern every 4 logical bits
524 if(c==0) {
525 dest[((*n)++)]=1;
526 dest[((*n)++)]=1;
527 dest[((*n)++)]=0;
528 dest[((*n)++)]=0;
529 dest[((*n)++)]=0;
530 dest[((*n)++)]=0;
531 dest[((*n)++)]=0;
532 dest[((*n)++)]=0;
533 }
534 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
535 if(c==8) {
536 for (idx=0; idx<6; idx++) {
537 dest[((*n)++)]=1;
538 dest[((*n)++)]=1;
539 dest[((*n)++)]=0;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 }
546 }
547
548 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
549 if(c==10) {
550 for (idx=0; idx<5; idx++) {
551 dest[((*n)++)]=1;
552 dest[((*n)++)]=1;
553 dest[((*n)++)]=1;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 dest[((*n)++)]=0;
557 dest[((*n)++)]=0;
558 dest[((*n)++)]=0;
559 dest[((*n)++)]=0;
560 dest[((*n)++)]=0;
561 }
562 }
563 }
564
565 // prepare a waveform pattern in the buffer based on the ID given then
566 // simulate a HID tag until the button is pressed
567 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
568 {
569 int n=0, i=0;
570 /*
571 HID tag bitstream format
572 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
573 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
574 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
575 A fc8 is inserted before every 4 bits
576 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
577 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
578 */
579
580 if (hi>0xFFF) {
581 DbpString("Tags can only have 44 bits.");
582 return;
583 }
584 fc(0,&n);
585 // special start of frame marker containing invalid bit sequences
586 fc(8, &n); fc(8, &n); // invalid
587 fc(8, &n); fc(10, &n); // logical 0
588 fc(10, &n); fc(10, &n); // invalid
589 fc(8, &n); fc(10, &n); // logical 0
590
591 WDT_HIT();
592 // manchester encode bits 43 to 32
593 for (i=11; i>=0; i--) {
594 if ((i%4)==3) fc(0,&n);
595 if ((hi>>i)&1) {
596 fc(10, &n); fc(8, &n); // low-high transition
597 } else {
598 fc(8, &n); fc(10, &n); // high-low transition
599 }
600 }
601
602 WDT_HIT();
603 // manchester encode bits 31 to 0
604 for (i=31; i>=0; i--) {
605 if ((i%4)==3) fc(0,&n);
606 if ((lo>>i)&1) {
607 fc(10, &n); fc(8, &n); // low-high transition
608 } else {
609 fc(8, &n); fc(10, &n); // high-low transition
610 }
611 }
612
613 if (ledcontrol)
614 LED_A_ON();
615 SimulateTagLowFrequency(n, 0, ledcontrol);
616
617 if (ledcontrol)
618 LED_A_OFF();
619 }
620
621 size_t fsk_demod(uint8_t * dest, size_t size)
622 {
623 uint32_t last_transition = 0;
624 uint32_t idx = 1;
625
626 // we don't care about actual value, only if it's more or less than a
627 // threshold essentially we capture zero crossings for later analysis
628 uint8_t threshold_value = 127;
629
630 // sync to first lo-hi transition, and threshold
631
632 //Need to threshold first sample
633 if(dest[0] < threshold_value) dest[0] = 0;
634 else dest[0] = 1;
635
636 size_t numBits = 0;
637 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
638 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
639 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
640 for(idx = 1; idx < size; idx++) {
641 // threshold current value
642 if (dest[idx] < threshold_value) dest[idx] = 0;
643 else dest[idx] = 1;
644
645 // Check for 0->1 transition
646 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
647
648 if (idx-last_transition < 9) {
649 dest[numBits]=1;
650 } else {
651 dest[numBits]=0;
652 }
653 last_transition = idx;
654 numBits++;
655 }
656 }
657 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
658 }
659
660
661 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
662 {
663 uint8_t lastval=dest[0];
664 uint32_t idx=0;
665 size_t numBits=0;
666 uint32_t n=1;
667
668 for( idx=1; idx < size; idx++) {
669
670 if (dest[idx]==lastval) {
671 n++;
672 continue;
673 }
674 //if lastval was 1, we have a 1->0 crossing
675 if ( dest[idx-1] ) {
676 n=(n+1) / h2l_crossing_value;
677 } else {// 0->1 crossing
678 n=(n+1) / l2h_crossing_value;
679 }
680 if (n == 0) n = 1;
681
682 if(n < maxConsequtiveBits)
683 {
684 memset(dest+numBits, dest[idx-1] , n);
685 numBits += n;
686 }
687 n=0;
688 lastval=dest[idx];
689 }//end for
690
691 return numBits;
692
693 }
694 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
695 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
696 {
697 uint8_t *dest = (uint8_t *)BigBuf;
698
699 size_t size=0,idx=0; //, found=0;
700 uint32_t hi2=0, hi=0, lo=0;
701
702
703 while(!BUTTON_PRESS()) {
704
705 // Configure to go in 125Khz listen mode
706 LFSetupFPGAForADC(0, true);
707
708 WDT_HIT();
709 if (ledcontrol) LED_A_ON();
710
711 DoAcquisition125k_internal(-1,true);
712 size = sizeof(BigBuf);
713
714 // FSK demodulator
715 size = fsk_demod(dest, size);
716 WDT_HIT();
717
718 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
719 // 1->0 : fc/8 in sets of 6
720 // 0->1 : fc/10 in sets of 5
721 size = aggregate_bits(dest,size, 6,5,5);
722
723 WDT_HIT();
724
725 // final loop, go over previously decoded manchester data and decode into usable tag ID
726 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
727 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
728 int numshifts = 0;
729 idx = 0;
730 while( idx + sizeof(frame_marker_mask) < size) {
731 // search for a start of frame marker
732 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
733 { // frame marker found
734 idx+=sizeof(frame_marker_mask);
735
736 while(dest[idx] != dest[idx+1] && idx < size-2)
737 { // Keep going until next frame marker (or error)
738 // Shift in a bit. Start by shifting high registers
739 hi2 = (hi2<<1)|(hi>>31);
740 hi = (hi<<1)|(lo>>31);
741 //Then, shift in a 0 or one into low
742 if (dest[idx] && !dest[idx+1]) // 1 0
743 lo=(lo<<1)|0;
744 else // 0 1
745 lo=(lo<<1)|
746 1;
747 numshifts ++;
748 idx += 2;
749 }
750 //Dbprintf("Num shifts: %d ", numshifts);
751 // Hopefully, we read a tag and hit upon the next frame marker
752 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
753 {
754 if (hi2 != 0){
755 Dbprintf("TAG ID: %x%08x%08x (%d)",
756 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
757 }
758 else {
759 Dbprintf("TAG ID: %x%08x (%d)",
760 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
761 }
762 }
763
764 // reset
765 hi2 = hi = lo = 0;
766 numshifts = 0;
767 }else
768 {
769 idx++;
770 }
771 }
772 WDT_HIT();
773
774 }
775 DbpString("Stopped");
776 if (ledcontrol) LED_A_OFF();
777 }
778
779 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
780 {
781 uint32_t num = 0;
782 for(int i = 0 ; i < numbits ; i++)
783 {
784 num = (num << 1) | (*src);
785 src++;
786 }
787 return num;
788 }
789
790
791 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
792 {
793 uint8_t *dest = (uint8_t *)BigBuf;
794
795 size_t size=0, idx=0;
796 uint32_t code=0, code2=0;
797
798
799 while(!BUTTON_PRESS()) {
800
801 // Configure to go in 125Khz listen mode
802 LFSetupFPGAForADC(0, true);
803
804 WDT_HIT();
805 if (ledcontrol) LED_A_ON();
806
807 DoAcquisition125k_internal(-1,true);
808 size = sizeof(BigBuf);
809
810 // FSK demodulator
811 size = fsk_demod(dest, size);
812 WDT_HIT();
813
814 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
815 // 1->0 : fc/8 in sets of 7
816 // 0->1 : fc/10 in sets of 6
817 size = aggregate_bits(dest, size, 7,6,13);
818
819 WDT_HIT();
820
821 //Handle the data
822 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
823 for( idx=0; idx < size - 64; idx++) {
824
825 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
826
827 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
828 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
829 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
830 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
831 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
832 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
833 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
834 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
835
836 code = bytebits_to_byte(dest+idx,32);
837 code2 = bytebits_to_byte(dest+idx+32,32);
838
839 short version = bytebits_to_byte(dest+idx+14,4);
840 char unknown = bytebits_to_byte(dest+idx+19,8) ;
841 uint16_t number = bytebits_to_byte(dest+idx+36,9);
842
843 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,unknown,number,code,code2);
844 if (ledcontrol) LED_D_OFF();
845
846 // if we're only looking for one tag
847 if (findone){
848 LED_A_OFF();
849 return;
850 }
851 }
852 WDT_HIT();
853 }
854 DbpString("Stopped");
855 if (ledcontrol) LED_A_OFF();
856 }
857
858 /*------------------------------
859 * T5555/T5557/T5567 routines
860 *------------------------------
861 */
862
863 /* T55x7 configuration register definitions */
864 #define T55x7_POR_DELAY 0x00000001
865 #define T55x7_ST_TERMINATOR 0x00000008
866 #define T55x7_PWD 0x00000010
867 #define T55x7_MAXBLOCK_SHIFT 5
868 #define T55x7_AOR 0x00000200
869 #define T55x7_PSKCF_RF_2 0
870 #define T55x7_PSKCF_RF_4 0x00000400
871 #define T55x7_PSKCF_RF_8 0x00000800
872 #define T55x7_MODULATION_DIRECT 0
873 #define T55x7_MODULATION_PSK1 0x00001000
874 #define T55x7_MODULATION_PSK2 0x00002000
875 #define T55x7_MODULATION_PSK3 0x00003000
876 #define T55x7_MODULATION_FSK1 0x00004000
877 #define T55x7_MODULATION_FSK2 0x00005000
878 #define T55x7_MODULATION_FSK1a 0x00006000
879 #define T55x7_MODULATION_FSK2a 0x00007000
880 #define T55x7_MODULATION_MANCHESTER 0x00008000
881 #define T55x7_MODULATION_BIPHASE 0x00010000
882 #define T55x7_BITRATE_RF_8 0
883 #define T55x7_BITRATE_RF_16 0x00040000
884 #define T55x7_BITRATE_RF_32 0x00080000
885 #define T55x7_BITRATE_RF_40 0x000C0000
886 #define T55x7_BITRATE_RF_50 0x00100000
887 #define T55x7_BITRATE_RF_64 0x00140000
888 #define T55x7_BITRATE_RF_100 0x00180000
889 #define T55x7_BITRATE_RF_128 0x001C0000
890
891 /* T5555 (Q5) configuration register definitions */
892 #define T5555_ST_TERMINATOR 0x00000001
893 #define T5555_MAXBLOCK_SHIFT 0x00000001
894 #define T5555_MODULATION_MANCHESTER 0
895 #define T5555_MODULATION_PSK1 0x00000010
896 #define T5555_MODULATION_PSK2 0x00000020
897 #define T5555_MODULATION_PSK3 0x00000030
898 #define T5555_MODULATION_FSK1 0x00000040
899 #define T5555_MODULATION_FSK2 0x00000050
900 #define T5555_MODULATION_BIPHASE 0x00000060
901 #define T5555_MODULATION_DIRECT 0x00000070
902 #define T5555_INVERT_OUTPUT 0x00000080
903 #define T5555_PSK_RF_2 0
904 #define T5555_PSK_RF_4 0x00000100
905 #define T5555_PSK_RF_8 0x00000200
906 #define T5555_USE_PWD 0x00000400
907 #define T5555_USE_AOR 0x00000800
908 #define T5555_BITRATE_SHIFT 12
909 #define T5555_FAST_WRITE 0x00004000
910 #define T5555_PAGE_SELECT 0x00008000
911
912 /*
913 * Relevant times in microsecond
914 * To compensate antenna falling times shorten the write times
915 * and enlarge the gap ones.
916 */
917 #define START_GAP 250
918 #define WRITE_GAP 160
919 #define WRITE_0 144 // 192
920 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
921
922 // Write one bit to card
923 void T55xxWriteBit(int bit)
924 {
925 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
926 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
927 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
928 if (bit == 0)
929 SpinDelayUs(WRITE_0);
930 else
931 SpinDelayUs(WRITE_1);
932 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
933 SpinDelayUs(WRITE_GAP);
934 }
935
936 // Write one card block in page 0, no lock
937 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
938 {
939 unsigned int i;
940
941 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
942 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
943 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
944
945 // Give it a bit of time for the resonant antenna to settle.
946 // And for the tag to fully power up
947 SpinDelay(150);
948
949 // Now start writting
950 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
951 SpinDelayUs(START_GAP);
952
953 // Opcode
954 T55xxWriteBit(1);
955 T55xxWriteBit(0); //Page 0
956 if (PwdMode == 1){
957 // Pwd
958 for (i = 0x80000000; i != 0; i >>= 1)
959 T55xxWriteBit(Pwd & i);
960 }
961 // Lock bit
962 T55xxWriteBit(0);
963
964 // Data
965 for (i = 0x80000000; i != 0; i >>= 1)
966 T55xxWriteBit(Data & i);
967
968 // Block
969 for (i = 0x04; i != 0; i >>= 1)
970 T55xxWriteBit(Block & i);
971
972 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
973 // so wait a little more)
974 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
975 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
976 SpinDelay(20);
977 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
978 }
979
980 // Read one card block in page 0
981 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
982 {
983 uint8_t *dest = (uint8_t *)BigBuf;
984 int m=0, i=0;
985
986 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
987 m = sizeof(BigBuf);
988 // Clear destination buffer before sending the command
989 memset(dest, 128, m);
990 // Connect the A/D to the peak-detected low-frequency path.
991 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
992 // Now set up the SSC to get the ADC samples that are now streaming at us.
993 FpgaSetupSsc();
994
995 LED_D_ON();
996 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
997 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
998
999 // Give it a bit of time for the resonant antenna to settle.
1000 // And for the tag to fully power up
1001 SpinDelay(150);
1002
1003 // Now start writting
1004 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1005 SpinDelayUs(START_GAP);
1006
1007 // Opcode
1008 T55xxWriteBit(1);
1009 T55xxWriteBit(0); //Page 0
1010 if (PwdMode == 1){
1011 // Pwd
1012 for (i = 0x80000000; i != 0; i >>= 1)
1013 T55xxWriteBit(Pwd & i);
1014 }
1015 // Lock bit
1016 T55xxWriteBit(0);
1017 // Block
1018 for (i = 0x04; i != 0; i >>= 1)
1019 T55xxWriteBit(Block & i);
1020
1021 // Turn field on to read the response
1022 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1023 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1024
1025 // Now do the acquisition
1026 i = 0;
1027 for(;;) {
1028 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1029 AT91C_BASE_SSC->SSC_THR = 0x43;
1030 }
1031 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1032 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1033 // we don't care about actual value, only if it's more or less than a
1034 // threshold essentially we capture zero crossings for later analysis
1035 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1036 i++;
1037 if (i >= m) break;
1038 }
1039 }
1040
1041 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1042 LED_D_OFF();
1043 DbpString("DONE!");
1044 }
1045
1046 // Read card traceability data (page 1)
1047 void T55xxReadTrace(void){
1048 uint8_t *dest = (uint8_t *)BigBuf;
1049 int m=0, i=0;
1050
1051 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1052 m = sizeof(BigBuf);
1053 // Clear destination buffer before sending the command
1054 memset(dest, 128, m);
1055 // Connect the A/D to the peak-detected low-frequency path.
1056 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1057 // Now set up the SSC to get the ADC samples that are now streaming at us.
1058 FpgaSetupSsc();
1059
1060 LED_D_ON();
1061 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1062 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1063
1064 // Give it a bit of time for the resonant antenna to settle.
1065 // And for the tag to fully power up
1066 SpinDelay(150);
1067
1068 // Now start writting
1069 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1070 SpinDelayUs(START_GAP);
1071
1072 // Opcode
1073 T55xxWriteBit(1);
1074 T55xxWriteBit(1); //Page 1
1075
1076 // Turn field on to read the response
1077 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1078 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1079
1080 // Now do the acquisition
1081 i = 0;
1082 for(;;) {
1083 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1084 AT91C_BASE_SSC->SSC_THR = 0x43;
1085 }
1086 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1087 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1088 i++;
1089 if (i >= m) break;
1090 }
1091 }
1092
1093 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1094 LED_D_OFF();
1095 DbpString("DONE!");
1096 }
1097
1098 /*-------------- Cloning routines -----------*/
1099 // Copy HID id to card and setup block 0 config
1100 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1101 {
1102 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1103 int last_block = 0;
1104
1105 if (longFMT){
1106 // Ensure no more than 84 bits supplied
1107 if (hi2>0xFFFFF) {
1108 DbpString("Tags can only have 84 bits.");
1109 return;
1110 }
1111 // Build the 6 data blocks for supplied 84bit ID
1112 last_block = 6;
1113 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1114 for (int i=0;i<4;i++) {
1115 if (hi2 & (1<<(19-i)))
1116 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1117 else
1118 data1 |= (1<<((3-i)*2)); // 0 -> 01
1119 }
1120
1121 data2 = 0;
1122 for (int i=0;i<16;i++) {
1123 if (hi2 & (1<<(15-i)))
1124 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1125 else
1126 data2 |= (1<<((15-i)*2)); // 0 -> 01
1127 }
1128
1129 data3 = 0;
1130 for (int i=0;i<16;i++) {
1131 if (hi & (1<<(31-i)))
1132 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1133 else
1134 data3 |= (1<<((15-i)*2)); // 0 -> 01
1135 }
1136
1137 data4 = 0;
1138 for (int i=0;i<16;i++) {
1139 if (hi & (1<<(15-i)))
1140 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1141 else
1142 data4 |= (1<<((15-i)*2)); // 0 -> 01
1143 }
1144
1145 data5 = 0;
1146 for (int i=0;i<16;i++) {
1147 if (lo & (1<<(31-i)))
1148 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1149 else
1150 data5 |= (1<<((15-i)*2)); // 0 -> 01
1151 }
1152
1153 data6 = 0;
1154 for (int i=0;i<16;i++) {
1155 if (lo & (1<<(15-i)))
1156 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1157 else
1158 data6 |= (1<<((15-i)*2)); // 0 -> 01
1159 }
1160 }
1161 else {
1162 // Ensure no more than 44 bits supplied
1163 if (hi>0xFFF) {
1164 DbpString("Tags can only have 44 bits.");
1165 return;
1166 }
1167
1168 // Build the 3 data blocks for supplied 44bit ID
1169 last_block = 3;
1170
1171 data1 = 0x1D000000; // load preamble
1172
1173 for (int i=0;i<12;i++) {
1174 if (hi & (1<<(11-i)))
1175 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1176 else
1177 data1 |= (1<<((11-i)*2)); // 0 -> 01
1178 }
1179
1180 data2 = 0;
1181 for (int i=0;i<16;i++) {
1182 if (lo & (1<<(31-i)))
1183 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1184 else
1185 data2 |= (1<<((15-i)*2)); // 0 -> 01
1186 }
1187
1188 data3 = 0;
1189 for (int i=0;i<16;i++) {
1190 if (lo & (1<<(15-i)))
1191 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1192 else
1193 data3 |= (1<<((15-i)*2)); // 0 -> 01
1194 }
1195 }
1196
1197 LED_D_ON();
1198 // Program the data blocks for supplied ID
1199 // and the block 0 for HID format
1200 T55xxWriteBlock(data1,1,0,0);
1201 T55xxWriteBlock(data2,2,0,0);
1202 T55xxWriteBlock(data3,3,0,0);
1203
1204 if (longFMT) { // if long format there are 6 blocks
1205 T55xxWriteBlock(data4,4,0,0);
1206 T55xxWriteBlock(data5,5,0,0);
1207 T55xxWriteBlock(data6,6,0,0);
1208 }
1209
1210 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1211 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1212 T55x7_MODULATION_FSK2a |
1213 last_block << T55x7_MAXBLOCK_SHIFT,
1214 0,0,0);
1215
1216 LED_D_OFF();
1217
1218 DbpString("DONE!");
1219 }
1220
1221 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1222 {
1223 int data1=0, data2=0; //up to six blocks for long format
1224
1225 data1 = hi; // load preamble
1226 data2 = lo;
1227
1228 LED_D_ON();
1229 // Program the data blocks for supplied ID
1230 // and the block 0 for HID format
1231 T55xxWriteBlock(data1,1,0,0);
1232 T55xxWriteBlock(data2,2,0,0);
1233
1234 //Config Block
1235 T55xxWriteBlock(0x00147040,0,0,0);
1236 LED_D_OFF();
1237
1238 DbpString("DONE!");
1239 }
1240
1241 // Define 9bit header for EM410x tags
1242 #define EM410X_HEADER 0x1FF
1243 #define EM410X_ID_LENGTH 40
1244
1245 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1246 {
1247 int i, id_bit;
1248 uint64_t id = EM410X_HEADER;
1249 uint64_t rev_id = 0; // reversed ID
1250 int c_parity[4]; // column parity
1251 int r_parity = 0; // row parity
1252 uint32_t clock = 0;
1253
1254 // Reverse ID bits given as parameter (for simpler operations)
1255 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1256 if (i < 32) {
1257 rev_id = (rev_id << 1) | (id_lo & 1);
1258 id_lo >>= 1;
1259 } else {
1260 rev_id = (rev_id << 1) | (id_hi & 1);
1261 id_hi >>= 1;
1262 }
1263 }
1264
1265 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1266 id_bit = rev_id & 1;
1267
1268 if (i % 4 == 0) {
1269 // Don't write row parity bit at start of parsing
1270 if (i)
1271 id = (id << 1) | r_parity;
1272 // Start counting parity for new row
1273 r_parity = id_bit;
1274 } else {
1275 // Count row parity
1276 r_parity ^= id_bit;
1277 }
1278
1279 // First elements in column?
1280 if (i < 4)
1281 // Fill out first elements
1282 c_parity[i] = id_bit;
1283 else
1284 // Count column parity
1285 c_parity[i % 4] ^= id_bit;
1286
1287 // Insert ID bit
1288 id = (id << 1) | id_bit;
1289 rev_id >>= 1;
1290 }
1291
1292 // Insert parity bit of last row
1293 id = (id << 1) | r_parity;
1294
1295 // Fill out column parity at the end of tag
1296 for (i = 0; i < 4; ++i)
1297 id = (id << 1) | c_parity[i];
1298
1299 // Add stop bit
1300 id <<= 1;
1301
1302 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1303 LED_D_ON();
1304
1305 // Write EM410x ID
1306 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1307 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1308
1309 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1310 if (card) {
1311 // Clock rate is stored in bits 8-15 of the card value
1312 clock = (card & 0xFF00) >> 8;
1313 Dbprintf("Clock rate: %d", clock);
1314 switch (clock)
1315 {
1316 case 32:
1317 clock = T55x7_BITRATE_RF_32;
1318 break;
1319 case 16:
1320 clock = T55x7_BITRATE_RF_16;
1321 break;
1322 case 0:
1323 // A value of 0 is assumed to be 64 for backwards-compatibility
1324 // Fall through...
1325 case 64:
1326 clock = T55x7_BITRATE_RF_64;
1327 break;
1328 default:
1329 Dbprintf("Invalid clock rate: %d", clock);
1330 return;
1331 }
1332
1333 // Writing configuration for T55x7 tag
1334 T55xxWriteBlock(clock |
1335 T55x7_MODULATION_MANCHESTER |
1336 2 << T55x7_MAXBLOCK_SHIFT,
1337 0, 0, 0);
1338 }
1339 else
1340 // Writing configuration for T5555(Q5) tag
1341 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1342 T5555_MODULATION_MANCHESTER |
1343 2 << T5555_MAXBLOCK_SHIFT,
1344 0, 0, 0);
1345
1346 LED_D_OFF();
1347 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1348 (uint32_t)(id >> 32), (uint32_t)id);
1349 }
1350
1351 // Clone Indala 64-bit tag by UID to T55x7
1352 void CopyIndala64toT55x7(int hi, int lo)
1353 {
1354
1355 //Program the 2 data blocks for supplied 64bit UID
1356 // and the block 0 for Indala64 format
1357 T55xxWriteBlock(hi,1,0,0);
1358 T55xxWriteBlock(lo,2,0,0);
1359 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1360 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1361 T55x7_MODULATION_PSK1 |
1362 2 << T55x7_MAXBLOCK_SHIFT,
1363 0, 0, 0);
1364 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1365 // T5567WriteBlock(0x603E1042,0);
1366
1367 DbpString("DONE!");
1368
1369 }
1370
1371 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1372 {
1373
1374 //Program the 7 data blocks for supplied 224bit UID
1375 // and the block 0 for Indala224 format
1376 T55xxWriteBlock(uid1,1,0,0);
1377 T55xxWriteBlock(uid2,2,0,0);
1378 T55xxWriteBlock(uid3,3,0,0);
1379 T55xxWriteBlock(uid4,4,0,0);
1380 T55xxWriteBlock(uid5,5,0,0);
1381 T55xxWriteBlock(uid6,6,0,0);
1382 T55xxWriteBlock(uid7,7,0,0);
1383 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1384 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1385 T55x7_MODULATION_PSK1 |
1386 7 << T55x7_MAXBLOCK_SHIFT,
1387 0,0,0);
1388 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1389 // T5567WriteBlock(0x603E10E2,0);
1390
1391 DbpString("DONE!");
1392
1393 }
1394
1395
1396 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1397 #define max(x,y) ( x<y ? y:x)
1398
1399 int DemodPCF7931(uint8_t **outBlocks) {
1400 uint8_t BitStream[256];
1401 uint8_t Blocks[8][16];
1402 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1403 int GraphTraceLen = sizeof(BigBuf);
1404 int i, j, lastval, bitidx, half_switch;
1405 int clock = 64;
1406 int tolerance = clock / 8;
1407 int pmc, block_done;
1408 int lc, warnings = 0;
1409 int num_blocks = 0;
1410 int lmin=128, lmax=128;
1411 uint8_t dir;
1412
1413 AcquireRawAdcSamples125k(0);
1414
1415 lmin = 64;
1416 lmax = 192;
1417
1418 i = 2;
1419
1420 /* Find first local max/min */
1421 if(GraphBuffer[1] > GraphBuffer[0]) {
1422 while(i < GraphTraceLen) {
1423 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1424 break;
1425 i++;
1426 }
1427 dir = 0;
1428 }
1429 else {
1430 while(i < GraphTraceLen) {
1431 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1432 break;
1433 i++;
1434 }
1435 dir = 1;
1436 }
1437
1438 lastval = i++;
1439 half_switch = 0;
1440 pmc = 0;
1441 block_done = 0;
1442
1443 for (bitidx = 0; i < GraphTraceLen; i++)
1444 {
1445 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1446 {
1447 lc = i - lastval;
1448 lastval = i;
1449
1450 // Switch depending on lc length:
1451 // Tolerance is 1/8 of clock rate (arbitrary)
1452 if (abs(lc-clock/4) < tolerance) {
1453 // 16T0
1454 if((i - pmc) == lc) { /* 16T0 was previous one */
1455 /* It's a PMC ! */
1456 i += (128+127+16+32+33+16)-1;
1457 lastval = i;
1458 pmc = 0;
1459 block_done = 1;
1460 }
1461 else {
1462 pmc = i;
1463 }
1464 } else if (abs(lc-clock/2) < tolerance) {
1465 // 32TO
1466 if((i - pmc) == lc) { /* 16T0 was previous one */
1467 /* It's a PMC ! */
1468 i += (128+127+16+32+33)-1;
1469 lastval = i;
1470 pmc = 0;
1471 block_done = 1;
1472 }
1473 else if(half_switch == 1) {
1474 BitStream[bitidx++] = 0;
1475 half_switch = 0;
1476 }
1477 else
1478 half_switch++;
1479 } else if (abs(lc-clock) < tolerance) {
1480 // 64TO
1481 BitStream[bitidx++] = 1;
1482 } else {
1483 // Error
1484 warnings++;
1485 if (warnings > 10)
1486 {
1487 Dbprintf("Error: too many detection errors, aborting.");
1488 return 0;
1489 }
1490 }
1491
1492 if(block_done == 1) {
1493 if(bitidx == 128) {
1494 for(j=0; j<16; j++) {
1495 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1496 64*BitStream[j*8+6]+
1497 32*BitStream[j*8+5]+
1498 16*BitStream[j*8+4]+
1499 8*BitStream[j*8+3]+
1500 4*BitStream[j*8+2]+
1501 2*BitStream[j*8+1]+
1502 BitStream[j*8];
1503 }
1504 num_blocks++;
1505 }
1506 bitidx = 0;
1507 block_done = 0;
1508 half_switch = 0;
1509 }
1510 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1511 else dir = 1;
1512 }
1513 if(bitidx==255)
1514 bitidx=0;
1515 warnings = 0;
1516 if(num_blocks == 4) break;
1517 }
1518 memcpy(outBlocks, Blocks, 16*num_blocks);
1519 return num_blocks;
1520 }
1521
1522 int IsBlock0PCF7931(uint8_t *Block) {
1523 // Assume RFU means 0 :)
1524 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1525 return 1;
1526 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1527 return 1;
1528 return 0;
1529 }
1530
1531 int IsBlock1PCF7931(uint8_t *Block) {
1532 // Assume RFU means 0 :)
1533 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1534 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1535 return 1;
1536
1537 return 0;
1538 }
1539
1540 #define ALLOC 16
1541
1542 void ReadPCF7931() {
1543 uint8_t Blocks[8][17];
1544 uint8_t tmpBlocks[4][16];
1545 int i, j, ind, ind2, n;
1546 int num_blocks = 0;
1547 int max_blocks = 8;
1548 int ident = 0;
1549 int error = 0;
1550 int tries = 0;
1551
1552 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1553
1554 do {
1555 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1556 n = DemodPCF7931((uint8_t**)tmpBlocks);
1557 if(!n)
1558 error++;
1559 if(error==10 && num_blocks == 0) {
1560 Dbprintf("Error, no tag or bad tag");
1561 return;
1562 }
1563 else if (tries==20 || error==10) {
1564 Dbprintf("Error reading the tag");
1565 Dbprintf("Here is the partial content");
1566 goto end;
1567 }
1568
1569 for(i=0; i<n; i++)
1570 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1571 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1572 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1573 if(!ident) {
1574 for(i=0; i<n; i++) {
1575 if(IsBlock0PCF7931(tmpBlocks[i])) {
1576 // Found block 0 ?
1577 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1578 // Found block 1!
1579 // \o/
1580 ident = 1;
1581 memcpy(Blocks[0], tmpBlocks[i], 16);
1582 Blocks[0][ALLOC] = 1;
1583 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1584 Blocks[1][ALLOC] = 1;
1585 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1586 // Debug print
1587 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1588 num_blocks = 2;
1589 // Handle following blocks
1590 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1591 if(j==n) j=0;
1592 if(j==i) break;
1593 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1594 Blocks[ind2][ALLOC] = 1;
1595 }
1596 break;
1597 }
1598 }
1599 }
1600 }
1601 else {
1602 for(i=0; i<n; i++) { // Look for identical block in known blocks
1603 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1604 for(j=0; j<max_blocks; j++) {
1605 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1606 // Found an identical block
1607 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1608 if(ind2 < 0)
1609 ind2 = max_blocks;
1610 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1611 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1612 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1613 Blocks[ind2][ALLOC] = 1;
1614 num_blocks++;
1615 if(num_blocks == max_blocks) goto end;
1616 }
1617 }
1618 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1619 if(ind2 > max_blocks)
1620 ind2 = 0;
1621 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1622 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1623 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1624 Blocks[ind2][ALLOC] = 1;
1625 num_blocks++;
1626 if(num_blocks == max_blocks) goto end;
1627 }
1628 }
1629 }
1630 }
1631 }
1632 }
1633 }
1634 tries++;
1635 if (BUTTON_PRESS()) return;
1636 } while (num_blocks != max_blocks);
1637 end:
1638 Dbprintf("-----------------------------------------");
1639 Dbprintf("Memory content:");
1640 Dbprintf("-----------------------------------------");
1641 for(i=0; i<max_blocks; i++) {
1642 if(Blocks[i][ALLOC]==1)
1643 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1644 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1645 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1646 else
1647 Dbprintf("<missing block %d>", i);
1648 }
1649 Dbprintf("-----------------------------------------");
1650
1651 return ;
1652 }
1653
1654
1655 //-----------------------------------
1656 // EM4469 / EM4305 routines
1657 //-----------------------------------
1658 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1659 #define FWD_CMD_WRITE 0xA
1660 #define FWD_CMD_READ 0x9
1661 #define FWD_CMD_DISABLE 0x5
1662
1663
1664 uint8_t forwardLink_data[64]; //array of forwarded bits
1665 uint8_t * forward_ptr; //ptr for forward message preparation
1666 uint8_t fwd_bit_sz; //forwardlink bit counter
1667 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1668
1669 //====================================================================
1670 // prepares command bits
1671 // see EM4469 spec
1672 //====================================================================
1673 //--------------------------------------------------------------------
1674 uint8_t Prepare_Cmd( uint8_t cmd ) {
1675 //--------------------------------------------------------------------
1676
1677 *forward_ptr++ = 0; //start bit
1678 *forward_ptr++ = 0; //second pause for 4050 code
1679
1680 *forward_ptr++ = cmd;
1681 cmd >>= 1;
1682 *forward_ptr++ = cmd;
1683 cmd >>= 1;
1684 *forward_ptr++ = cmd;
1685 cmd >>= 1;
1686 *forward_ptr++ = cmd;
1687
1688 return 6; //return number of emited bits
1689 }
1690
1691 //====================================================================
1692 // prepares address bits
1693 // see EM4469 spec
1694 //====================================================================
1695
1696 //--------------------------------------------------------------------
1697 uint8_t Prepare_Addr( uint8_t addr ) {
1698 //--------------------------------------------------------------------
1699
1700 register uint8_t line_parity;
1701
1702 uint8_t i;
1703 line_parity = 0;
1704 for(i=0;i<6;i++) {
1705 *forward_ptr++ = addr;
1706 line_parity ^= addr;
1707 addr >>= 1;
1708 }
1709
1710 *forward_ptr++ = (line_parity & 1);
1711
1712 return 7; //return number of emited bits
1713 }
1714
1715 //====================================================================
1716 // prepares data bits intreleaved with parity bits
1717 // see EM4469 spec
1718 //====================================================================
1719
1720 //--------------------------------------------------------------------
1721 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1722 //--------------------------------------------------------------------
1723
1724 register uint8_t line_parity;
1725 register uint8_t column_parity;
1726 register uint8_t i, j;
1727 register uint16_t data;
1728
1729 data = data_low;
1730 column_parity = 0;
1731
1732 for(i=0; i<4; i++) {
1733 line_parity = 0;
1734 for(j=0; j<8; j++) {
1735 line_parity ^= data;
1736 column_parity ^= (data & 1) << j;
1737 *forward_ptr++ = data;
1738 data >>= 1;
1739 }
1740 *forward_ptr++ = line_parity;
1741 if(i == 1)
1742 data = data_hi;
1743 }
1744
1745 for(j=0; j<8; j++) {
1746 *forward_ptr++ = column_parity;
1747 column_parity >>= 1;
1748 }
1749 *forward_ptr = 0;
1750
1751 return 45; //return number of emited bits
1752 }
1753
1754 //====================================================================
1755 // Forward Link send function
1756 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1757 // fwd_bit_count set with number of bits to be sent
1758 //====================================================================
1759 void SendForward(uint8_t fwd_bit_count) {
1760
1761 fwd_write_ptr = forwardLink_data;
1762 fwd_bit_sz = fwd_bit_count;
1763
1764 LED_D_ON();
1765
1766 //Field on
1767 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1768 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1769 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1770
1771 // Give it a bit of time for the resonant antenna to settle.
1772 // And for the tag to fully power up
1773 SpinDelay(150);
1774
1775 // force 1st mod pulse (start gap must be longer for 4305)
1776 fwd_bit_sz--; //prepare next bit modulation
1777 fwd_write_ptr++;
1778 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1779 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1780 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1781 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1782 SpinDelayUs(16*8); //16 cycles on (8us each)
1783
1784 // now start writting
1785 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1786 if(((*fwd_write_ptr++) & 1) == 1)
1787 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1788 else {
1789 //These timings work for 4469/4269/4305 (with the 55*8 above)
1790 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1791 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1792 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1793 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1794 SpinDelayUs(9*8); //16 cycles on (8us each)
1795 }
1796 }
1797 }
1798
1799 void EM4xLogin(uint32_t Password) {
1800
1801 uint8_t fwd_bit_count;
1802
1803 forward_ptr = forwardLink_data;
1804 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1805 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1806
1807 SendForward(fwd_bit_count);
1808
1809 //Wait for command to complete
1810 SpinDelay(20);
1811
1812 }
1813
1814 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1815
1816 uint8_t fwd_bit_count;
1817 uint8_t *dest = (uint8_t *)BigBuf;
1818 int m=0, i=0;
1819
1820 //If password mode do login
1821 if (PwdMode == 1) EM4xLogin(Pwd);
1822
1823 forward_ptr = forwardLink_data;
1824 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1825 fwd_bit_count += Prepare_Addr( Address );
1826
1827 m = sizeof(BigBuf);
1828 // Clear destination buffer before sending the command
1829 memset(dest, 128, m);
1830 // Connect the A/D to the peak-detected low-frequency path.
1831 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1832 // Now set up the SSC to get the ADC samples that are now streaming at us.
1833 FpgaSetupSsc();
1834
1835 SendForward(fwd_bit_count);
1836
1837 // Now do the acquisition
1838 i = 0;
1839 for(;;) {
1840 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1841 AT91C_BASE_SSC->SSC_THR = 0x43;
1842 }
1843 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1844 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1845 i++;
1846 if (i >= m) break;
1847 }
1848 }
1849 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1850 LED_D_OFF();
1851 }
1852
1853 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1854
1855 uint8_t fwd_bit_count;
1856
1857 //If password mode do login
1858 if (PwdMode == 1) EM4xLogin(Pwd);
1859
1860 forward_ptr = forwardLink_data;
1861 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1862 fwd_bit_count += Prepare_Addr( Address );
1863 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1864
1865 SendForward(fwd_bit_count);
1866
1867 //Wait for write to complete
1868 SpinDelay(20);
1869 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1870 LED_D_OFF();
1871 }
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