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git.zerfleddert.de Git - proxmark3-svn/blob - common/protocols.h
39fed40f7ff324e1cd54d06aa47c9f5fed700ea3
4 //The following data is taken from http://www.proxmark.org/forum/viewtopic.php?pid=13501#p13501 6 ISO14443A (usually NFC tags) 8 30 = Read (usage: 30+1byte block number+2bytes ISO14443A-CRC - answer: 16bytes) 9 A2 = Write (usage: A2+1byte block number+4bytes data+2bytes ISO14443A-CRC - answer: 0A [ACK] or 00 [NAK]) 10 52 (7bits) = WUPA (usage: 52(7bits) - answer: 2bytes ATQA) 11 93 20 = Anticollision (usage: 9320 - answer: 4bytes UID+1byte UID-bytes-xor) 12 93 70 = Select (usage: 9370+5bytes 9320 answer - answer: 1byte SAK) 13 95 20 = Anticollision of cascade level2 14 95 70 = Select of cascade level2 15 50 00 = Halt (usage: 5000+2bytes ISO14443A-CRC - no answer from card) 17 60 = Authenticate with KeyA 18 61 = Authenticate with KeyB 19 40 (7bits) = Used to put Chinese Changeable UID cards in special mode (must be followed by 43 (8bits) - answer: 0A) 25 A0 = Compatibility Write (to accomodate MIFARE commands) 26 1A = Step1 Authenticate 27 AF = Step2 Authenticate 34 SRIX4K (tag does not respond to 05) 36 0E xx = SELECT ID (xx = Chip-ID) 38 08 yy = Read Block (yy = block number) 39 09 yy dd dd dd dd = Write Block (yy = block number; dd dd dd dd = data to be written) 40 0C = Reset to Inventory 42 0A 11 22 33 44 55 66 = Authenticate (11 22 33 44 55 66 = data to authenticate) 46 MANDATORY COMMANDS (all ISO15693 tags must support those) 47 01 = Inventory (usage: 260100+2bytes ISO15693-CRC - answer: 12bytes) 49 OPTIONAL COMMANDS (not all tags support them) 50 20 = Read Block (usage: 0220+1byte block number+2bytes ISO15693-CRC - answer: 4bytes) 51 21 = Write Block (usage: 0221+1byte block number+4bytes data+2bytes ISO15693-CRC - answer: 4bytes) 53 23 = Read Multiple Blocks (usage: 0223+1byte 1st block to read+1byte last block to read+2bytes ISO15693-CRC) 60 2B = Get_System_Info (usage: 022B+2bytes ISO15693-CRC - answer: 14 or more bytes) 61 2C = Read Multiple Block Security Status (usage: 022C+1byte 1st block security to read+1byte last block security to read+2bytes ISO15693-CRC) 63 EM Microelectronic CUSTOM COMMANDS 64 A5 = Active EAS (followed by 1byte IC Manufacturer code+1byte EAS type) 65 A7 = Write EAS ID (followed by 1byte IC Manufacturer code+2bytes EAS value) 66 B8 = Get Protection Status for a specific block (followed by 1byte IC Manufacturer code+1byte block number+1byte of how many blocks after the previous is needed the info) 67 E4 = Login (followed by 1byte IC Manufacturer code+4bytes password) 68 NXP/Philips CUSTOM COMMANDS 70 A1 = Fast Inventory Read 75 A6 = Password Protect EAS 78 B0 = Inventory Page Read 79 B1 = Fast Inventory Page Read 80 B2 = Get Random Number 84 B6 = Bit Password Protection 85 B7 = Lock Page Protection Condition 86 B8 = Get Multiple Block Protection Status 89 BB = 64bit Password Protection 90 40 = Long Range CMD (Standard ISO/TR7003:1990) 93 #define ICLASS_CMD_ACTALL 0x0A 94 #define ICLASS_CMD_READ_OR_IDENTIFY 0x0C 95 #define ICLASS_CMD_SELECT 0x81 96 #define ICLASS_CMD_PAGESEL 0x84 97 #define ICLASS_CMD_READCHECK_KD 0x88 98 #define ICLASS_CMD_READCHECK_KC 0x18 99 #define ICLASS_CMD_CHECK 0x05 100 #define ICLASS_CMD_DETECT 0x0F 101 #define ICLASS_CMD_HALT 0x00 102 #define ICLASS_CMD_UPDATE 0x87 103 #define ICLASS_CMD_ACT 0x8E 104 #define ICLASS_CMD_READ4 0x06 107 #define ISO14443A_CMD_REQA 0x26 108 #define ISO14443A_CMD_READBLOCK 0x30 109 #define ISO14443A_CMD_WUPA 0x52 110 #define ISO14443A_CMD_ANTICOLL_OR_SELECT 0x93 111 #define ISO14443A_CMD_ANTICOLL_OR_SELECT_2 0x95 112 #define ISO14443A_CMD_ANTICOLL_OR_SELECT_3 0x97 113 #define ISO14443A_CMD_WRITEBLOCK 0xA0 // or 0xA2 ? 114 #define ISO14443A_CMD_HALT 0x50 115 #define ISO14443A_CMD_RATS 0xE0 117 #define MIFARE_AUTH_KEYA 0x60 118 #define MIFARE_AUTH_KEYB 0x61 119 #define MIFARE_MAGICWUPC1 0x40 120 #define MIFARE_MAGICWUPC2 0x43 121 #define MIFARE_MAGICWIPEC 0x41 122 #define MIFARE_CMD_INC 0xC0 123 #define MIFARE_CMD_DEC 0xC1 124 #define MIFARE_CMD_RESTORE 0xC2 125 #define MIFARE_CMD_TRANSFER 0xB0 127 #define MIFARE_EV1_PERSONAL_UID 0x40 128 #define MIFARE_EV1_SETMODE 0x43 131 #define MIFARE_ULC_WRITE 0xA2 132 //#define MIFARE_ULC__COMP_WRITE 0xA0 133 #define MIFARE_ULC_AUTH_1 0x1A 134 #define MIFARE_ULC_AUTH_2 0xAF 136 #define MIFARE_ULEV1_AUTH 0x1B 137 #define MIFARE_ULEV1_VERSION 0x60 138 #define MIFARE_ULEV1_FASTREAD 0x3A 139 //#define MIFARE_ULEV1_WRITE 0xA2 140 //#define MIFARE_ULEV1_COMP_WRITE 0xA0 141 #define MIFARE_ULEV1_READ_CNT 0x39 142 #define MIFARE_ULEV1_INCR_CNT 0xA5 143 #define MIFARE_ULEV1_READSIG 0x3C 144 #define MIFARE_ULEV1_CHECKTEAR 0x3E 145 #define MIFARE_ULEV1_VCSL 0x4B 149 0E xx = SELECT ID (xx = Chip-ID) 151 08 yy = Read Block (yy = block number) 152 09 yy dd dd dd dd = Write Block (yy = block number; dd dd dd dd = data to be written) 153 0C = Reset to Inventory 155 0A 11 22 33 44 55 66 = Authenticate (11 22 33 44 55 66 = data to authenticate) 158 #define ISO14443B_REQB 0x05 159 #define ISO14443B_ATTRIB 0x1D 160 #define ISO14443B_HALT 0x50 161 #define ISO14443B_INITIATE 0x06 162 #define ISO14443B_SELECT 0x0E 163 #define ISO14443B_GET_UID 0x0B 164 #define ISO14443B_READ_BLK 0x08 165 #define ISO14443B_WRITE_BLK 0x09 166 #define ISO14443B_RESET 0x0C 167 #define ISO14443B_COMPLETION 0x0F 168 #define ISO14443B_AUTHENTICATE 0x0A 171 #define ISO15693_INVENTORY 0x01 172 #define ISO15693_STAYQUIET 0x02 173 #define ISO15693_READBLOCK 0x20 174 #define ISO15693_WRITEBLOCK 0x21 175 #define ISO15693_LOCKBLOCK 0x22 176 #define ISO15693_READ_MULTI_BLOCK 0x23 177 #define ISO15693_SELECT 0x25 178 #define ISO15693_RESET_TO_READY 0x26 179 #define ISO15693_WRITE_AFI 0x27 180 #define ISO15693_LOCK_AFI 0x28 181 #define ISO15693_WRITE_DSFID 0x29 182 #define ISO15693_LOCK_DSFID 0x2A 183 #define ISO15693_GET_SYSTEM_INFO 0x2B 184 #define ISO15693_READ_MULTI_SECSTATUS 0x2C 186 // ISO15693 REQUEST FLAGS 187 #define ISO15693_REQ_SUBCARRIER_TWO (1<<0) 188 #define ISO15693_REQ_DATARATE_HIGH (1<<1) 189 #define ISO15693_REQ_INVENTORY (1<<2) 190 #define ISO15693_REQ_PROTOCOL_EXT (1<<3) // RFU 191 #define ISO15693_REQ_OPTION (1<<6) // Command specific option selector 192 // when REQ_INVENTORY is not set 193 #define ISO15693_REQ_SELECT (1<<4) // only selected cards response 194 #define ISO15693_REQ_ADDRESS (1<<5) // this req contains an address 195 // when REQ_INVENTORY is set 196 #define ISO15693_REQINV_AFI (1<<4) // AFI Field is present 197 #define ISO15693_REQINV_SLOT1 (1<<5) // 1 Slot (16 slots if not set) 199 // ISO15693 RESPONSE FLAGS 200 #define ISO15693_RES_ERROR (1<<0) 201 #define ISO15693_RES_EXT (1<<3) // Protocol Extention 203 // ISO15693 RESPONSE ERROR CODES 204 #define ISO15693_NOERROR 0x00 205 #define ISO15693_ERROR_CMD_NOT_SUP 0x01 // Command not supported 206 #define ISO15693_ERROR_CMD_NOT_REC 0x02 // Command not recognized (eg. parameter error) 207 #define ISO15693_ERROR_CMD_OPTION 0x03 // Command option not supported 208 #define ISO15693_ERROR_GENERIC 0x0F // No additional Info about this error 209 #define ISO15693_ERROR_BLOCK_UNAVAILABLE 0x10 210 #define ISO15693_ERROR_BLOCK_LOCKED_ALREADY 0x11 // cannot lock again 211 #define ISO15693_ERROR_BLOCK_LOCKED 0x12 // cannot be changed 212 #define ISO15693_ERROR_BLOCK_WRITE 0x13 // Writing was unsuccessful 213 #define ISO15693_ERROR_BLOCL_WRITELOCK 0x14 // Locking was unsuccessful 216 // Topaz command set: 217 #define TOPAZ_REQA 0x26 // Request 218 #define TOPAZ_WUPA 0x52 // WakeUp 219 #define TOPAZ_RID 0x78 // Read ID 220 #define TOPAZ_RALL 0x00 // Read All (all bytes) 221 #define TOPAZ_READ 0x01 // Read (a single byte) 222 #define TOPAZ_WRITE_E 0x53 // Write-with-erase (a single byte) 223 #define TOPAZ_WRITE_NE 0x1a // Write-no-erase (a single byte) 224 // additional commands for Dynamic Memory Model 225 #define TOPAZ_RSEG 0x10 // Read segment 226 #define TOPAZ_READ8 0x02 // Read (eight bytes) 227 #define TOPAZ_WRITE_E8 0x54 // Write-with-erase (eight bytes) 228 #define TOPAZ_WRITE_NE8 0x1B // Write-no-erase (eight bytes) 235 #define PROTO_MIFARE 4 238 #define ISO_14443_4 7 242 #define FUSE_FPERS 0x80 243 #define FUSE_CODING1 0x40 244 #define FUSE_CODING0 0x20 245 #define FUSE_CRYPT1 0x10 246 #define FUSE_CRYPT0 0x08 247 #define FUSE_FPROD1 0x04 248 #define FUSE_FPROD0 0x02 251 // ISO 7816-4 Basic interindustry commands. For command APDU's. 252 #define ISO7816_ERASE_BINARY 0x0E 253 #define ISO7816_VERIFY 0x20 254 #define ISO7816_MANAGE_CHANNEL 0x70 255 #define ISO7816_EXTERNAL_AUTHENTICATE 0x82 256 #define ISO7816_GET_CHALLENGE 0x84 257 #define ISO7816_INTERNAL_AUTHENTICATE 0x88 258 #define ISO7816_SELECT_FILE 0xA4 259 #define ISO7816_GET_PROCESSING_OPTIONS 0xA8 260 #define ISO7816_READ_BINARY 0xB0 261 #define ISO7816_READ_RECORDS 0xB2 262 #define ISO7816_GET_RESPONSE 0xC0 263 #define ISO7816_ENVELOPE 0xC2 264 #define ISO7816_GET_DATA 0xCA 265 #define ISO7816_WRITE_BINARY 0xD0 266 #define ISO7816_WRITE_RECORD 0xD2 267 #define ISO7816_UPDATE_BINARY 0xD6 268 #define ISO7816_PUT_DATA 0xDA 269 #define ISO7816_UPDATE_DATA 0xDC 270 #define ISO7816_APPEND_RECORD 0xE2 271 // ISO7816-4 For response APDU's 272 #define ISO7816_OK 0x9000 274 #define ISO7816_MAX_FRAME_SIZE 261 278 void printIclassDumpInfo ( uint8_t * iclass_dump
); 279 void getMemConfig ( uint8_t mem_cfg
, uint8_t chip_cfg
, uint8_t * max_blk
, uint8_t * app_areas
, uint8_t * kb
); 281 /* T55x7 configuration register definitions */ 282 #define T55x7_POR_DELAY 0x00000001 283 #define T55x7_ST_TERMINATOR 0x00000008 284 #define T55x7_PWD 0x00000010 285 #define T55x7_MAXBLOCK_SHIFT 5 286 #define T55x7_AOR 0x00000200 287 #define T55x7_PSKCF_RF_2 0 288 #define T55x7_PSKCF_RF_4 0x00000400 289 #define T55x7_PSKCF_RF_8 0x00000800 290 #define T55x7_MODULATION_DIRECT 0 291 #define T55x7_MODULATION_PSK1 0x00001000 292 #define T55x7_MODULATION_PSK2 0x00002000 293 #define T55x7_MODULATION_PSK3 0x00003000 294 #define T55x7_MODULATION_FSK1 0x00004000 295 #define T55x7_MODULATION_FSK2 0x00005000 296 #define T55x7_MODULATION_FSK1a 0x00006000 297 #define T55x7_MODULATION_FSK2a 0x00007000 298 #define T55x7_MODULATION_MANCHESTER 0x00008000 299 #define T55x7_MODULATION_BIPHASE 0x00010000 300 #define T55x7_MODULATION_DIPHASE 0x00018000 301 #define T55x7_X_MODE 0x00020000 302 #define T55x7_BITRATE_RF_8 0 303 #define T55x7_BITRATE_RF_16 0x00040000 304 #define T55x7_BITRATE_RF_32 0x00080000 305 #define T55x7_BITRATE_RF_40 0x000C0000 306 #define T55x7_BITRATE_RF_50 0x00100000 307 #define T55x7_BITRATE_RF_64 0x00140000 308 #define T55x7_BITRATE_RF_100 0x00180000 309 #define T55x7_BITRATE_RF_128 0x001C0000 311 /* T5555 (Q5) configuration register definitions */ 312 #define T5555_ST_TERMINATOR 0x00000001 313 #define T5555_MAXBLOCK_SHIFT 0x00000001 314 #define T5555_MODULATION_MANCHESTER 0 315 #define T5555_MODULATION_PSK1 0x00000010 316 #define T5555_MODULATION_PSK2 0x00000020 317 #define T5555_MODULATION_PSK3 0x00000030 318 #define T5555_MODULATION_FSK1 0x00000040 319 #define T5555_MODULATION_FSK2 0x00000050 320 #define T5555_MODULATION_BIPHASE 0x00000060 321 #define T5555_MODULATION_DIRECT 0x00000070 322 #define T5555_INVERT_OUTPUT 0x00000080 323 #define T5555_PSK_RF_2 0 324 #define T5555_PSK_RF_4 0x00000100 325 #define T5555_PSK_RF_8 0x00000200 326 #define T5555_USE_PWD 0x00000400 327 #define T5555_USE_AOR 0x00000800 328 #define T5555_SET_BITRATE(x) (((x-2)/2)<<12) 329 #define T5555_GET_BITRATE(x) ((((x >> 12) & 0x3F)*2)+2) 330 #define T5555_BITRATE_SHIFT 12 //(RF=2n+2) ie 64=2*0x1F+2 or n = (RF-2)/2 331 #define T5555_FAST_WRITE 0x00004000 332 #define T5555_PAGE_SELECT 0x00008000 334 #define T55XX_WRITE_TIMEOUT 1500 336 uint32_t GetT55xxClockBit ( uint32_t clock
); 338 // em4x05 & em4x69 chip configuration register definitions 339 #define EM4x05_GET_BITRATE(x) (((x & 0x3F)*2)+2) 340 #define EM4x05_SET_BITRATE(x) ((x-2)/2) 341 #define EM4x05_MODULATION_NRZ 0x00000000 342 #define EM4x05_MODULATION_MANCHESTER 0x00000040 343 #define EM4x05_MODULATION_BIPHASE 0x00000080 344 #define EM4x05_MODULATION_MILLER 0x000000C0 //not supported by all 4x05/4x69 chips 345 #define EM4x05_MODULATION_PSK1 0x00000100 //not supported by all 4x05/4x69 chips 346 #define EM4x05_MODULATION_PSK2 0x00000140 //not supported by all 4x05/4x69 chips 347 #define EM4x05_MODULATION_PSK3 0x00000180 //not supported by all 4x05/4x69 chips 348 #define EM4x05_MODULATION_FSK1 0x00000200 //not supported by all 4x05/4x69 chips 349 #define EM4x05_MODULATION_FSK2 0x00000240 //not supported by all 4x05/4x69 chips 350 #define EM4x05_PSK_RF_2 0 351 #define EM4x05_PSK_RF_4 0x00000400 352 #define EM4x05_PSK_RF_8 0x00000800 353 #define EM4x05_MAXBLOCK_SHIFT 14 354 #define EM4x05_FIRST_USER_BLOCK 5 355 #define EM4x05_SET_NUM_BLOCKS(x) ((x+5-1)<<14) //# of blocks sent during default read mode 356 #define EM4x05_GET_NUM_BLOCKS(x) (((x>>14) & 0xF)-5+1) 357 #define EM4x05_READ_LOGIN_REQ 1<<18 358 #define EM4x05_READ_HK_LOGIN_REQ 1<<19 359 #define EM4x05_WRITE_LOGIN_REQ 1<<20 360 #define EM4x05_WRITE_HK_LOGIN_REQ 1<<21 361 #define EM4x05_READ_AFTER_WRITE 1<<22 362 #define EM4x05_DISABLE_ALLOWED 1<<23 363 #define EM4x05_READER_TALK_FIRST 1<<24
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