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1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 // piwi 2018
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // Routines to support ISO 14443B. This includes both the reader software and
10 // the `fake tag' modes.
11 //-----------------------------------------------------------------------------
12
13 #include "iso14443b.h"
14
15 #include "proxmark3.h"
16 #include "apps.h"
17 #include "util.h"
18 #include "string.h"
19 #include "iso14443crc.h"
20 #include "fpgaloader.h"
21
22 #define RECEIVE_SAMPLES_TIMEOUT 1000 // TR0 max is 256/fs = 256/(848kHz) = 302us or 64 samples from FPGA. 1000 seems to be much too high?
23 #define ISO14443B_DMA_BUFFER_SIZE 128
24
25 // PCB Block number for APDUs
26 static uint8_t pcb_blocknum = 0;
27
28 //=============================================================================
29 // An ISO 14443 Type B tag. We listen for commands from the reader, using
30 // a UART kind of thing that's implemented in software. When we get a
31 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
32 // If it's good, then we can do something appropriate with it, and send
33 // a response.
34 //=============================================================================
35
36 //-----------------------------------------------------------------------------
37 // Code up a string of octets at layer 2 (including CRC, we don't generate
38 // that here) so that they can be transmitted to the reader. Doesn't transmit
39 // them yet, just leaves them ready to send in ToSend[].
40 //-----------------------------------------------------------------------------
41 static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
42 {
43 int i;
44
45 ToSendReset();
46
47 // Transmit a burst of ones, as the initial thing that lets the
48 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
49 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
50 // so I will too.
51 for(i = 0; i < 20; i++) {
52 ToSendStuffBit(1);
53 ToSendStuffBit(1);
54 ToSendStuffBit(1);
55 ToSendStuffBit(1);
56 }
57
58 // Send SOF.
59 for(i = 0; i < 10; i++) {
60 ToSendStuffBit(0);
61 ToSendStuffBit(0);
62 ToSendStuffBit(0);
63 ToSendStuffBit(0);
64 }
65 for(i = 0; i < 2; i++) {
66 ToSendStuffBit(1);
67 ToSendStuffBit(1);
68 ToSendStuffBit(1);
69 ToSendStuffBit(1);
70 }
71
72 for(i = 0; i < len; i++) {
73 int j;
74 uint8_t b = cmd[i];
75
76 // Start bit
77 ToSendStuffBit(0);
78 ToSendStuffBit(0);
79 ToSendStuffBit(0);
80 ToSendStuffBit(0);
81
82 // Data bits
83 for(j = 0; j < 8; j++) {
84 if(b & 1) {
85 ToSendStuffBit(1);
86 ToSendStuffBit(1);
87 ToSendStuffBit(1);
88 ToSendStuffBit(1);
89 } else {
90 ToSendStuffBit(0);
91 ToSendStuffBit(0);
92 ToSendStuffBit(0);
93 ToSendStuffBit(0);
94 }
95 b >>= 1;
96 }
97
98 // Stop bit
99 ToSendStuffBit(1);
100 ToSendStuffBit(1);
101 ToSendStuffBit(1);
102 ToSendStuffBit(1);
103 }
104
105 // Send EOF.
106 for(i = 0; i < 10; i++) {
107 ToSendStuffBit(0);
108 ToSendStuffBit(0);
109 ToSendStuffBit(0);
110 ToSendStuffBit(0);
111 }
112 for(i = 0; i < 2; i++) {
113 ToSendStuffBit(1);
114 ToSendStuffBit(1);
115 ToSendStuffBit(1);
116 ToSendStuffBit(1);
117 }
118
119 // Convert from last byte pos to length
120 ToSendMax++;
121 }
122
123 //-----------------------------------------------------------------------------
124 // The software UART that receives commands from the reader, and its state
125 // variables.
126 //-----------------------------------------------------------------------------
127 static struct {
128 enum {
129 STATE_UNSYNCD,
130 STATE_GOT_FALLING_EDGE_OF_SOF,
131 STATE_AWAITING_START_BIT,
132 STATE_RECEIVING_DATA
133 } state;
134 uint16_t shiftReg;
135 int bitCnt;
136 int byteCnt;
137 int byteCntMax;
138 int posCnt;
139 uint8_t *output;
140 } Uart;
141
142 /* Receive & handle a bit coming from the reader.
143 *
144 * This function is called 4 times per bit (every 2 subcarrier cycles).
145 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
146 *
147 * LED handling:
148 * LED A -> ON once we have received the SOF and are expecting the rest.
149 * LED A -> OFF once we have received EOF or are in error state or unsynced
150 *
151 * Returns: true if we received a EOF
152 * false if we are still waiting for some more
153 */
154 static RAMFUNC int Handle14443bUartBit(uint8_t bit)
155 {
156 switch(Uart.state) {
157 case STATE_UNSYNCD:
158 if(!bit) {
159 // we went low, so this could be the beginning
160 // of an SOF
161 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
162 Uart.posCnt = 0;
163 Uart.bitCnt = 0;
164 }
165 break;
166
167 case STATE_GOT_FALLING_EDGE_OF_SOF:
168 Uart.posCnt++;
169 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
170 if(bit) {
171 if(Uart.bitCnt > 9) {
172 // we've seen enough consecutive
173 // zeros that it's a valid SOF
174 Uart.posCnt = 0;
175 Uart.byteCnt = 0;
176 Uart.state = STATE_AWAITING_START_BIT;
177 LED_A_ON(); // Indicate we got a valid SOF
178 } else {
179 // didn't stay down long enough
180 // before going high, error
181 Uart.state = STATE_UNSYNCD;
182 }
183 } else {
184 // do nothing, keep waiting
185 }
186 Uart.bitCnt++;
187 }
188 if(Uart.posCnt >= 4) Uart.posCnt = 0;
189 if(Uart.bitCnt > 12) {
190 // Give up if we see too many zeros without
191 // a one, too.
192 LED_A_OFF();
193 Uart.state = STATE_UNSYNCD;
194 }
195 break;
196
197 case STATE_AWAITING_START_BIT:
198 Uart.posCnt++;
199 if(bit) {
200 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
201 // stayed high for too long between
202 // characters, error
203 Uart.state = STATE_UNSYNCD;
204 }
205 } else {
206 // falling edge, this starts the data byte
207 Uart.posCnt = 0;
208 Uart.bitCnt = 0;
209 Uart.shiftReg = 0;
210 Uart.state = STATE_RECEIVING_DATA;
211 }
212 break;
213
214 case STATE_RECEIVING_DATA:
215 Uart.posCnt++;
216 if(Uart.posCnt == 2) {
217 // time to sample a bit
218 Uart.shiftReg >>= 1;
219 if(bit) {
220 Uart.shiftReg |= 0x200;
221 }
222 Uart.bitCnt++;
223 }
224 if(Uart.posCnt >= 4) {
225 Uart.posCnt = 0;
226 }
227 if(Uart.bitCnt == 10) {
228 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
229 {
230 // this is a data byte, with correct
231 // start and stop bits
232 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
233 Uart.byteCnt++;
234
235 if(Uart.byteCnt >= Uart.byteCntMax) {
236 // Buffer overflowed, give up
237 LED_A_OFF();
238 Uart.state = STATE_UNSYNCD;
239 } else {
240 // so get the next byte now
241 Uart.posCnt = 0;
242 Uart.state = STATE_AWAITING_START_BIT;
243 }
244 } else if (Uart.shiftReg == 0x000) {
245 // this is an EOF byte
246 LED_A_OFF(); // Finished receiving
247 Uart.state = STATE_UNSYNCD;
248 if (Uart.byteCnt != 0) {
249 return true;
250 }
251 } else {
252 // this is an error
253 LED_A_OFF();
254 Uart.state = STATE_UNSYNCD;
255 }
256 }
257 break;
258
259 default:
260 LED_A_OFF();
261 Uart.state = STATE_UNSYNCD;
262 break;
263 }
264
265 return false;
266 }
267
268
269 static void UartReset()
270 {
271 Uart.byteCntMax = MAX_FRAME_SIZE;
272 Uart.state = STATE_UNSYNCD;
273 Uart.byteCnt = 0;
274 Uart.bitCnt = 0;
275 }
276
277
278 static void UartInit(uint8_t *data)
279 {
280 Uart.output = data;
281 UartReset();
282 }
283
284
285 //-----------------------------------------------------------------------------
286 // Receive a command (from the reader to us, where we are the simulated tag),
287 // and store it in the given buffer, up to the given maximum length. Keeps
288 // spinning, waiting for a well-framed command, until either we get one
289 // (returns true) or someone presses the pushbutton on the board (false).
290 //
291 // Assume that we're called with the SSC (to the FPGA) and ADC path set
292 // correctly.
293 //-----------------------------------------------------------------------------
294 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
295 {
296 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
297 // only, since we are receiving, not transmitting).
298 // Signal field is off with the appropriate LED
299 LED_D_OFF();
300 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
301
302 // Now run a `software UART' on the stream of incoming samples.
303 UartInit(received);
304
305 for(;;) {
306 WDT_HIT();
307
308 if(BUTTON_PRESS()) return false;
309
310 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
311 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
312 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
313 if(Handle14443bUartBit(b & mask)) {
314 *len = Uart.byteCnt;
315 return true;
316 }
317 }
318 }
319 }
320
321 return false;
322 }
323
324 //-----------------------------------------------------------------------------
325 // Main loop of simulated tag: receive commands from reader, decide what
326 // response to send, and send it.
327 //-----------------------------------------------------------------------------
328 void SimulateIso14443bTag(void)
329 {
330 LED_A_ON();
331 // the only commands we understand is WUPB, AFI=0, Select All, N=1:
332 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 }; // WUPB
333 // ... and REQB, AFI=0, Normal Request, N=1:
334 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF }; // REQB
335 // ... and HLTB
336 static const uint8_t cmd3[] = { 0x50, 0xff, 0xff, 0xff, 0xff }; // HLTB
337 // ... and ATTRIB
338 static const uint8_t cmd4[] = { 0x1D, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
339
340 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
341 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
342 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
343 static const uint8_t response1[] = {
344 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
345 0x00, 0x21, 0x85, 0x5e, 0xd7
346 };
347 // response to HLTB and ATTRIB
348 static const uint8_t response2[] = {0x00, 0x78, 0xF0};
349
350
351 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
352
353 clear_trace();
354 set_tracing(true);
355
356 const uint8_t *resp;
357 uint8_t *respCode;
358 uint16_t respLen, respCodeLen;
359
360 // allocate command receive buffer
361 BigBuf_free();
362 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
363
364 uint16_t len;
365 uint16_t cmdsRecvd = 0;
366
367 // prepare the (only one) tag answer:
368 CodeIso14443bAsTag(response1, sizeof(response1));
369 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
370 memcpy(resp1Code, ToSend, ToSendMax);
371 uint16_t resp1CodeLen = ToSendMax;
372
373 // prepare the (other) tag answer:
374 CodeIso14443bAsTag(response2, sizeof(response2));
375 uint8_t *resp2Code = BigBuf_malloc(ToSendMax);
376 memcpy(resp2Code, ToSend, ToSendMax);
377 uint16_t resp2CodeLen = ToSendMax;
378
379 // We need to listen to the high-frequency, peak-detected path.
380 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
381 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
382
383 cmdsRecvd = 0;
384
385 for(;;) {
386
387 if(!GetIso14443bCommandFromReader(receivedCmd, &len)) {
388 Dbprintf("button pressed, received %d commands", cmdsRecvd);
389 break;
390 }
391
392 LogTrace(receivedCmd, len, 0, 0, NULL, true);
393
394 // Good, look at the command now.
395 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
396 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
397 resp = response1;
398 respLen = sizeof(response1);
399 respCode = resp1Code;
400 respCodeLen = resp1CodeLen;
401 } else if ( (len == sizeof(cmd3) && receivedCmd[0] == cmd3[0])
402 || (len == sizeof(cmd4) && receivedCmd[0] == cmd4[0]) ) {
403 resp = response2;
404 respLen = sizeof(response2);
405 respCode = resp2Code;
406 respCodeLen = resp2CodeLen;
407 } else {
408 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
409 // And print whether the CRC fails, just for good measure
410 uint8_t b1, b2;
411 if (len >= 3){ // if crc exists
412 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
413 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
414 // Not so good, try again.
415 DbpString("+++CRC fail");
416
417 } else {
418 DbpString("CRC passes");
419 }
420 }
421 //get rid of compiler warning
422 respCodeLen = 0;
423 resp = response1;
424 respLen = 0;
425 respCode = resp1Code;
426 //don't crash at new command just wait and see if reader will send other new cmds.
427 //break;
428 }
429
430 cmdsRecvd++;
431
432 if(cmdsRecvd > 0x30) {
433 DbpString("many commands later...");
434 break;
435 }
436
437 if(respCodeLen <= 0) continue;
438
439 // Modulate BPSK
440 // Signal field is off with the appropriate LED
441 LED_D_OFF();
442 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
443 AT91C_BASE_SSC->SSC_THR = 0xff;
444 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
445
446 // Transmit the response.
447 uint16_t i = 0;
448 for(;;) {
449 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
450 uint8_t b = respCode[i];
451
452 AT91C_BASE_SSC->SSC_THR = b;
453
454 i++;
455 if(i > respCodeLen) {
456 break;
457 }
458 }
459 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
460 volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
461 (void)b;
462 }
463 }
464
465 // trace the response:
466 LogTrace(resp, respLen, 0, 0, NULL, false);
467
468 }
469
470 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
471 LED_A_OFF();
472 }
473
474 //=============================================================================
475 // An ISO 14443 Type B reader. We take layer two commands, code them
476 // appropriately, and then send them to the tag. We then listen for the
477 // tag's response, which we leave in the buffer to be demodulated on the
478 // PC side.
479 //=============================================================================
480
481 static struct {
482 enum {
483 DEMOD_UNSYNCD,
484 DEMOD_PHASE_REF_TRAINING,
485 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
486 DEMOD_GOT_FALLING_EDGE_OF_SOF,
487 DEMOD_AWAITING_START_BIT,
488 DEMOD_RECEIVING_DATA
489 } state;
490 int bitCount;
491 int posCount;
492 int thisBit;
493 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
494 int metric;
495 int metricN;
496 */
497 uint16_t shiftReg;
498 uint8_t *output;
499 int len;
500 int sumI;
501 int sumQ;
502 } Demod;
503
504 /*
505 * Handles reception of a bit from the tag
506 *
507 * This function is called 2 times per bit (every 4 subcarrier cycles).
508 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
509 *
510 * LED handling:
511 * LED C -> ON once we have received the SOF and are expecting the rest.
512 * LED C -> OFF once we have received EOF or are unsynced
513 *
514 * Returns: true if we received a EOF
515 * false if we are still waiting for some more
516 *
517 */
518 static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
519 {
520 int v;
521
522 // The soft decision on the bit uses an estimate of just the
523 // quadrant of the reference angle, not the exact angle.
524 #define MAKE_SOFT_DECISION() { \
525 if(Demod.sumI > 0) { \
526 v = ci; \
527 } else { \
528 v = -ci; \
529 } \
530 if(Demod.sumQ > 0) { \
531 v += cq; \
532 } else { \
533 v -= cq; \
534 } \
535 }
536
537 #define SUBCARRIER_DETECT_THRESHOLD 8
538
539 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
540 #define AMPLITUDE(ci,cq) (MAX(ABS(ci),ABS(cq)) + (MIN(ABS(ci),ABS(cq))/2))
541 switch(Demod.state) {
542 case DEMOD_UNSYNCD:
543 if(AMPLITUDE(ci,cq) > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
544 Demod.state = DEMOD_PHASE_REF_TRAINING;
545 Demod.sumI = ci;
546 Demod.sumQ = cq;
547 Demod.posCount = 1;
548 }
549 break;
550
551 case DEMOD_PHASE_REF_TRAINING:
552 if(Demod.posCount < 8) {
553 if (AMPLITUDE(ci,cq) > SUBCARRIER_DETECT_THRESHOLD) {
554 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
555 // note: synchronization time > 80 1/fs
556 Demod.sumI += ci;
557 Demod.sumQ += cq;
558 Demod.posCount++;
559 } else { // subcarrier lost
560 Demod.state = DEMOD_UNSYNCD;
561 }
562 } else {
563 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
564 }
565 break;
566
567 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
568 MAKE_SOFT_DECISION();
569 if(v < 0) { // logic '0' detected
570 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
571 Demod.posCount = 0; // start of SOF sequence
572 } else {
573 if(Demod.posCount > 200/4) { // maximum length of TR1 = 200 1/fs
574 Demod.state = DEMOD_UNSYNCD;
575 }
576 }
577 Demod.posCount++;
578 break;
579
580 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
581 Demod.posCount++;
582 MAKE_SOFT_DECISION();
583 if(v > 0) {
584 if(Demod.posCount < 9*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
585 Demod.state = DEMOD_UNSYNCD;
586 } else {
587 LED_C_ON(); // Got SOF
588 Demod.state = DEMOD_AWAITING_START_BIT;
589 Demod.posCount = 0;
590 Demod.len = 0;
591 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
592 Demod.metricN = 0;
593 Demod.metric = 0;
594 */
595 }
596 } else {
597 if(Demod.posCount > 12*2) { // low phase of SOF too long (> 12 etu)
598 Demod.state = DEMOD_UNSYNCD;
599 LED_C_OFF();
600 }
601 }
602 break;
603
604 case DEMOD_AWAITING_START_BIT:
605 Demod.posCount++;
606 MAKE_SOFT_DECISION();
607 if(v > 0) {
608 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
609 Demod.state = DEMOD_UNSYNCD;
610 LED_C_OFF();
611 }
612 } else { // start bit detected
613 Demod.bitCount = 0;
614 Demod.posCount = 1; // this was the first half
615 Demod.thisBit = v;
616 Demod.shiftReg = 0;
617 Demod.state = DEMOD_RECEIVING_DATA;
618 }
619 break;
620
621 case DEMOD_RECEIVING_DATA:
622 MAKE_SOFT_DECISION();
623 if(Demod.posCount == 0) { // first half of bit
624 Demod.thisBit = v;
625 Demod.posCount = 1;
626 } else { // second half of bit
627 Demod.thisBit += v;
628
629 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
630 if(Demod.thisBit > 0) {
631 Demod.metric += Demod.thisBit;
632 } else {
633 Demod.metric -= Demod.thisBit;
634 }
635 (Demod.metricN)++;
636 */
637
638 Demod.shiftReg >>= 1;
639 if(Demod.thisBit > 0) { // logic '1'
640 Demod.shiftReg |= 0x200;
641 }
642
643 Demod.bitCount++;
644 if(Demod.bitCount == 10) {
645 uint16_t s = Demod.shiftReg;
646 if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
647 uint8_t b = (s >> 1);
648 Demod.output[Demod.len] = b;
649 Demod.len++;
650 Demod.state = DEMOD_AWAITING_START_BIT;
651 } else {
652 Demod.state = DEMOD_UNSYNCD;
653 LED_C_OFF();
654 if(s == 0x000) {
655 // This is EOF (start, stop and all data bits == '0'
656 return true;
657 }
658 }
659 }
660 Demod.posCount = 0;
661 }
662 break;
663
664 default:
665 Demod.state = DEMOD_UNSYNCD;
666 LED_C_OFF();
667 break;
668 }
669
670 return false;
671 }
672
673
674 static void DemodReset()
675 {
676 // Clear out the state of the "UART" that receives from the tag.
677 Demod.len = 0;
678 Demod.state = DEMOD_UNSYNCD;
679 Demod.posCount = 0;
680 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
681 }
682
683
684 static void DemodInit(uint8_t *data)
685 {
686 Demod.output = data;
687 DemodReset();
688 }
689
690
691 /*
692 * Demodulate the samples we received from the tag, also log to tracebuffer
693 * quiet: set to 'true' to disable debug output
694 */
695 static void GetSamplesFor14443bDemod(int n, bool quiet)
696 {
697 int maxBehindBy = 0;
698 bool gotFrame = false;
699 int lastRxCounter, samples = 0;
700 int8_t ci, cq;
701
702 // Allocate memory from BigBuf for some buffers
703 // free all previous allocations first
704 BigBuf_free();
705
706 // The response (tag -> reader) that we're receiving.
707 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
708
709 // The DMA buffer, used to stream samples from the FPGA
710 uint16_t *dmaBuf = (uint16_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE * sizeof(uint16_t));
711
712 // Set up the demodulator for tag -> reader responses.
713 DemodInit(receivedResponse);
714
715 // wait for last transfer to complete
716 while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXEMPTY))
717
718 // Setup and start DMA.
719 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
720 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
721
722 uint16_t *upTo = dmaBuf;
723 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
724
725 // Signal field is ON with the appropriate LED:
726 LED_D_ON();
727 // And put the FPGA in the appropriate mode
728 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
729
730 for(;;) {
731 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1);
732 if(behindBy > maxBehindBy) {
733 maxBehindBy = behindBy;
734 }
735
736 if(behindBy < 1) continue;
737
738 ci = *upTo >> 8;
739 cq = *upTo;
740 upTo++;
741 lastRxCounter--;
742 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) { // we have read all of the DMA buffer content.
743 upTo = dmaBuf; // start reading the circular buffer from the beginning
744 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
745 }
746 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX)) { // DMA Counter Register had reached 0, already rotated.
747 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; // refresh the DMA Next Buffer and
748 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE; // DMA Next Counter registers
749 }
750 samples++;
751
752 if(Handle14443bSamplesDemod(ci, cq)) {
753 gotFrame = true;
754 break;
755 }
756
757 if(samples > n) {
758 break;
759 }
760 }
761
762 FpgaDisableSscDma();
763
764 if (!quiet) Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", maxBehindBy, samples, gotFrame, Demod.len, Demod.sumI, Demod.sumQ);
765 //Tracing
766 if (Demod.len > 0) {
767 LogTrace(Demod.output, Demod.len, 0, 0, NULL, false);
768 }
769 }
770
771
772 //-----------------------------------------------------------------------------
773 // Transmit the command (to the tag) that was placed in ToSend[].
774 //-----------------------------------------------------------------------------
775 static void TransmitFor14443b(void)
776 {
777 int c;
778
779 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
780
781 // Signal field is ON with the appropriate Red LED
782 LED_D_ON();
783 // Signal we are transmitting with the Green LED
784 LED_B_ON();
785 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
786
787 c = 0;
788 for(;;) {
789 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
790 AT91C_BASE_SSC->SSC_THR = ~ToSend[c];
791 c++;
792 if(c >= ToSendMax) {
793 break;
794 }
795 }
796 WDT_HIT();
797 }
798 LED_B_OFF(); // Finished sending
799 }
800
801
802 //-----------------------------------------------------------------------------
803 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
804 // so that it is ready to transmit to the tag using TransmitFor14443b().
805 //-----------------------------------------------------------------------------
806 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
807 {
808 int i, j;
809 uint8_t b;
810
811 ToSendReset();
812
813 // Send SOF
814 for(i = 0; i < 10; i++) {
815 ToSendStuffBit(0);
816 }
817 ToSendStuffBit(1);
818 ToSendStuffBit(1);
819
820 for(i = 0; i < len; i++) {
821 // Start bit
822 ToSendStuffBit(0);
823 // Data bits
824 b = cmd[i];
825 for(j = 0; j < 8; j++) {
826 if(b & 1) {
827 ToSendStuffBit(1);
828 } else {
829 ToSendStuffBit(0);
830 }
831 b >>= 1;
832 }
833 // Stop bit
834 ToSendStuffBit(1);
835 }
836
837 // Send EOF
838 for(i = 0; i < 10; i++) {
839 ToSendStuffBit(0);
840 }
841 ToSendStuffBit(1);
842
843 // ensure that last byte is filled up
844 for(i = 0; i < 8; i++) {
845 ToSendStuffBit(1);
846 }
847
848 // Convert from last character reference to length
849 ToSendMax++;
850 }
851
852
853 /**
854 Convenience function to encode, transmit and trace iso 14443b comms
855 **/
856 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
857 {
858 CodeIso14443bAsReader(cmd, len);
859 TransmitFor14443b();
860 LogTrace(cmd,len, 0, 0, NULL, true);
861 }
862
863 /* Sends an APDU to the tag
864 * TODO: check CRC and preamble
865 */
866 int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
867 {
868 LED_A_ON();
869 uint8_t message_frame[message_length + 4];
870 // PCB
871 message_frame[0] = 0x0A | pcb_blocknum;
872 pcb_blocknum ^= 1;
873 // CID
874 message_frame[1] = 0;
875 // INF
876 memcpy(message_frame + 2, message, message_length);
877 // EDC (CRC)
878 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
879 // send
880 CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
881 // get response
882 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
883 FpgaDisableTracing();
884 if(Demod.len < 3)
885 {
886 LED_A_OFF();
887 return 0;
888 }
889 // TODO: Check CRC
890 // copy response contents
891 if(response != NULL)
892 {
893 memcpy(response, Demod.output, Demod.len);
894 }
895 LED_A_OFF();
896 return Demod.len;
897 }
898
899 /* Perform the ISO 14443 B Card Selection procedure
900 * Currently does NOT do any collision handling.
901 * It expects 0-1 cards in the device's range.
902 * TODO: Support multiple cards (perform anticollision)
903 * TODO: Verify CRC checksums
904 */
905 int iso14443b_select_card()
906 {
907 // WUPB command (including CRC)
908 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
909 static const uint8_t wupb[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
910 // ATTRIB command (with space for CRC)
911 uint8_t attrib[] = { 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
912
913 // first, wake up the tag
914 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
915 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
916 // ATQB too short?
917 if (Demod.len < 14)
918 {
919 return 2;
920 }
921
922 // select the tag
923 // copy the PUPI to ATTRIB
924 memcpy(attrib + 1, Demod.output + 1, 4);
925 /* copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into
926 ATTRIB (Param 3) */
927 attrib[7] = Demod.output[10] & 0x0F;
928 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
929 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
930 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
931 // Answer to ATTRIB too short?
932 if(Demod.len < 3)
933 {
934 return 2;
935 }
936 // reset PCB block number
937 pcb_blocknum = 0;
938 return 1;
939 }
940
941 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
942 void iso14443b_setup() {
943 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
944 // Set up the synchronous serial port
945 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
946 // connect Demodulated Signal to ADC:
947 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
948
949 // Signal field is on with the appropriate LED
950 LED_D_ON();
951 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
952
953 DemodReset();
954 UartReset();
955 }
956
957 //-----------------------------------------------------------------------------
958 // Read a SRI512 ISO 14443B tag.
959 //
960 // SRI512 tags are just simple memory tags, here we're looking at making a dump
961 // of the contents of the memory. No anticollision algorithm is done, we assume
962 // we have a single tag in the field.
963 //
964 // I tried to be systematic and check every answer of the tag, every CRC, etc...
965 //-----------------------------------------------------------------------------
966 void ReadSTMemoryIso14443b(uint32_t dwLast)
967 {
968 LED_A_ON();
969 uint8_t i = 0x00;
970
971 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
972 // Make sure that we start from off, since the tags are stateful;
973 // confusing things will happen if we don't reset them between reads.
974 LED_D_OFF();
975 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
976 SpinDelay(200);
977
978 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
979 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
980
981 // Now give it time to spin up.
982 // Signal field is on with the appropriate LED
983 LED_D_ON();
984 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
985 SpinDelay(200);
986
987 clear_trace();
988 set_tracing(true);
989
990 // First command: wake up the tag using the INITIATE command
991 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
992 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
993 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
994
995 if (Demod.len == 0) {
996 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
997 DbpString("No response from tag");
998 LEDsoff();
999 return;
1000 } else {
1001 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
1002 Demod.output[0], Demod.output[1], Demod.output[2]);
1003 }
1004
1005 // There is a response, SELECT the uid
1006 DbpString("Now SELECT tag:");
1007 cmd1[0] = 0x0E; // 0x0E is SELECT
1008 cmd1[1] = Demod.output[0];
1009 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1010 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1011 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1012 if (Demod.len != 3) {
1013 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1014 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1015 LEDsoff();
1016 return;
1017 }
1018 // Check the CRC of the answer:
1019 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1020 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1021 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1022 DbpString("CRC Error reading select response.");
1023 LEDsoff();
1024 return;
1025 }
1026 // Check response from the tag: should be the same UID as the command we just sent:
1027 if (cmd1[1] != Demod.output[0]) {
1028 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1029 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1030 LEDsoff();
1031 return;
1032 }
1033
1034 // Tag is now selected,
1035 // First get the tag's UID:
1036 cmd1[0] = 0x0B;
1037 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1038 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
1039 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1040 if (Demod.len != 10) {
1041 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1042 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1043 LEDsoff();
1044 return;
1045 }
1046 // The check the CRC of the answer (use cmd1 as temporary variable):
1047 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1048 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1049 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1050 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1051 // Do not return;, let's go on... (we should retry, maybe ?)
1052 }
1053 Dbprintf("Tag UID (64 bits): %08x %08x",
1054 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1055 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1056
1057 // Now loop to read all 16 blocks, address from 0 to last block
1058 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
1059 cmd1[0] = 0x08;
1060 i = 0x00;
1061 dwLast++;
1062 for (;;) {
1063 if (i == dwLast) {
1064 DbpString("System area block (0xff):");
1065 i = 0xff;
1066 }
1067 cmd1[1] = i;
1068 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1069 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1070 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1071 if (Demod.len != 6) { // Check if we got an answer from the tag
1072 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1073 DbpString("Expected 6 bytes from tag, got less...");
1074 LEDsoff();
1075 return;
1076 }
1077 // The check the CRC of the answer (use cmd1 as temporary variable):
1078 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1079 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1080 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1081 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1082 // Do not return;, let's go on... (we should retry, maybe ?)
1083 }
1084 // Now print out the memory location:
1085 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1086 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1087 (Demod.output[4]<<8)+Demod.output[5]);
1088 if (i == 0xff) {
1089 break;
1090 }
1091 i++;
1092 }
1093
1094 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1095 LEDsoff();
1096 }
1097
1098
1099 //=============================================================================
1100 // Finally, the `sniffer' combines elements from both the reader and
1101 // simulated tag, to show both sides of the conversation.
1102 //=============================================================================
1103
1104 //-----------------------------------------------------------------------------
1105 // Record the sequence of commands sent by the reader to the tag, with
1106 // triggering so that we start recording at the point that the tag is moved
1107 // near the reader.
1108 //-----------------------------------------------------------------------------
1109 /*
1110 * Memory usage for this function, (within BigBuf)
1111 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1112 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1113 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1114 * Demodulated samples received - all the rest
1115 */
1116 void RAMFUNC SnoopIso14443b(void)
1117 {
1118 LED_A_ON();
1119 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1120 BigBuf_free();
1121
1122 clear_trace();
1123 set_tracing(true);
1124
1125 // The DMA buffer, used to stream samples from the FPGA
1126 uint16_t *dmaBuf = (uint16_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE * sizeof(uint16_t));
1127 int lastRxCounter;
1128 uint16_t *upTo;
1129 int8_t ci, cq;
1130 int maxBehindBy = 0;
1131
1132 // Count of samples received so far, so that we can include timing
1133 // information in the trace buffer.
1134 int samples = 0;
1135
1136 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1137 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1138
1139 // Print some debug information about the buffer sizes
1140 Dbprintf("Snooping buffers initialized:");
1141 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1142 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1143 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1144 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1145
1146 // Signal field is off, no reader signal, no tag signal
1147 LEDsoff();
1148
1149 // And put the FPGA in the appropriate mode
1150 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1151 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1152
1153 // Setup for the DMA.
1154 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
1155 upTo = dmaBuf;
1156 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1157 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
1158
1159 bool TagIsActive = false;
1160 bool ReaderIsActive = false;
1161 // We won't start recording the frames that we acquire until we trigger.
1162 // A good trigger condition to get started is probably when we see a
1163 // reader command
1164 bool triggered = false;
1165
1166 // And now we loop, receiving samples.
1167 for(;;) {
1168 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1);
1169 if(behindBy > maxBehindBy) {
1170 maxBehindBy = behindBy;
1171 }
1172
1173 if(behindBy < 1) continue;
1174
1175 ci = *upTo>>8;
1176 cq = *upTo;
1177 upTo++;
1178 lastRxCounter--;
1179 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) { // we have read all of the DMA buffer content.
1180 upTo = dmaBuf; // start reading the circular buffer from the beginning again
1181 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
1182 if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) {
1183 Dbprintf("About to blow circular buffer - aborted! behindBy=%d", behindBy);
1184 break;
1185 }
1186 }
1187 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX)) { // DMA Counter Register had reached 0, already rotated.
1188 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; // refresh the DMA Next Buffer and
1189 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE; // DMA Next Counter registers
1190 WDT_HIT();
1191 if(BUTTON_PRESS()) {
1192 DbpString("cancelled");
1193 break;
1194 }
1195 }
1196
1197 samples++;
1198
1199 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
1200 if(Handle14443bUartBit(ci & 0x01)) {
1201 triggered = true;
1202 LogTrace(Uart.output, Uart.byteCnt, samples, samples, NULL, true);
1203 /* And ready to receive another command. */
1204 UartReset();
1205 /* And also reset the demod code, which might have been */
1206 /* false-triggered by the commands from the reader. */
1207 DemodReset();
1208 }
1209 if(Handle14443bUartBit(cq & 0x01)) {
1210 triggered = true;
1211 LogTrace(Uart.output, Uart.byteCnt, samples, samples, NULL, true);
1212 /* And ready to receive another command. */
1213 UartReset();
1214 /* And also reset the demod code, which might have been */
1215 /* false-triggered by the commands from the reader. */
1216 DemodReset();
1217 }
1218 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1219 }
1220
1221 if(!ReaderIsActive && triggered) { // no need to try decoding tag data if the reader is sending or not yet triggered
1222 if(Handle14443bSamplesDemod(ci/2, cq/2)) {
1223 //Use samples as a time measurement
1224 LogTrace(Demod.output, Demod.len, samples, samples, NULL, false);
1225 // And ready to receive another response.
1226 DemodReset();
1227 }
1228 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1229 }
1230
1231 }
1232
1233 FpgaDisableSscDma();
1234 DbpString("Snoop statistics:");
1235 Dbprintf(" Max behind by: %i", maxBehindBy);
1236 Dbprintf(" Uart State: %x", Uart.state);
1237 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1238 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
1239 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1240 LEDsoff();
1241 }
1242
1243
1244 /*
1245 * Send raw command to tag ISO14443B
1246 * @Input
1247 * datalen len of buffer data
1248 * recv bool when true wait for data from tag and send to client
1249 * powerfield bool leave the field on when true
1250 * data buffer with byte to send
1251 *
1252 * @Output
1253 * none
1254 *
1255 */
1256 void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
1257 {
1258 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1259 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1260
1261 // switch field on and give tag some time to power up
1262 LED_D_ON();
1263 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
1264 SpinDelay(10);
1265
1266 if (datalen){
1267 set_tracing(true);
1268
1269 CodeAndTransmit14443bAsReader(data, datalen);
1270
1271 if(recv) {
1272 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1273 FpgaDisableTracing();
1274 uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1275 cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
1276 }
1277
1278 FpgaDisableTracing();
1279 }
1280
1281 if(!powerfield) {
1282 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1283 LED_D_OFF();
1284 }
1285 }
1286
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