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1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to support ISO 14443B. This includes both the reader software and
9 // the `fake tag' modes.
10 //-----------------------------------------------------------------------------
11
12 #include "proxmark3.h"
13 #include "apps.h"
14 #include "util.h"
15 #include "string.h"
16 #include "iso14443crc.h"
17 #include "common.h"
18 #define RECEIVE_SAMPLES_TIMEOUT 20000
19 #define ISO14443B_DMA_BUFFER_SIZE 256
20
21 // PCB Block number for APDUs
22 static uint8_t pcb_blocknum = 0;
23
24 //=============================================================================
25 // An ISO 14443 Type B tag. We listen for commands from the reader, using
26 // a UART kind of thing that's implemented in software. When we get a
27 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
28 // If it's good, then we can do something appropriate with it, and send
29 // a response.
30 //=============================================================================
31
32
33 //-----------------------------------------------------------------------------
34 // The software UART that receives commands from the reader, and its state
35 // variables.
36 //-----------------------------------------------------------------------------
37 static struct {
38 enum {
39 STATE_UNSYNCD,
40 STATE_GOT_FALLING_EDGE_OF_SOF,
41 STATE_AWAITING_START_BIT,
42 STATE_RECEIVING_DATA
43 } state;
44 uint16_t shiftReg;
45 int bitCnt;
46 int byteCnt;
47 int byteCntMax;
48 int posCnt;
49 uint8_t *output;
50 } Uart;
51
52 static void UartReset()
53 {
54 Uart.byteCntMax = MAX_FRAME_SIZE;
55 Uart.state = STATE_UNSYNCD;
56 Uart.byteCnt = 0;
57 Uart.bitCnt = 0;
58 Uart.posCnt = 0;
59 memset(Uart.output, 0x00, MAX_FRAME_SIZE);
60 }
61
62 static void UartInit(uint8_t *data)
63 {
64 Uart.output = data;
65 UartReset();
66 }
67
68
69 static struct {
70 enum {
71 DEMOD_UNSYNCD,
72 DEMOD_PHASE_REF_TRAINING,
73 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
74 DEMOD_GOT_FALLING_EDGE_OF_SOF,
75 DEMOD_AWAITING_START_BIT,
76 DEMOD_RECEIVING_DATA
77 } state;
78 int bitCount;
79 int posCount;
80 int thisBit;
81 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
82 int metric;
83 int metricN;
84 */
85 uint16_t shiftReg;
86 uint8_t *output;
87 int len;
88 int sumI;
89 int sumQ;
90 } Demod;
91
92 static void DemodReset()
93 {
94 // Clear out the state of the "UART" that receives from the tag.
95 Demod.len = 0;
96 Demod.state = DEMOD_UNSYNCD;
97 Demod.posCount = 0;
98 Demod.sumI = 0;
99 Demod.sumQ = 0;
100 Demod.bitCount = 0;
101 Demod.thisBit = 0;
102 Demod.shiftReg = 0;
103 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
104 }
105
106
107 static void DemodInit(uint8_t *data)
108 {
109 Demod.output = data;
110 DemodReset();
111 }
112
113
114 //-----------------------------------------------------------------------------
115 // Code up a string of octets at layer 2 (including CRC, we don't generate
116 // that here) so that they can be transmitted to the reader. Doesn't transmit
117 // them yet, just leaves them ready to send in ToSend[].
118 //-----------------------------------------------------------------------------
119 static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
120 {
121 int i;
122
123 ToSendReset();
124
125 // Transmit a burst of ones, as the initial thing that lets the
126 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
127 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
128 // so I will too.
129 for(i = 0; i < 20; i++) {
130 ToSendStuffBit(1);
131 ToSendStuffBit(1);
132 ToSendStuffBit(1);
133 ToSendStuffBit(1);
134 }
135
136 // Send SOF.
137 for(i = 0; i < 10; i++) {
138 ToSendStuffBit(0);
139 ToSendStuffBit(0);
140 ToSendStuffBit(0);
141 ToSendStuffBit(0);
142 }
143 for(i = 0; i < 2; i++) {
144 ToSendStuffBit(1);
145 ToSendStuffBit(1);
146 ToSendStuffBit(1);
147 ToSendStuffBit(1);
148 }
149
150 for(i = 0; i < len; i++) {
151 int j;
152 uint8_t b = cmd[i];
153
154 // Start bit
155 ToSendStuffBit(0);
156 ToSendStuffBit(0);
157 ToSendStuffBit(0);
158 ToSendStuffBit(0);
159
160 // Data bits
161 for(j = 0; j < 8; j++) {
162 if(b & 1) {
163 ToSendStuffBit(1);
164 ToSendStuffBit(1);
165 ToSendStuffBit(1);
166 ToSendStuffBit(1);
167 } else {
168 ToSendStuffBit(0);
169 ToSendStuffBit(0);
170 ToSendStuffBit(0);
171 ToSendStuffBit(0);
172 }
173 b >>= 1;
174 }
175
176 // Stop bit
177 ToSendStuffBit(1);
178 ToSendStuffBit(1);
179 ToSendStuffBit(1);
180 ToSendStuffBit(1);
181 }
182
183 // Send EOF.
184 for(i = 0; i < 10; i++) {
185 ToSendStuffBit(0);
186 ToSendStuffBit(0);
187 ToSendStuffBit(0);
188 ToSendStuffBit(0);
189 }
190 for(i = 0; i < 2; i++) {
191 ToSendStuffBit(1);
192 ToSendStuffBit(1);
193 ToSendStuffBit(1);
194 ToSendStuffBit(1);
195 }
196
197 // Convert from last byte pos to length
198 ToSendMax++;
199 }
200
201
202
203 /* Receive & handle a bit coming from the reader.
204 *
205 * This function is called 4 times per bit (every 2 subcarrier cycles).
206 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
207 *
208 * LED handling:
209 * LED A -> ON once we have received the SOF and are expecting the rest.
210 * LED A -> OFF once we have received EOF or are in error state or unsynced
211 *
212 * Returns: true if we received a EOF
213 * false if we are still waiting for some more
214 */
215 static RAMFUNC int Handle14443bUartBit(uint8_t bit)
216 {
217 switch(Uart.state) {
218 case STATE_UNSYNCD:
219 if(!bit) {
220 // we went low, so this could be the beginning
221 // of an SOF
222 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
223 Uart.posCnt = 0;
224 Uart.bitCnt = 0;
225 }
226 break;
227
228 case STATE_GOT_FALLING_EDGE_OF_SOF:
229 Uart.posCnt++;
230 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
231 if(bit) {
232 if(Uart.bitCnt > 9) {
233 // we've seen enough consecutive
234 // zeros that it's a valid SOF
235 Uart.posCnt = 0;
236 Uart.byteCnt = 0;
237 Uart.state = STATE_AWAITING_START_BIT;
238 LED_A_ON(); // Indicate we got a valid SOF
239 } else {
240 // didn't stay down long enough
241 // before going high, error
242 Uart.state = STATE_UNSYNCD;
243 }
244 } else {
245 // do nothing, keep waiting
246 }
247 Uart.bitCnt++;
248 }
249 if(Uart.posCnt >= 4) Uart.posCnt = 0;
250 if(Uart.bitCnt > 12) {
251 // Give up if we see too many zeros without
252 // a one, too.
253 LED_A_OFF();
254 Uart.state = STATE_UNSYNCD;
255 }
256 break;
257
258 case STATE_AWAITING_START_BIT:
259 Uart.posCnt++;
260 if(bit) {
261 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
262 // stayed high for too long between
263 // characters, error
264 Uart.state = STATE_UNSYNCD;
265 }
266 } else {
267 // falling edge, this starts the data byte
268 Uart.posCnt = 0;
269 Uart.bitCnt = 0;
270 Uart.shiftReg = 0;
271 Uart.state = STATE_RECEIVING_DATA;
272 }
273 break;
274
275 case STATE_RECEIVING_DATA:
276 Uart.posCnt++;
277 if(Uart.posCnt == 2) {
278 // time to sample a bit
279 Uart.shiftReg >>= 1;
280 if(bit) {
281 Uart.shiftReg |= 0x200;
282 }
283 Uart.bitCnt++;
284 }
285 if(Uart.posCnt >= 4) {
286 Uart.posCnt = 0;
287 }
288 if(Uart.bitCnt == 10) {
289 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
290 {
291 // this is a data byte, with correct
292 // start and stop bits
293 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
294 Uart.byteCnt++;
295
296 if(Uart.byteCnt >= Uart.byteCntMax) {
297 // Buffer overflowed, give up
298 LED_A_OFF();
299 Uart.state = STATE_UNSYNCD;
300 } else {
301 // so get the next byte now
302 Uart.posCnt = 0;
303 Uart.state = STATE_AWAITING_START_BIT;
304 }
305 } else if (Uart.shiftReg == 0x000) {
306 // this is an EOF byte
307 LED_A_OFF(); // Finished receiving
308 Uart.state = STATE_UNSYNCD;
309 if (Uart.byteCnt != 0) {
310 return TRUE;
311 }
312 } else {
313 // this is an error
314 LED_A_OFF();
315 Uart.state = STATE_UNSYNCD;
316 }
317 }
318 break;
319
320 default:
321 LED_A_OFF();
322 Uart.state = STATE_UNSYNCD;
323 break;
324 }
325
326 return FALSE;
327 }
328
329 //-----------------------------------------------------------------------------
330 // Receive a command (from the reader to us, where we are the simulated tag),
331 // and store it in the given buffer, up to the given maximum length. Keeps
332 // spinning, waiting for a well-framed command, until either we get one
333 // (returns TRUE) or someone presses the pushbutton on the board (FALSE).
334 //
335 // Assume that we're called with the SSC (to the FPGA) and ADC path set
336 // correctly.
337 //-----------------------------------------------------------------------------
338 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
339 {
340 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
341 // only, since we are receiving, not transmitting).
342 // Signal field is off with the appropriate LED
343 LED_D_OFF();
344 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
345
346 // Now run a `software UART' on the stream of incoming samples.
347 UartInit(received);
348
349 for(;;) {
350 WDT_HIT();
351
352 if(BUTTON_PRESS()) return FALSE;
353
354 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
355 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
356 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
357 if(Handle14443bUartBit(b & mask)) {
358 *len = Uart.byteCnt;
359 return TRUE;
360 }
361 }
362 }
363 }
364
365 return FALSE;
366 }
367
368 //-----------------------------------------------------------------------------
369 // Main loop of simulated tag: receive commands from reader, decide what
370 // response to send, and send it.
371 //-----------------------------------------------------------------------------
372 void SimulateIso14443bTag(void)
373 {
374 // the only commands we understand is WUPB, AFI=0, Select All, N=1:
375 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 }; // WUPB
376 // ... and REQB, AFI=0, Normal Request, N=1:
377 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF }; // REQB
378 // ... and HLTB
379 static const uint8_t cmd3[] = { 0x50, 0xff, 0xff, 0xff, 0xff }; // HLTB
380 // ... and ATTRIB
381 static const uint8_t cmd4[] = { 0x1D, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
382
383 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
384 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
385 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
386 static const uint8_t response1[] = {
387 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
388 0x00, 0x21, 0x85, 0x5e, 0xd7
389 };
390 // response to HLTB and ATTRIB
391 static const uint8_t response2[] = {0x00, 0x78, 0xF0};
392
393 //uint8_t parity[MAX_PARITY_SIZE] = {0x00};
394
395 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
396
397 clear_trace();
398 set_tracing(TRUE);
399
400 const uint8_t *resp;
401 uint8_t *respCode;
402 uint16_t respLen, respCodeLen;
403
404 // allocate command receive buffer
405 BigBuf_free(); BigBuf_Clear_ext(false);
406
407 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
408
409 uint16_t len;
410 uint16_t cmdsRecvd = 0;
411
412 // prepare the (only one) tag answer:
413 CodeIso14443bAsTag(response1, sizeof(response1));
414 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
415 memcpy(resp1Code, ToSend, ToSendMax);
416 uint16_t resp1CodeLen = ToSendMax;
417
418 // prepare the (other) tag answer:
419 CodeIso14443bAsTag(response2, sizeof(response2));
420 uint8_t *resp2Code = BigBuf_malloc(ToSendMax);
421 memcpy(resp2Code, ToSend, ToSendMax);
422 uint16_t resp2CodeLen = ToSendMax;
423
424 // We need to listen to the high-frequency, peak-detected path.
425 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
426 FpgaSetupSsc();
427
428 cmdsRecvd = 0;
429
430 for(;;) {
431
432 if (!GetIso14443bCommandFromReader(receivedCmd, &len)) {
433 Dbprintf("button pressed, received %d commands", cmdsRecvd);
434 break;
435 }
436
437 if (tracing)
438 //LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
439 LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
440
441
442 // Good, look at the command now.
443 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
444 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
445 resp = response1;
446 respLen = sizeof(response1);
447 respCode = resp1Code;
448 respCodeLen = resp1CodeLen;
449 } else if ( (len == sizeof(cmd3) && receivedCmd[0] == cmd3[0])
450 || (len == sizeof(cmd4) && receivedCmd[0] == cmd4[0]) ) {
451 resp = response2;
452 respLen = sizeof(response2);
453 respCode = resp2Code;
454 respCodeLen = resp2CodeLen;
455 } else {
456 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
457 // And print whether the CRC fails, just for good measure
458 uint8_t b1, b2;
459 if (len >= 3){ // if crc exists
460 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
461 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
462 // Not so good, try again.
463 DbpString("+++CRC fail");
464
465 } else {
466 DbpString("CRC passes");
467 }
468 }
469 //get rid of compiler warning
470 respCodeLen = 0;
471 resp = response1;
472 respLen = 0;
473 respCode = resp1Code;
474 //don't crash at new command just wait and see if reader will send other new cmds.
475 //break;
476 }
477
478 cmdsRecvd++;
479
480 if(cmdsRecvd > 0x30) {
481 DbpString("many commands later...");
482 break;
483 }
484
485 if(respCodeLen <= 0) continue;
486
487 // Modulate BPSK
488 // Signal field is off with the appropriate LED
489 LED_D_OFF();
490 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
491 AT91C_BASE_SSC->SSC_THR = 0xff;
492 FpgaSetupSsc();
493
494 // Transmit the response.
495 uint16_t i = 0;
496 for(;;) {
497 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
498 uint8_t b = respCode[i];
499
500 AT91C_BASE_SSC->SSC_THR = b;
501
502 i++;
503 if(i > respCodeLen) {
504 break;
505 }
506 }
507 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
508 volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
509 (void)b;
510 }
511 }
512
513 // trace the response:
514 if (tracing)
515 //LogTrace(resp, respLen, 0, 0, parity, FALSE);
516 LogTrace(resp, respLen, 0, 0, NULL, FALSE);
517 }
518 }
519
520 //=============================================================================
521 // An ISO 14443 Type B reader. We take layer two commands, code them
522 // appropriately, and then send them to the tag. We then listen for the
523 // tag's response, which we leave in the buffer to be demodulated on the
524 // PC side.
525 //=============================================================================
526
527 /*
528 * Handles reception of a bit from the tag
529 *
530 * This function is called 2 times per bit (every 4 subcarrier cycles).
531 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
532 *
533 * LED handling:
534 * LED C -> ON once we have received the SOF and are expecting the rest.
535 * LED C -> OFF once we have received EOF or are unsynced
536 *
537 * Returns: true if we received a EOF
538 * false if we are still waiting for some more
539 *
540 */
541 #ifndef SUBCARRIER_DETECT_THRESHOLD
542 # define SUBCARRIER_DETECT_THRESHOLD 6
543 #endif
544
545 static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
546 {
547 int v = 0;
548 // The soft decision on the bit uses an estimate of just the
549 // quadrant of the reference angle, not the exact angle.
550 #define MAKE_SOFT_DECISION() { \
551 if(Demod.sumI > 0) { \
552 v = ci; \
553 } else { \
554 v = -ci; \
555 } \
556 if(Demod.sumQ > 0) { \
557 v += cq; \
558 } else { \
559 v -= cq; \
560 } \
561 }
562
563 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
564 /* #define CHECK_FOR_SUBCARRIER() { \
565 v = ci; \
566 if(v < 0) v = -v; \
567 if(cq > 0) { \
568 v += cq; \
569 } else { \
570 v -= cq; \
571 } \
572 }
573 */
574 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
575 #define CHECK_FOR_SUBCARRIER() { \
576 if(ci < 0) { \
577 if(cq < 0) { /* ci < 0, cq < 0 */ \
578 if (cq < ci) { \
579 v = -cq - (ci >> 1); \
580 } else { \
581 v = -ci - (cq >> 1); \
582 } \
583 } else { /* ci < 0, cq >= 0 */ \
584 if (cq < -ci) { \
585 v = -ci + (cq >> 1); \
586 } else { \
587 v = cq - (ci >> 1); \
588 } \
589 } \
590 } else { \
591 if(cq < 0) { /* ci >= 0, cq < 0 */ \
592 if (-cq < ci) { \
593 v = ci - (cq >> 1); \
594 } else { \
595 v = -cq + (ci >> 1); \
596 } \
597 } else { /* ci >= 0, cq >= 0 */ \
598 if (cq < ci) { \
599 v = ci + (cq >> 1); \
600 } else { \
601 v = cq + (ci >> 1); \
602 } \
603 } \
604 } \
605 }
606
607
608 switch(Demod.state) {
609 case DEMOD_UNSYNCD:
610
611 CHECK_FOR_SUBCARRIER();
612
613 // subcarrier detected
614 if(v > SUBCARRIER_DETECT_THRESHOLD) {
615 Demod.state = DEMOD_PHASE_REF_TRAINING;
616 Demod.sumI = ci;
617 Demod.sumQ = cq;
618 Demod.posCount = 1;
619 }
620 break;
621
622 case DEMOD_PHASE_REF_TRAINING:
623 if(Demod.posCount < 8) {
624
625 CHECK_FOR_SUBCARRIER();
626
627 if (v > SUBCARRIER_DETECT_THRESHOLD) {
628 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
629 // note: synchronization time > 80 1/fs
630 Demod.sumI += ci;
631 Demod.sumQ += cq;
632 ++Demod.posCount;
633 } else {
634 // subcarrier lost
635 Demod.state = DEMOD_UNSYNCD;
636 }
637 } else {
638 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
639 }
640 break;
641
642 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
643
644 MAKE_SOFT_DECISION();
645
646 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
647 if(v < 0) { // logic '0' detected
648 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
649 Demod.posCount = 0; // start of SOF sequence
650 } else {
651 // maximum length of TR1 = 200 1/fs
652 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
653 }
654 ++Demod.posCount;
655 break;
656
657 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
658 ++Demod.posCount;
659
660 MAKE_SOFT_DECISION();
661
662 if(v > 0) {
663 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
664 if(Demod.posCount < 9*2) {
665 Demod.state = DEMOD_UNSYNCD;
666 } else {
667 LED_C_ON(); // Got SOF
668 Demod.state = DEMOD_AWAITING_START_BIT;
669 Demod.posCount = 0;
670 Demod.len = 0;
671 }
672 } else {
673 // low phase of SOF too long (> 12 etu)
674 if (Demod.posCount > 12*2) {
675 Demod.state = DEMOD_UNSYNCD;
676 LED_C_OFF();
677 }
678 }
679 break;
680
681 case DEMOD_AWAITING_START_BIT:
682 ++Demod.posCount;
683
684 MAKE_SOFT_DECISION();
685
686 if (v > 0) {
687 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
688 Demod.state = DEMOD_UNSYNCD;
689 LED_C_OFF();
690 }
691 } else { // start bit detected
692 Demod.bitCount = 0;
693 Demod.posCount = 1; // this was the first half
694 Demod.thisBit = v;
695 Demod.shiftReg = 0;
696 Demod.state = DEMOD_RECEIVING_DATA;
697 }
698 break;
699
700 case DEMOD_RECEIVING_DATA:
701
702 MAKE_SOFT_DECISION();
703
704 if (Demod.posCount == 0) {
705 // first half of bit
706 Demod.thisBit = v;
707 Demod.posCount = 1;
708 } else {
709 // second half of bit
710 Demod.thisBit += v;
711 Demod.shiftReg >>= 1;
712
713 // logic '1'
714 if(Demod.thisBit > 0) Demod.shiftReg |= 0x200;
715
716 ++Demod.bitCount;
717
718 if(Demod.bitCount == 10) {
719
720 uint16_t s = Demod.shiftReg;
721
722 // stop bit == '1', start bit == '0'
723 if((s & 0x200) && !(s & 0x001)) {
724 uint8_t b = (s >> 1);
725 Demod.output[Demod.len] = b;
726 ++Demod.len;
727 Demod.state = DEMOD_AWAITING_START_BIT;
728 } else {
729 Demod.state = DEMOD_UNSYNCD;
730 LED_C_OFF();
731
732 // This is EOF (start, stop and all data bits == '0'
733 if(s == 0) return TRUE;
734 }
735 }
736 Demod.posCount = 0;
737 }
738 break;
739
740 default:
741 Demod.state = DEMOD_UNSYNCD;
742 LED_C_OFF();
743 break;
744 }
745 return FALSE;
746 }
747
748
749 /*
750 * Demodulate the samples we received from the tag, also log to tracebuffer
751 * quiet: set to 'TRUE' to disable debug output
752 */
753 static void GetSamplesFor14443bDemod(int n, bool quiet)
754 {
755 int max = 0;
756 bool gotFrame = FALSE;
757 int lastRxCounter, ci, cq, samples = 0;
758
759 // Allocate memory from BigBuf for some buffers
760 // free all previous allocations first
761 BigBuf_free();
762
763 // The response (tag -> reader) that we're receiving.
764 // Set up the demodulator for tag -> reader responses.
765 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
766
767 // The DMA buffer, used to stream samples from the FPGA
768 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
769
770 // And put the FPGA in the appropriate mode
771 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
772
773 // Setup and start DMA.
774 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
775
776 int8_t *upTo = dmaBuf;
777 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
778
779 // Signal field is ON with the appropriate LED:
780 LED_D_ON();
781 for(;;) {
782 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
783 if(behindBy > max) max = behindBy;
784
785 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1)) > 2) {
786 ci = upTo[0];
787 cq = upTo[1];
788 upTo += 2;
789 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
790 upTo = dmaBuf;
791 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
792 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
793 }
794 lastRxCounter -= 2;
795
796 if(lastRxCounter <= 0)
797 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
798
799 samples += 2;
800
801 //
802 gotFrame = Handle14443bSamplesDemod(ci , cq );
803 if ( gotFrame )
804 break;
805 }
806
807 if(samples > n || gotFrame) {
808 break;
809 }
810 }
811
812 //disable
813 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
814
815 if (!quiet) {
816 Dbprintf("max behindby = %d, samples = %d, gotFrame = %s, Demod.state = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
817 max,
818 samples,
819 (gotFrame) ? "true" : "false",
820 Demod.state,
821 Demod.len,
822 Demod.sumI,
823 Demod.sumQ
824 );
825 }
826
827 //Tracing
828 if (Demod.len > 0)
829 LogTrace(Demod.output, Demod.len, 0, 0, NULL, FALSE);
830 }
831
832
833 //-----------------------------------------------------------------------------
834 // Transmit the command (to the tag) that was placed in ToSend[].
835 //-----------------------------------------------------------------------------
836 static void TransmitFor14443b(void)
837 {
838 int c;
839 volatile uint32_t r;
840 FpgaSetupSsc();
841
842 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
843 AT91C_BASE_SSC->SSC_THR = 0xff;
844
845 // Signal field is ON with the appropriate Red LED
846 LED_D_ON();
847 // Signal we are transmitting with the Green LED
848 LED_B_ON();
849 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
850
851 for(c = 0; c < 10;) {
852 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
853 AT91C_BASE_SSC->SSC_THR = 0xff;
854 ++c;
855 }
856 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
857 r = AT91C_BASE_SSC->SSC_RHR;
858 (void)r;
859 }
860 WDT_HIT();
861 }
862
863 c = 0;
864 for(;;) {
865 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
866 AT91C_BASE_SSC->SSC_THR = ToSend[c];
867 ++c;
868 if(c >= ToSendMax)
869 break;
870 }
871 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
872 r = AT91C_BASE_SSC->SSC_RHR;
873 (void)r;
874 }
875 WDT_HIT();
876 }
877 LED_B_OFF(); // Finished sending
878 }
879
880
881 //-----------------------------------------------------------------------------
882 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
883 // so that it is ready to transmit to the tag using TransmitFor14443b().
884 //-----------------------------------------------------------------------------
885 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
886 {
887 int i, j;
888 uint8_t b;
889
890 ToSendReset();
891
892 // Establish initial reference level
893 for(i = 0; i < 40; i++)
894 ToSendStuffBit(1);
895
896 // Send SOF
897 for(i = 0; i < 10; i++)
898 ToSendStuffBit(0);
899
900 for(i = 0; i < len; i++) {
901 // Stop bits/EGT
902 ToSendStuffBit(1);
903 ToSendStuffBit(1);
904 // Start bit
905 ToSendStuffBit(0);
906 // Data bits
907 b = cmd[i];
908 for(j = 0; j < 8; j++) {
909 if(b & 1)
910 ToSendStuffBit(1);
911 else
912 ToSendStuffBit(0);
913
914 b >>= 1;
915 }
916 }
917 // Send EOF
918 ToSendStuffBit(1);
919 for(i = 0; i < 10; i++)
920 ToSendStuffBit(0);
921
922 for(i = 0; i < 8; i++)
923 ToSendStuffBit(1);
924
925
926 // And then a little more, to make sure that the last character makes
927 // it out before we switch to rx mode.
928 for(i = 0; i < 24; i++)
929 ToSendStuffBit(1);
930
931 // Convert from last character reference to length
932 ++ToSendMax;
933 }
934
935
936 /**
937 Convenience function to encode, transmit and trace iso 14443b comms
938 **/
939 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
940 {
941 CodeIso14443bAsReader(cmd, len);
942 TransmitFor14443b();
943 if (tracing) {
944 //uint8_t parity[MAX_PARITY_SIZE];
945 //LogTrace(cmd,len, 0, 0, parity, TRUE);
946 LogTrace(cmd,len, 0, 0, NULL, TRUE);
947 }
948 }
949
950 /* Sends an APDU to the tag
951 * TODO: check CRC and preamble
952 */
953 int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
954 {
955 uint8_t message_frame[message_length + 4];
956 // PCB
957 message_frame[0] = 0x0A | pcb_blocknum;
958 pcb_blocknum ^= 1;
959 // CID
960 message_frame[1] = 0;
961 // INF
962 memcpy(message_frame + 2, message, message_length);
963 // EDC (CRC)
964 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
965 // send
966 CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
967 // get response
968 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
969 if(Demod.len < 3)
970 return 0;
971
972 // TODO: Check CRC
973 // copy response contents
974 if(response != NULL)
975 memcpy(response, Demod.output, Demod.len);
976
977 return Demod.len;
978 }
979
980 /* Perform the ISO 14443 B Card Selection procedure
981 * Currently does NOT do any collision handling.
982 * It expects 0-1 cards in the device's range.
983 * TODO: Support multiple cards (perform anticollision)
984 * TODO: Verify CRC checksums
985 */
986 int iso14443b_select_card()
987 {
988 // WUPB command (including CRC)
989 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
990 static const uint8_t wupb[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
991 // ATTRIB command (with space for CRC)
992 uint8_t attrib[] = { 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
993
994 // first, wake up the tag
995 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
996 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
997 // ATQB too short?
998 if (Demod.len < 14)
999 return 2;
1000
1001 // select the tag
1002 // copy the PUPI to ATTRIB
1003 memcpy(attrib + 1, Demod.output + 1, 4);
1004 /* copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into
1005 ATTRIB (Param 3) */
1006 attrib[7] = Demod.output[10] & 0x0F;
1007 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
1008 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
1009 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1010 // Answer to ATTRIB too short?
1011 if(Demod.len < 3)
1012 return 2;
1013
1014 // reset PCB block number
1015 pcb_blocknum = 0;
1016 return 1;
1017 }
1018
1019 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
1020 void iso14443b_setup() {
1021
1022 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1023
1024 BigBuf_free(); BigBuf_Clear_ext(false);
1025 DemodReset();
1026 UartReset();
1027
1028 // Set up the synchronous serial port
1029 FpgaSetupSsc();
1030
1031 // connect Demodulated Signal to ADC:
1032 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1033
1034 // Signal field is on with the appropriate LED
1035 LED_D_ON();
1036 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1037 SpinDelay(200);
1038
1039 // Start the timer
1040 StartCountSspClk();
1041 }
1042
1043 //-----------------------------------------------------------------------------
1044 // Read a SRI512 ISO 14443B tag.
1045 //
1046 // SRI512 tags are just simple memory tags, here we're looking at making a dump
1047 // of the contents of the memory. No anticollision algorithm is done, we assume
1048 // we have a single tag in the field.
1049 //
1050 // I tried to be systematic and check every answer of the tag, every CRC, etc...
1051 //-----------------------------------------------------------------------------
1052 void ReadSTMemoryIso14443b(uint32_t dwLast)
1053 {
1054 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1055 clear_trace();
1056 set_tracing(TRUE);
1057
1058 uint8_t i = 0x00;
1059
1060 // Make sure that we start from off, since the tags are stateful;
1061 // confusing things will happen if we don't reset them between reads.
1062 LED_D_OFF();
1063 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1064 SpinDelay(200);
1065
1066 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1067 FpgaSetupSsc();
1068
1069 // Now give it time to spin up.
1070 // Signal field is on with the appropriate LED
1071 LED_D_ON();
1072 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
1073 SpinDelay(200);
1074
1075 // First command: wake up the tag using the INITIATE command
1076 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
1077 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1078 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1079
1080 if (Demod.len == 0) {
1081 DbpString("No response from tag");
1082 set_tracing(FALSE);
1083 return;
1084 } else {
1085 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
1086 Demod.output[0], Demod.output[1], Demod.output[2]);
1087 }
1088
1089 // There is a response, SELECT the uid
1090 DbpString("Now SELECT tag:");
1091 cmd1[0] = 0x0E; // 0x0E is SELECT
1092 cmd1[1] = Demod.output[0];
1093 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1094 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1095 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1096 if (Demod.len != 3) {
1097 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1098 set_tracing(FALSE);
1099 return;
1100 }
1101 // Check the CRC of the answer:
1102 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1103 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1104 DbpString("CRC Error reading select response.");
1105 set_tracing(FALSE);
1106 return;
1107 }
1108 // Check response from the tag: should be the same UID as the command we just sent:
1109 if (cmd1[1] != Demod.output[0]) {
1110 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1111 set_tracing(FALSE);
1112 return;
1113 }
1114
1115 // Tag is now selected,
1116 // First get the tag's UID:
1117 cmd1[0] = 0x0B;
1118 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1119 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
1120 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1121 if (Demod.len != 10) {
1122 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1123 set_tracing(FALSE);
1124 return;
1125 }
1126 // The check the CRC of the answer (use cmd1 as temporary variable):
1127 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1128 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1129 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1130 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1131 // Do not return;, let's go on... (we should retry, maybe ?)
1132 }
1133 Dbprintf("Tag UID (64 bits): %08x %08x",
1134 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1135 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1136
1137 // Now loop to read all 16 blocks, address from 0 to last block
1138 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
1139 cmd1[0] = 0x08;
1140 i = 0x00;
1141 dwLast++;
1142 for (;;) {
1143 if (i == dwLast) {
1144 DbpString("System area block (0xff):");
1145 i = 0xff;
1146 }
1147 cmd1[1] = i;
1148 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1149 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1150 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1151 if (Demod.len != 6) { // Check if we got an answer from the tag
1152 DbpString("Expected 6 bytes from tag, got less...");
1153 return;
1154 }
1155 // The check the CRC of the answer (use cmd1 as temporary variable):
1156 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1157 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1158 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1159 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1160 // Do not return;, let's go on... (we should retry, maybe ?)
1161 }
1162 // Now print out the memory location:
1163 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1164 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1165 (Demod.output[4]<<8)+Demod.output[5]);
1166 if (i == 0xff) {
1167 break;
1168 }
1169 i++;
1170 }
1171
1172 set_tracing(FALSE);
1173 }
1174
1175
1176 //=============================================================================
1177 // Finally, the `sniffer' combines elements from both the reader and
1178 // simulated tag, to show both sides of the conversation.
1179 //=============================================================================
1180
1181 //-----------------------------------------------------------------------------
1182 // Record the sequence of commands sent by the reader to the tag, with
1183 // triggering so that we start recording at the point that the tag is moved
1184 // near the reader.
1185 //-----------------------------------------------------------------------------
1186 /*
1187 * Memory usage for this function, (within BigBuf)
1188 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1189 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1190 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1191 * Demodulated samples received - all the rest
1192 */
1193 void RAMFUNC SnoopIso14443b(void)
1194 {
1195 // We won't start recording the frames that we acquire until we trigger;
1196 // a good trigger condition to get started is probably when we see a
1197 // response from the tag.
1198 int triggered = TRUE; // TODO: set and evaluate trigger condition
1199
1200 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1201 BigBuf_free(); BigBuf_Clear_ext(false);
1202
1203 clear_trace();
1204 set_tracing(TRUE);
1205
1206 // The DMA buffer, used to stream samples from the FPGA
1207 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
1208 int lastRxCounter;
1209 int8_t *upTo;
1210 int ci, cq;
1211 int maxBehindBy = 0;
1212
1213 // Count of samples received so far, so that we can include timing
1214 // information in the trace buffer.
1215 int samples = 0;
1216
1217 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1218 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1219
1220 // Print some debug information about the buffer sizes
1221 Dbprintf("Snooping buffers initialized:");
1222 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1223 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1224 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1225 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1226
1227 // Signal field is off, no reader signal, no tag signal
1228 LEDsoff();
1229
1230 // And put the FPGA in the appropriate mode
1231 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1232 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1233
1234 // Setup for the DMA.
1235 FpgaSetupSsc();
1236 upTo = dmaBuf;
1237 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1238 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
1239 //uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1240
1241 bool TagIsActive = FALSE;
1242 bool ReaderIsActive = FALSE;
1243
1244 // And now we loop, receiving samples.
1245 for(;;) {
1246 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
1247 (ISO14443B_DMA_BUFFER_SIZE-1);
1248 if(behindBy > maxBehindBy) {
1249 maxBehindBy = behindBy;
1250 }
1251
1252 if(behindBy < 2) continue;
1253
1254 ci = upTo[0];
1255 cq = upTo[1];
1256 upTo += 2;
1257 lastRxCounter -= 2;
1258 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
1259 upTo = dmaBuf;
1260 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
1261 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
1262 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
1263 WDT_HIT();
1264 if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) { // TODO: understand whether we can increase/decrease as we want or not?
1265 Dbprintf("blew circular buffer! behindBy=%d", behindBy);
1266 break;
1267 }
1268
1269 if(!tracing) {
1270 DbpString("Trace full");
1271 break;
1272 }
1273
1274 if(BUTTON_PRESS()) {
1275 DbpString("cancelled");
1276 break;
1277 }
1278 }
1279
1280 samples += 2;
1281
1282 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
1283 if (Handle14443bUartBit(ci & 0x01)) {
1284 if(triggered && tracing) {
1285 //LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1286 LogTrace(Uart.output, Uart.byteCnt, samples, samples, NULL, TRUE);
1287 }
1288 /* And ready to receive another command. */
1289 UartReset();
1290 /* And also reset the demod code, which might have been */
1291 /* false-triggered by the commands from the reader. */
1292 DemodReset();
1293 }
1294 if (Handle14443bUartBit(cq & 0x01)) {
1295 if(triggered && tracing) {
1296 //LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1297 LogTrace(Uart.output, Uart.byteCnt, samples, samples, NULL, TRUE);
1298 }
1299 /* And ready to receive another command. */
1300 UartReset();
1301 /* And also reset the demod code, which might have been */
1302 /* false-triggered by the commands from the reader. */
1303 DemodReset();
1304 }
1305 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1306 }
1307
1308 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
1309 // is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
1310 if(Handle14443bSamplesDemod(ci | 0x01, cq | 0x01)) {
1311
1312 //Use samples as a time measurement
1313 if(tracing)
1314 //LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
1315 LogTrace(Demod.output, Demod.len, samples, samples, NULL, FALSE);
1316
1317 triggered = TRUE;
1318
1319 // And ready to receive another response.
1320 DemodReset();
1321 }
1322 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1323 }
1324 }
1325
1326 FpgaDisableSscDma();
1327 LEDsoff();
1328
1329 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
1330 DbpString("Snoop statistics:");
1331 Dbprintf(" Max behind by: %i", maxBehindBy);
1332 Dbprintf(" Uart State: %x", Uart.state);
1333 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1334 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
1335 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1336 set_tracing(FALSE);
1337 }
1338
1339
1340 /*
1341 * Send raw command to tag ISO14443B
1342 * @Input
1343 * datalen len of buffer data
1344 * recv bool when true wait for data from tag and send to client
1345 * powerfield bool leave the field on when true
1346 * data buffer with byte to send
1347 *
1348 * @Output
1349 * none
1350 *
1351 */
1352 void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
1353 {
1354 // param ISO_
1355 // param ISO_CONNECT
1356 // param ISO14A_NO_DISCONNECT
1357 //if (param & ISO14A_NO_DISCONNECT)
1358 // return;
1359 iso14443b_setup();
1360
1361 if ( datalen == 0 && recv == 0 && powerfield == 0){
1362
1363 } else {
1364 clear_trace();
1365 set_tracing(TRUE);
1366 CodeAndTransmit14443bAsReader(data, datalen);
1367 }
1368
1369 if (recv) {
1370 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, FALSE);
1371 uint16_t len = MIN(Demod.len, USB_CMD_DATA_SIZE);
1372 cmd_send(CMD_ACK, len, 0, 0, Demod.output, len);
1373 }
1374
1375 if (!powerfield) {
1376 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1377 FpgaDisableSscDma();
1378 set_tracing(FALSE);
1379 LED_D_OFF();
1380 }
1381 }
1382
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