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1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 // piwi 2018
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // Routines to support ISO 14443B. This includes both the reader software and
10 // the `fake tag' modes.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17
18 #include "iso14443crc.h"
19
20 #define RECEIVE_SAMPLES_TIMEOUT 1000 // TR0 max is 256/fs = 256/(848kHz) = 302us or 64 samples from FPGA. 1000 seems to be much too high?
21 #define ISO14443B_DMA_BUFFER_SIZE 128
22
23 // PCB Block number for APDUs
24 static uint8_t pcb_blocknum = 0;
25
26 //=============================================================================
27 // An ISO 14443 Type B tag. We listen for commands from the reader, using
28 // a UART kind of thing that's implemented in software. When we get a
29 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
30 // If it's good, then we can do something appropriate with it, and send
31 // a response.
32 //=============================================================================
33
34 //-----------------------------------------------------------------------------
35 // Code up a string of octets at layer 2 (including CRC, we don't generate
36 // that here) so that they can be transmitted to the reader. Doesn't transmit
37 // them yet, just leaves them ready to send in ToSend[].
38 //-----------------------------------------------------------------------------
39 static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
40 {
41 int i;
42
43 ToSendReset();
44
45 // Transmit a burst of ones, as the initial thing that lets the
46 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
47 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
48 // so I will too.
49 for(i = 0; i < 20; i++) {
50 ToSendStuffBit(1);
51 ToSendStuffBit(1);
52 ToSendStuffBit(1);
53 ToSendStuffBit(1);
54 }
55
56 // Send SOF.
57 for(i = 0; i < 10; i++) {
58 ToSendStuffBit(0);
59 ToSendStuffBit(0);
60 ToSendStuffBit(0);
61 ToSendStuffBit(0);
62 }
63 for(i = 0; i < 2; i++) {
64 ToSendStuffBit(1);
65 ToSendStuffBit(1);
66 ToSendStuffBit(1);
67 ToSendStuffBit(1);
68 }
69
70 for(i = 0; i < len; i++) {
71 int j;
72 uint8_t b = cmd[i];
73
74 // Start bit
75 ToSendStuffBit(0);
76 ToSendStuffBit(0);
77 ToSendStuffBit(0);
78 ToSendStuffBit(0);
79
80 // Data bits
81 for(j = 0; j < 8; j++) {
82 if(b & 1) {
83 ToSendStuffBit(1);
84 ToSendStuffBit(1);
85 ToSendStuffBit(1);
86 ToSendStuffBit(1);
87 } else {
88 ToSendStuffBit(0);
89 ToSendStuffBit(0);
90 ToSendStuffBit(0);
91 ToSendStuffBit(0);
92 }
93 b >>= 1;
94 }
95
96 // Stop bit
97 ToSendStuffBit(1);
98 ToSendStuffBit(1);
99 ToSendStuffBit(1);
100 ToSendStuffBit(1);
101 }
102
103 // Send EOF.
104 for(i = 0; i < 10; i++) {
105 ToSendStuffBit(0);
106 ToSendStuffBit(0);
107 ToSendStuffBit(0);
108 ToSendStuffBit(0);
109 }
110 for(i = 0; i < 2; i++) {
111 ToSendStuffBit(1);
112 ToSendStuffBit(1);
113 ToSendStuffBit(1);
114 ToSendStuffBit(1);
115 }
116
117 // Convert from last byte pos to length
118 ToSendMax++;
119 }
120
121 //-----------------------------------------------------------------------------
122 // The software UART that receives commands from the reader, and its state
123 // variables.
124 //-----------------------------------------------------------------------------
125 static struct {
126 enum {
127 STATE_UNSYNCD,
128 STATE_GOT_FALLING_EDGE_OF_SOF,
129 STATE_AWAITING_START_BIT,
130 STATE_RECEIVING_DATA
131 } state;
132 uint16_t shiftReg;
133 int bitCnt;
134 int byteCnt;
135 int byteCntMax;
136 int posCnt;
137 uint8_t *output;
138 } Uart;
139
140 /* Receive & handle a bit coming from the reader.
141 *
142 * This function is called 4 times per bit (every 2 subcarrier cycles).
143 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
144 *
145 * LED handling:
146 * LED A -> ON once we have received the SOF and are expecting the rest.
147 * LED A -> OFF once we have received EOF or are in error state or unsynced
148 *
149 * Returns: true if we received a EOF
150 * false if we are still waiting for some more
151 */
152 static RAMFUNC int Handle14443bUartBit(uint8_t bit)
153 {
154 switch(Uart.state) {
155 case STATE_UNSYNCD:
156 if(!bit) {
157 // we went low, so this could be the beginning
158 // of an SOF
159 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
160 Uart.posCnt = 0;
161 Uart.bitCnt = 0;
162 }
163 break;
164
165 case STATE_GOT_FALLING_EDGE_OF_SOF:
166 Uart.posCnt++;
167 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
168 if(bit) {
169 if(Uart.bitCnt > 9) {
170 // we've seen enough consecutive
171 // zeros that it's a valid SOF
172 Uart.posCnt = 0;
173 Uart.byteCnt = 0;
174 Uart.state = STATE_AWAITING_START_BIT;
175 LED_A_ON(); // Indicate we got a valid SOF
176 } else {
177 // didn't stay down long enough
178 // before going high, error
179 Uart.state = STATE_UNSYNCD;
180 }
181 } else {
182 // do nothing, keep waiting
183 }
184 Uart.bitCnt++;
185 }
186 if(Uart.posCnt >= 4) Uart.posCnt = 0;
187 if(Uart.bitCnt > 12) {
188 // Give up if we see too many zeros without
189 // a one, too.
190 LED_A_OFF();
191 Uart.state = STATE_UNSYNCD;
192 }
193 break;
194
195 case STATE_AWAITING_START_BIT:
196 Uart.posCnt++;
197 if(bit) {
198 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
199 // stayed high for too long between
200 // characters, error
201 Uart.state = STATE_UNSYNCD;
202 }
203 } else {
204 // falling edge, this starts the data byte
205 Uart.posCnt = 0;
206 Uart.bitCnt = 0;
207 Uart.shiftReg = 0;
208 Uart.state = STATE_RECEIVING_DATA;
209 }
210 break;
211
212 case STATE_RECEIVING_DATA:
213 Uart.posCnt++;
214 if(Uart.posCnt == 2) {
215 // time to sample a bit
216 Uart.shiftReg >>= 1;
217 if(bit) {
218 Uart.shiftReg |= 0x200;
219 }
220 Uart.bitCnt++;
221 }
222 if(Uart.posCnt >= 4) {
223 Uart.posCnt = 0;
224 }
225 if(Uart.bitCnt == 10) {
226 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
227 {
228 // this is a data byte, with correct
229 // start and stop bits
230 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
231 Uart.byteCnt++;
232
233 if(Uart.byteCnt >= Uart.byteCntMax) {
234 // Buffer overflowed, give up
235 LED_A_OFF();
236 Uart.state = STATE_UNSYNCD;
237 } else {
238 // so get the next byte now
239 Uart.posCnt = 0;
240 Uart.state = STATE_AWAITING_START_BIT;
241 }
242 } else if (Uart.shiftReg == 0x000) {
243 // this is an EOF byte
244 LED_A_OFF(); // Finished receiving
245 Uart.state = STATE_UNSYNCD;
246 if (Uart.byteCnt != 0) {
247 return true;
248 }
249 } else {
250 // this is an error
251 LED_A_OFF();
252 Uart.state = STATE_UNSYNCD;
253 }
254 }
255 break;
256
257 default:
258 LED_A_OFF();
259 Uart.state = STATE_UNSYNCD;
260 break;
261 }
262
263 return false;
264 }
265
266
267 static void UartReset()
268 {
269 Uart.byteCntMax = MAX_FRAME_SIZE;
270 Uart.state = STATE_UNSYNCD;
271 Uart.byteCnt = 0;
272 Uart.bitCnt = 0;
273 }
274
275
276 static void UartInit(uint8_t *data)
277 {
278 Uart.output = data;
279 UartReset();
280 }
281
282
283 //-----------------------------------------------------------------------------
284 // Receive a command (from the reader to us, where we are the simulated tag),
285 // and store it in the given buffer, up to the given maximum length. Keeps
286 // spinning, waiting for a well-framed command, until either we get one
287 // (returns true) or someone presses the pushbutton on the board (false).
288 //
289 // Assume that we're called with the SSC (to the FPGA) and ADC path set
290 // correctly.
291 //-----------------------------------------------------------------------------
292 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
293 {
294 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
295 // only, since we are receiving, not transmitting).
296 // Signal field is off with the appropriate LED
297 LED_D_OFF();
298 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
299
300 // Now run a `software UART' on the stream of incoming samples.
301 UartInit(received);
302
303 for(;;) {
304 WDT_HIT();
305
306 if(BUTTON_PRESS()) return false;
307
308 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
309 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
310 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
311 if(Handle14443bUartBit(b & mask)) {
312 *len = Uart.byteCnt;
313 return true;
314 }
315 }
316 }
317 }
318
319 return false;
320 }
321
322 //-----------------------------------------------------------------------------
323 // Main loop of simulated tag: receive commands from reader, decide what
324 // response to send, and send it.
325 //-----------------------------------------------------------------------------
326 void SimulateIso14443bTag(void)
327 {
328 // the only commands we understand is WUPB, AFI=0, Select All, N=1:
329 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 }; // WUPB
330 // ... and REQB, AFI=0, Normal Request, N=1:
331 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF }; // REQB
332 // ... and HLTB
333 static const uint8_t cmd3[] = { 0x50, 0xff, 0xff, 0xff, 0xff }; // HLTB
334 // ... and ATTRIB
335 static const uint8_t cmd4[] = { 0x1D, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
336
337 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
338 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
339 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
340 static const uint8_t response1[] = {
341 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
342 0x00, 0x21, 0x85, 0x5e, 0xd7
343 };
344 // response to HLTB and ATTRIB
345 static const uint8_t response2[] = {0x00, 0x78, 0xF0};
346
347
348 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
349
350 clear_trace();
351 set_tracing(true);
352
353 const uint8_t *resp;
354 uint8_t *respCode;
355 uint16_t respLen, respCodeLen;
356
357 // allocate command receive buffer
358 BigBuf_free();
359 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
360
361 uint16_t len;
362 uint16_t cmdsRecvd = 0;
363
364 // prepare the (only one) tag answer:
365 CodeIso14443bAsTag(response1, sizeof(response1));
366 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
367 memcpy(resp1Code, ToSend, ToSendMax);
368 uint16_t resp1CodeLen = ToSendMax;
369
370 // prepare the (other) tag answer:
371 CodeIso14443bAsTag(response2, sizeof(response2));
372 uint8_t *resp2Code = BigBuf_malloc(ToSendMax);
373 memcpy(resp2Code, ToSend, ToSendMax);
374 uint16_t resp2CodeLen = ToSendMax;
375
376 // We need to listen to the high-frequency, peak-detected path.
377 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
378 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
379
380 cmdsRecvd = 0;
381
382 for(;;) {
383
384 if(!GetIso14443bCommandFromReader(receivedCmd, &len)) {
385 Dbprintf("button pressed, received %d commands", cmdsRecvd);
386 break;
387 }
388
389 LogTrace(receivedCmd, len, 0, 0, NULL, true);
390
391 // Good, look at the command now.
392 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
393 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
394 resp = response1;
395 respLen = sizeof(response1);
396 respCode = resp1Code;
397 respCodeLen = resp1CodeLen;
398 } else if ( (len == sizeof(cmd3) && receivedCmd[0] == cmd3[0])
399 || (len == sizeof(cmd4) && receivedCmd[0] == cmd4[0]) ) {
400 resp = response2;
401 respLen = sizeof(response2);
402 respCode = resp2Code;
403 respCodeLen = resp2CodeLen;
404 } else {
405 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
406 // And print whether the CRC fails, just for good measure
407 uint8_t b1, b2;
408 if (len >= 3){ // if crc exists
409 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
410 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
411 // Not so good, try again.
412 DbpString("+++CRC fail");
413
414 } else {
415 DbpString("CRC passes");
416 }
417 }
418 //get rid of compiler warning
419 respCodeLen = 0;
420 resp = response1;
421 respLen = 0;
422 respCode = resp1Code;
423 //don't crash at new command just wait and see if reader will send other new cmds.
424 //break;
425 }
426
427 cmdsRecvd++;
428
429 if(cmdsRecvd > 0x30) {
430 DbpString("many commands later...");
431 break;
432 }
433
434 if(respCodeLen <= 0) continue;
435
436 // Modulate BPSK
437 // Signal field is off with the appropriate LED
438 LED_D_OFF();
439 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
440 AT91C_BASE_SSC->SSC_THR = 0xff;
441 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
442
443 // Transmit the response.
444 uint16_t i = 0;
445 for(;;) {
446 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
447 uint8_t b = respCode[i];
448
449 AT91C_BASE_SSC->SSC_THR = b;
450
451 i++;
452 if(i > respCodeLen) {
453 break;
454 }
455 }
456 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
457 volatile uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
458 (void)b;
459 }
460 }
461
462 // trace the response:
463 LogTrace(resp, respLen, 0, 0, NULL, false);
464
465 }
466 }
467
468 //=============================================================================
469 // An ISO 14443 Type B reader. We take layer two commands, code them
470 // appropriately, and then send them to the tag. We then listen for the
471 // tag's response, which we leave in the buffer to be demodulated on the
472 // PC side.
473 //=============================================================================
474
475 static struct {
476 enum {
477 DEMOD_UNSYNCD,
478 DEMOD_PHASE_REF_TRAINING,
479 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
480 DEMOD_GOT_FALLING_EDGE_OF_SOF,
481 DEMOD_AWAITING_START_BIT,
482 DEMOD_RECEIVING_DATA
483 } state;
484 int bitCount;
485 int posCount;
486 int thisBit;
487 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
488 int metric;
489 int metricN;
490 */
491 uint16_t shiftReg;
492 uint8_t *output;
493 int len;
494 int sumI;
495 int sumQ;
496 } Demod;
497
498 /*
499 * Handles reception of a bit from the tag
500 *
501 * This function is called 2 times per bit (every 4 subcarrier cycles).
502 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
503 *
504 * LED handling:
505 * LED C -> ON once we have received the SOF and are expecting the rest.
506 * LED C -> OFF once we have received EOF or are unsynced
507 *
508 * Returns: true if we received a EOF
509 * false if we are still waiting for some more
510 *
511 */
512 static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
513 {
514 int v;
515
516 // The soft decision on the bit uses an estimate of just the
517 // quadrant of the reference angle, not the exact angle.
518 #define MAKE_SOFT_DECISION() { \
519 if(Demod.sumI > 0) { \
520 v = ci; \
521 } else { \
522 v = -ci; \
523 } \
524 if(Demod.sumQ > 0) { \
525 v += cq; \
526 } else { \
527 v -= cq; \
528 } \
529 }
530
531 #define SUBCARRIER_DETECT_THRESHOLD 8
532
533 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
534 #define AMPLITUDE(ci,cq) (MAX(ABS(ci),ABS(cq)) + (MIN(ABS(ci),ABS(cq))/2))
535 switch(Demod.state) {
536 case DEMOD_UNSYNCD:
537 if(AMPLITUDE(ci,cq) > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
538 Demod.state = DEMOD_PHASE_REF_TRAINING;
539 Demod.sumI = ci;
540 Demod.sumQ = cq;
541 Demod.posCount = 1;
542 }
543 break;
544
545 case DEMOD_PHASE_REF_TRAINING:
546 if(Demod.posCount < 8) {
547 if (AMPLITUDE(ci,cq) > SUBCARRIER_DETECT_THRESHOLD) {
548 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
549 // note: synchronization time > 80 1/fs
550 Demod.sumI += ci;
551 Demod.sumQ += cq;
552 Demod.posCount++;
553 } else { // subcarrier lost
554 Demod.state = DEMOD_UNSYNCD;
555 }
556 } else {
557 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
558 }
559 break;
560
561 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
562 MAKE_SOFT_DECISION();
563 if(v < 0) { // logic '0' detected
564 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
565 Demod.posCount = 0; // start of SOF sequence
566 } else {
567 if(Demod.posCount > 200/4) { // maximum length of TR1 = 200 1/fs
568 Demod.state = DEMOD_UNSYNCD;
569 }
570 }
571 Demod.posCount++;
572 break;
573
574 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
575 Demod.posCount++;
576 MAKE_SOFT_DECISION();
577 if(v > 0) {
578 if(Demod.posCount < 9*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
579 Demod.state = DEMOD_UNSYNCD;
580 } else {
581 LED_C_ON(); // Got SOF
582 Demod.state = DEMOD_AWAITING_START_BIT;
583 Demod.posCount = 0;
584 Demod.len = 0;
585 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
586 Demod.metricN = 0;
587 Demod.metric = 0;
588 */
589 }
590 } else {
591 if(Demod.posCount > 12*2) { // low phase of SOF too long (> 12 etu)
592 Demod.state = DEMOD_UNSYNCD;
593 LED_C_OFF();
594 }
595 }
596 break;
597
598 case DEMOD_AWAITING_START_BIT:
599 Demod.posCount++;
600 MAKE_SOFT_DECISION();
601 if(v > 0) {
602 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
603 Demod.state = DEMOD_UNSYNCD;
604 LED_C_OFF();
605 }
606 } else { // start bit detected
607 Demod.bitCount = 0;
608 Demod.posCount = 1; // this was the first half
609 Demod.thisBit = v;
610 Demod.shiftReg = 0;
611 Demod.state = DEMOD_RECEIVING_DATA;
612 }
613 break;
614
615 case DEMOD_RECEIVING_DATA:
616 MAKE_SOFT_DECISION();
617 if(Demod.posCount == 0) { // first half of bit
618 Demod.thisBit = v;
619 Demod.posCount = 1;
620 } else { // second half of bit
621 Demod.thisBit += v;
622
623 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
624 if(Demod.thisBit > 0) {
625 Demod.metric += Demod.thisBit;
626 } else {
627 Demod.metric -= Demod.thisBit;
628 }
629 (Demod.metricN)++;
630 */
631
632 Demod.shiftReg >>= 1;
633 if(Demod.thisBit > 0) { // logic '1'
634 Demod.shiftReg |= 0x200;
635 }
636
637 Demod.bitCount++;
638 if(Demod.bitCount == 10) {
639 uint16_t s = Demod.shiftReg;
640 if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
641 uint8_t b = (s >> 1);
642 Demod.output[Demod.len] = b;
643 Demod.len++;
644 Demod.state = DEMOD_AWAITING_START_BIT;
645 } else {
646 Demod.state = DEMOD_UNSYNCD;
647 LED_C_OFF();
648 if(s == 0x000) {
649 // This is EOF (start, stop and all data bits == '0'
650 return true;
651 }
652 }
653 }
654 Demod.posCount = 0;
655 }
656 break;
657
658 default:
659 Demod.state = DEMOD_UNSYNCD;
660 LED_C_OFF();
661 break;
662 }
663
664 return false;
665 }
666
667
668 static void DemodReset()
669 {
670 // Clear out the state of the "UART" that receives from the tag.
671 Demod.len = 0;
672 Demod.state = DEMOD_UNSYNCD;
673 Demod.posCount = 0;
674 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
675 }
676
677
678 static void DemodInit(uint8_t *data)
679 {
680 Demod.output = data;
681 DemodReset();
682 }
683
684
685 /*
686 * Demodulate the samples we received from the tag, also log to tracebuffer
687 * quiet: set to 'true' to disable debug output
688 */
689 static void GetSamplesFor14443bDemod(int n, bool quiet)
690 {
691 int maxBehindBy = 0;
692 bool gotFrame = false;
693 int lastRxCounter, samples = 0;
694 int8_t ci, cq;
695
696 // Allocate memory from BigBuf for some buffers
697 // free all previous allocations first
698 BigBuf_free();
699
700 // The response (tag -> reader) that we're receiving.
701 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
702
703 // The DMA buffer, used to stream samples from the FPGA
704 uint16_t *dmaBuf = (uint16_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE * sizeof(uint16_t));
705
706 // Set up the demodulator for tag -> reader responses.
707 DemodInit(receivedResponse);
708
709 // wait for last transfer to complete
710 while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXEMPTY))
711
712 // Setup and start DMA.
713 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
714 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
715
716 uint16_t *upTo = dmaBuf;
717 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
718
719 // Signal field is ON with the appropriate LED:
720 LED_D_ON();
721 // And put the FPGA in the appropriate mode
722 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
723
724 for(;;) {
725 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1);
726 if(behindBy > maxBehindBy) {
727 maxBehindBy = behindBy;
728 }
729
730 if(behindBy < 1) continue;
731
732 ci = *upTo >> 8;
733 cq = *upTo;
734 upTo++;
735 lastRxCounter--;
736 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) { // we have read all of the DMA buffer content.
737 upTo = dmaBuf; // start reading the circular buffer from the beginning
738 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
739 }
740 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX)) { // DMA Counter Register had reached 0, already rotated.
741 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; // refresh the DMA Next Buffer and
742 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE; // DMA Next Counter registers
743 }
744 samples++;
745
746 if(Handle14443bSamplesDemod(ci, cq)) {
747 gotFrame = true;
748 break;
749 }
750
751 if(samples > n) {
752 break;
753 }
754 }
755
756 FpgaDisableSscDma();
757
758 if (!quiet) Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", maxBehindBy, samples, gotFrame, Demod.len, Demod.sumI, Demod.sumQ);
759 //Tracing
760 if (Demod.len > 0) {
761 LogTrace(Demod.output, Demod.len, 0, 0, NULL, false);
762 }
763 }
764
765
766 //-----------------------------------------------------------------------------
767 // Transmit the command (to the tag) that was placed in ToSend[].
768 //-----------------------------------------------------------------------------
769 static void TransmitFor14443b(void)
770 {
771 int c;
772
773 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
774
775 // Signal field is ON with the appropriate Red LED
776 LED_D_ON();
777 // Signal we are transmitting with the Green LED
778 LED_B_ON();
779 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
780
781 c = 0;
782 for(;;) {
783 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
784 AT91C_BASE_SSC->SSC_THR = ~ToSend[c];
785 c++;
786 if(c >= ToSendMax) {
787 break;
788 }
789 }
790 WDT_HIT();
791 }
792 LED_B_OFF(); // Finished sending
793 }
794
795
796 //-----------------------------------------------------------------------------
797 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
798 // so that it is ready to transmit to the tag using TransmitFor14443b().
799 //-----------------------------------------------------------------------------
800 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
801 {
802 int i, j;
803 uint8_t b;
804
805 ToSendReset();
806
807 // Send SOF
808 for(i = 0; i < 10; i++) {
809 ToSendStuffBit(0);
810 }
811 ToSendStuffBit(1);
812 ToSendStuffBit(1);
813
814 for(i = 0; i < len; i++) {
815 // Start bit
816 ToSendStuffBit(0);
817 // Data bits
818 b = cmd[i];
819 for(j = 0; j < 8; j++) {
820 if(b & 1) {
821 ToSendStuffBit(1);
822 } else {
823 ToSendStuffBit(0);
824 }
825 b >>= 1;
826 }
827 // Stop bit
828 ToSendStuffBit(1);
829 }
830
831 // Send EOF
832 for(i = 0; i < 10; i++) {
833 ToSendStuffBit(0);
834 }
835 ToSendStuffBit(1);
836
837 // ensure that last byte is filled up
838 for(i = 0; i < 8; i++) {
839 ToSendStuffBit(1);
840 }
841
842 // Convert from last character reference to length
843 ToSendMax++;
844 }
845
846
847 /**
848 Convenience function to encode, transmit and trace iso 14443b comms
849 **/
850 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
851 {
852 CodeIso14443bAsReader(cmd, len);
853 TransmitFor14443b();
854 LogTrace(cmd,len, 0, 0, NULL, true);
855 }
856
857 /* Sends an APDU to the tag
858 * TODO: check CRC and preamble
859 */
860 int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
861 {
862 uint8_t message_frame[message_length + 4];
863 // PCB
864 message_frame[0] = 0x0A | pcb_blocknum;
865 pcb_blocknum ^= 1;
866 // CID
867 message_frame[1] = 0;
868 // INF
869 memcpy(message_frame + 2, message, message_length);
870 // EDC (CRC)
871 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
872 // send
873 CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
874 // get response
875 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
876 if(Demod.len < 3)
877 {
878 return 0;
879 }
880 // TODO: Check CRC
881 // copy response contents
882 if(response != NULL)
883 {
884 memcpy(response, Demod.output, Demod.len);
885 }
886 return Demod.len;
887 }
888
889 /* Perform the ISO 14443 B Card Selection procedure
890 * Currently does NOT do any collision handling.
891 * It expects 0-1 cards in the device's range.
892 * TODO: Support multiple cards (perform anticollision)
893 * TODO: Verify CRC checksums
894 */
895 int iso14443b_select_card()
896 {
897 // WUPB command (including CRC)
898 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
899 static const uint8_t wupb[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
900 // ATTRIB command (with space for CRC)
901 uint8_t attrib[] = { 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
902
903 // first, wake up the tag
904 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
905 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
906 // ATQB too short?
907 if (Demod.len < 14)
908 {
909 return 2;
910 }
911
912 // select the tag
913 // copy the PUPI to ATTRIB
914 memcpy(attrib + 1, Demod.output + 1, 4);
915 /* copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into
916 ATTRIB (Param 3) */
917 attrib[7] = Demod.output[10] & 0x0F;
918 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
919 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
920 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
921 // Answer to ATTRIB too short?
922 if(Demod.len < 3)
923 {
924 return 2;
925 }
926 // reset PCB block number
927 pcb_blocknum = 0;
928 return 1;
929 }
930
931 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
932 void iso14443b_setup() {
933 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
934 // Set up the synchronous serial port
935 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
936 // connect Demodulated Signal to ADC:
937 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
938
939 // Signal field is on with the appropriate LED
940 LED_D_ON();
941 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
942
943 DemodReset();
944 UartReset();
945 }
946
947 //-----------------------------------------------------------------------------
948 // Read a SRI512 ISO 14443B tag.
949 //
950 // SRI512 tags are just simple memory tags, here we're looking at making a dump
951 // of the contents of the memory. No anticollision algorithm is done, we assume
952 // we have a single tag in the field.
953 //
954 // I tried to be systematic and check every answer of the tag, every CRC, etc...
955 //-----------------------------------------------------------------------------
956 void ReadSTMemoryIso14443b(uint32_t dwLast)
957 {
958 uint8_t i = 0x00;
959
960 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
961 // Make sure that we start from off, since the tags are stateful;
962 // confusing things will happen if we don't reset them between reads.
963 LED_D_OFF();
964 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
965 SpinDelay(200);
966
967 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
968 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
969
970 // Now give it time to spin up.
971 // Signal field is on with the appropriate LED
972 LED_D_ON();
973 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
974 SpinDelay(200);
975
976 clear_trace();
977 set_tracing(true);
978
979 // First command: wake up the tag using the INITIATE command
980 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
981 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
982 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
983
984 if (Demod.len == 0) {
985 DbpString("No response from tag");
986 LED_D_OFF();
987 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
988 return;
989 } else {
990 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
991 Demod.output[0], Demod.output[1], Demod.output[2]);
992 }
993
994 // There is a response, SELECT the uid
995 DbpString("Now SELECT tag:");
996 cmd1[0] = 0x0E; // 0x0E is SELECT
997 cmd1[1] = Demod.output[0];
998 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
999 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1000 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1001 if (Demod.len != 3) {
1002 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1003 LED_D_OFF();
1004 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1005 return;
1006 }
1007 // Check the CRC of the answer:
1008 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1009 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1010 DbpString("CRC Error reading select response.");
1011 LED_D_OFF();
1012 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1013 return;
1014 }
1015 // Check response from the tag: should be the same UID as the command we just sent:
1016 if (cmd1[1] != Demod.output[0]) {
1017 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1018 LED_D_OFF();
1019 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1020 return;
1021 }
1022
1023 // Tag is now selected,
1024 // First get the tag's UID:
1025 cmd1[0] = 0x0B;
1026 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1027 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
1028 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1029 if (Demod.len != 10) {
1030 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1031 LED_D_OFF();
1032 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1033 return;
1034 }
1035 // The check the CRC of the answer (use cmd1 as temporary variable):
1036 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1037 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1038 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1039 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1040 // Do not return;, let's go on... (we should retry, maybe ?)
1041 }
1042 Dbprintf("Tag UID (64 bits): %08x %08x",
1043 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1044 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1045
1046 // Now loop to read all 16 blocks, address from 0 to last block
1047 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
1048 cmd1[0] = 0x08;
1049 i = 0x00;
1050 dwLast++;
1051 for (;;) {
1052 if (i == dwLast) {
1053 DbpString("System area block (0xff):");
1054 i = 0xff;
1055 }
1056 cmd1[1] = i;
1057 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1058 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1059 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1060 if (Demod.len != 6) { // Check if we got an answer from the tag
1061 DbpString("Expected 6 bytes from tag, got less...");
1062 LED_D_OFF();
1063 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1064 return;
1065 }
1066 // The check the CRC of the answer (use cmd1 as temporary variable):
1067 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1068 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1069 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1070 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1071 // Do not return;, let's go on... (we should retry, maybe ?)
1072 }
1073 // Now print out the memory location:
1074 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1075 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1076 (Demod.output[4]<<8)+Demod.output[5]);
1077 if (i == 0xff) {
1078 break;
1079 }
1080 i++;
1081 }
1082
1083 LED_D_OFF();
1084 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1085 }
1086
1087
1088 //=============================================================================
1089 // Finally, the `sniffer' combines elements from both the reader and
1090 // simulated tag, to show both sides of the conversation.
1091 //=============================================================================
1092
1093 //-----------------------------------------------------------------------------
1094 // Record the sequence of commands sent by the reader to the tag, with
1095 // triggering so that we start recording at the point that the tag is moved
1096 // near the reader.
1097 //-----------------------------------------------------------------------------
1098 /*
1099 * Memory usage for this function, (within BigBuf)
1100 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1101 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1102 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1103 * Demodulated samples received - all the rest
1104 */
1105 void RAMFUNC SnoopIso14443b(void)
1106 {
1107 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1108 BigBuf_free();
1109
1110 clear_trace();
1111 set_tracing(true);
1112
1113 // The DMA buffer, used to stream samples from the FPGA
1114 uint16_t *dmaBuf = (uint16_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE * sizeof(uint16_t));
1115 int lastRxCounter;
1116 uint16_t *upTo;
1117 int8_t ci, cq;
1118 int maxBehindBy = 0;
1119
1120 // Count of samples received so far, so that we can include timing
1121 // information in the trace buffer.
1122 int samples = 0;
1123
1124 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1125 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1126
1127 // Print some debug information about the buffer sizes
1128 Dbprintf("Snooping buffers initialized:");
1129 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1130 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1131 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1132 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1133
1134 // Signal field is off, no reader signal, no tag signal
1135 LEDsoff();
1136
1137 // And put the FPGA in the appropriate mode
1138 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1139 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1140
1141 // Setup for the DMA.
1142 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
1143 upTo = dmaBuf;
1144 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1145 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
1146
1147 bool TagIsActive = false;
1148 bool ReaderIsActive = false;
1149 // We won't start recording the frames that we acquire until we trigger.
1150 // A good trigger condition to get started is probably when we see a
1151 // reader command
1152 bool triggered = false;
1153
1154 // And now we loop, receiving samples.
1155 for(;;) {
1156 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1);
1157 if(behindBy > maxBehindBy) {
1158 maxBehindBy = behindBy;
1159 }
1160
1161 if(behindBy < 1) continue;
1162
1163 ci = *upTo>>8;
1164 cq = *upTo;
1165 upTo++;
1166 lastRxCounter--;
1167 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) { // we have read all of the DMA buffer content.
1168 upTo = dmaBuf; // start reading the circular buffer from the beginning again
1169 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
1170 if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) {
1171 Dbprintf("About to blow circular buffer - aborted! behindBy=%d", behindBy);
1172 break;
1173 }
1174 }
1175 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX)) { // DMA Counter Register had reached 0, already rotated.
1176 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; // refresh the DMA Next Buffer and
1177 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE; // DMA Next Counter registers
1178 WDT_HIT();
1179 if(BUTTON_PRESS()) {
1180 DbpString("cancelled");
1181 break;
1182 }
1183 }
1184
1185 samples++;
1186
1187 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
1188 if(Handle14443bUartBit(ci & 0x01)) {
1189 triggered = true;
1190 LogTrace(Uart.output, Uart.byteCnt, samples, samples, NULL, true);
1191 /* And ready to receive another command. */
1192 UartReset();
1193 /* And also reset the demod code, which might have been */
1194 /* false-triggered by the commands from the reader. */
1195 DemodReset();
1196 }
1197 if(Handle14443bUartBit(cq & 0x01)) {
1198 triggered = true;
1199 LogTrace(Uart.output, Uart.byteCnt, samples, samples, NULL, true);
1200 /* And ready to receive another command. */
1201 UartReset();
1202 /* And also reset the demod code, which might have been */
1203 /* false-triggered by the commands from the reader. */
1204 DemodReset();
1205 }
1206 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1207 }
1208
1209 if(!ReaderIsActive && triggered) { // no need to try decoding tag data if the reader is sending or not yet triggered
1210 if(Handle14443bSamplesDemod(ci/2, cq/2)) {
1211 //Use samples as a time measurement
1212 LogTrace(Demod.output, Demod.len, samples, samples, NULL, false);
1213 // And ready to receive another response.
1214 DemodReset();
1215 }
1216 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1217 }
1218
1219 }
1220
1221 FpgaDisableSscDma();
1222 LEDsoff();
1223 DbpString("Snoop statistics:");
1224 Dbprintf(" Max behind by: %i", maxBehindBy);
1225 Dbprintf(" Uart State: %x", Uart.state);
1226 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1227 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
1228 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1229 }
1230
1231
1232 /*
1233 * Send raw command to tag ISO14443B
1234 * @Input
1235 * datalen len of buffer data
1236 * recv bool when true wait for data from tag and send to client
1237 * powerfield bool leave the field on when true
1238 * data buffer with byte to send
1239 *
1240 * @Output
1241 * none
1242 *
1243 */
1244 void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
1245 {
1246 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1247 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1248
1249 // switch field on and give tag some time to power up
1250 LED_D_ON();
1251 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_TX);
1252 SpinDelay(10);
1253
1254 if (datalen){
1255 set_tracing(true);
1256
1257 CodeAndTransmit14443bAsReader(data, datalen);
1258
1259 if(recv) {
1260 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, true);
1261 uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1262 cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
1263 }
1264 }
1265
1266 if(!powerfield) {
1267 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1268 LED_D_OFF();
1269 }
1270 }
1271
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